JP2000215677A - Ferroelectric material memory device and method of driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it unnecessary to introduce a refresh cycle from the external side, prevent generation of over-head in velocity assures small power consumption and prevent reduction of polarized amount. SOLUTION: This memory device is formed of a ferroelectric material capacitor 11 holding a ferroelectric material between a couple of electrodes and a cell transistor 12 where the gate terminal is connected to a word line 30, the drain terminal to a bit line 40 and the source terminal to one electrode of the ferroelectric capacitor 11. In this case, a memory cell in which the plate line 50 is connected to the other electrode of the ferroelectric material capacitor 11 is provided with a potential compensation transistor 21 in which the gate terminal is connected to the control line 90, the drain terminal to the source terminal of the cell transistor 12, and the source terminal to the plate line 50. During the power feeding, the plate line 50 is fixed to 1/2 of the power supply level. When the memory cell is non-selected, the source terminal of the cell transistor 12 is set to 1/2 of the power supply level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ferroelectric memory device and a method of driving the same, and more particularly, to a ferroelectric memory device having a fixed plate line potential and a method of driving the same.

[0002]

2. Description of the Related Art Conventionally, in a ferroelectric memory device, it has been pointed out that an increase in cycle time and power consumption and noise generation caused by driving a plate line having a large parasitic capacitance and a large wiring resistance. .

Therefore, a plate line non-driving system has been proposed as a circuit system for solving these problems.

In this plate line non-driving system, the plate line is fixed to Vcc / 2 which is half of the power supply potential Vcc, and the intermediate node where the cell transistor and the capacitor are connected to each other is floating. ing. Therefore, it is necessary to provide a mechanism for compensating the potential of the intermediate node to Vcc / 2 so that the potential of the intermediate node does not become another potential due to leakage. The following two schemes have been proposed.

The first method is a method of refreshing like a dynamic random access memory (DRAM), as disclosed in Japanese Patent Application Laid-Open No. 9-82083, to compensate for a decrease in the potential of the intermediate node due to leakage.

FIG. 4 is a diagram showing a configuration example of a memory cell of a conventional ferroelectric memory device.

In this conventional example, as shown in FIG. 4, a ferroelectric capacitor 1 formed with a ferroelectric material sandwiched between two electrodes is used.
1 and a cell transistor 12 having a gate terminal connected to the word line 30, a drain terminal connected to the bit line 40, and a source terminal connected to one electrode of the ferroelectric capacitor 11. Dielectric capacitor 1
A plate line 50 is connected to one other electrode.
Further, the gate terminal is connected to the precharge line 70a,
A precharge transistor 60a having a drain terminal connected to the bit line 40 and a source terminal connected to GND.
And the gate terminal is connected to the precharge line 70b, the drain terminal is connected to the bit line 40, and the source terminal is
Precharge transistor 60b set to cc / 2
And a sense amplifier 80 for detecting and amplifying the potential output on the bit line 40.

Hereinafter, the operation of the ferroelectric memory device configured as described above will be described.

FIG. 5 is a timing chart for explaining an example of the operation of the ferroelectric memory device shown in FIG. The plate line 50 is fixed at Vcc / 2.

First, the precharge line 70a is connected to the power supply potential V
cc, and the precharge transistor 70a is turned on to precharge the bit line 40 to the GND potential Vss.
The bit line 40 is floated by setting a to a non-conductive state.

Next, the potential of the word line 30 is changed to the GND potential V
ss to Vcc + Vth (Vth: threshold voltage of the cell transistor 12).
2 is made conductive.

Then, a charge corresponding to the polarization state of the ferroelectric capacitor 11 is output to the bit line 40. At this time, if the polarization state of the ferroelectric capacitor 11 is a direction in which the polarization is inverted when the cell transistor 12 is turned on, the potential change amount of the bit line 40 becomes large,
Conversely, if the polarization is not reversed, the potential change amount of the bit line 40 becomes small.

The potential output to the bit line 40 is detected and amplified by a sense amplifier 80.

Thereafter, the read data amplified by the sense amplifier 80 is output to the outside of the memory device via an appropriate buffer (not shown).

When writing to a memory cell, first, a potential corresponding to write data input from outside the memory device is set to the bit line 40.

Next, the precharge line 70b is connected to the power supply potential V.
cc to turn on the precharge transistor 60b, thereby setting the bit line 40 to Vcc / 2, thereby completing rewriting to the memory cell.

Thereafter, the potential of the word line 30 is set to Vcc + Vth
, The cell transistor 12 is turned off, and one operation cycle ends.

Here, if the cell transistor 12 is in a non-conductive state for a long time, the intermediate node 13 becomes the GND potential Vss due to, for example, leakage to the substrate. Therefore, a refresh cycle is provided in which the cell transistor 12 is turned on with the bit line 40 set to Vcc / 2, whereby the intermediate node 13 is set to Vcc /
2 has been compensated.

In the second method, as disclosed in Japanese Patent Publication No. 7-13877, during each operation cycle, all bit lines are connected to Vcc / 2 and all word lines are connected to Vcc / 2 + Vth (Vt).
h: the threshold voltage of the cell transistor) to compensate for the potential drop at the intermediate node due to leakage from the bit line.

FIG. 6 is a timing chart for explaining another example of the operation of the ferroelectric memory device shown in FIG. The plate line 50 is fixed at Vcc / 2.

Before entering the operation cycle, the potential of the bit line 40 is set to Vcc / 2 and the potential of the word line 30 is set to Vcc.
By setting to cc / 2 + Vth, the potential drop due to the leak at the intermediate node 13 is compensated from the bit line 40.

In this state, the cell transistor 12 is turned off by setting the potential of the word line 30 to the GND potential Vss, and then the bit line 40 is once precharged to the GND potential Vss and then floated. I do.

Next, as in the first method described above, the cell transistor 12 is turned on, and a potential corresponding to the polarization state of the ferroelectric capacitor 11 is output on the bit line 40. The output data voltage is detected and amplified by the sense amplifier 80 to perform reading and writing.

Next, the cell transistor 12 is turned off, and thereafter, the potential of the bit line 40 is returned to Vcc / 2 to compensate for the potential drop due to the leakage of the intermediate node 13 from the bit line 40 again. The potential of the word line 30 is set to V
Return to cc / 2 + Vth.

As described above, in the second method, the potential of the intermediate node is compensated during each operation cycle.
It does not require a refresh cycle as in the first method.

In addition to the above-mentioned conventional example, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent No. 40298, in a plate line drive type ferroelectric memory device characterized in that a pulse is simultaneously applied to plate lines of all memory cells, a memory cell not selected by a word line Then
A technique has been proposed in which a short-circuit transistor disposed between two electrodes of a ferroelectric capacitor is made conductive, so that a pulse applied to a plate line does not cause a large potential difference between the electrodes of the ferroelectric capacitor. Have been.

[0027]

However, the above-mentioned conventional ferroelectric memory device has the following problems.

(1) In the device disclosed in Japanese Patent Application Laid-Open No. 9-82083, since a refresh cycle must be externally input, the chip specification becomes complicated.

(2) In the device disclosed in Japanese Patent Publication No. 7-13877, every word line is set from Vcc / 2 + Vth to the GND potential Vss for each operation cycle, and then normal reading and writing are performed. All word lines are changed from GND potential Vss to Vcc / 2 +
An operation of returning to Vth is performed. In this operation, all word lines are set from Vcc / 2 + Vth to GND potential Vss, and all word lines are set from GND potential Vss to Vcc / 2 + V.
In the process of returning to th, speed overhead and power consumption increase.

(3) In the device disclosed in JP-A-3-40298, a change in the potential of the intermediate node is slightly delayed from a change in the potential of the plate line due to the resistance of the short-circuit transistor and the capacitance of the ferroelectric capacitor. A potential difference occurs between the electrodes of the dielectric capacitor, and the amount of polarization of the ferroelectric capacitor changes to the initial state INI.
From.

FIG. 7 is a diagram for explaining a decrease in the amount of polarization that occurs in a ferroelectric memory device having a function of short-circuiting between electrodes.

As shown in FIG. 7, the amount of polarization reduction per cycle is small, but the amount of polarization reduction per cycle is accumulated unless a memory cell is selected by a word line. .

The present invention has been made in view of the above-mentioned problems of the prior art, and does not require an external refresh cycle, does not cause speed overhead, and consumes no power. It is an object of the present invention to provide a ferroelectric memory device which has low power and does not reduce the amount of polarization.

[0034]

According to the present invention, there is provided a ferroelectric capacitor having a ferroelectric material sandwiched between two electrodes, a gate terminal connected to a word line, and a A memory cell having a terminal connected to a bit line, a source terminal connected to one electrode of the ferroelectric capacitor, and the other electrode of the ferroelectric capacitor connected to a plate line is a matrix. In the ferroelectric memory device having a cell array arranged in a matrix, the plate line is fixed to a half of a power supply level during energization, and the cell transistor is turned on when the memory cell is in a non-selected state. And a potential setting unit for setting the source terminal of the power supply to half the power supply level.

Further, when the memory cell is in a non-selected state, the potential setting section short-circuits the two electrodes of the ferroelectric capacitor to set the source terminal of the cell transistor to the power supply level of one. / 2 level.

The potential setting unit is a potential compensation transistor having a gate terminal to which an external control signal is input, a drain terminal connected to a source terminal of the cell transistor, and a source terminal connected to the plate line. There is a feature.

Further, the semiconductor device is characterized by having a precharge transistor for precharging the bit line.

Also, in the method of driving the ferroelectric memory device, the timing of setting the source terminal of the cell transistor to a half of the power supply level and the timing of precharging the bit line are simultaneously performed. It is characterized by the following.

Further, the method of driving the ferroelectric memory device is characterized in that the timing for floating the source terminal of the cell transistor and the timing for floating the bit line are simultaneous.

(Operation) In the present invention configured as described above, the plate line is fixed to a level of 1/2 of the power supply level during energization, and the memory cell is set in the non-selected state by the potential setting unit. In this case, the source terminal of the cell transistor serving as the intermediate node is set to half the power supply level, and the intermediate node is floated only in the memory cell selected by the word line.

As a result, it is sufficient to operate one control line arranged along the word line per cycle, and power consumption can be reduced.

The timing for setting the intermediate node to half the power supply level and the timing for precharging the bit line are set at the same time, and the timing for floating the intermediate node and the timing for floating the bit line. Is possible at the same time,
Even when the potential setting unit is provided, there is no overhead in terms of speed.

In a memory cell not selected by the word line, the potentials of the plate line and the intermediate node are
Since the voltage is fixed to a half of the power supply level, no potential difference occurs between the electrodes of the ferroelectric capacitor, and the amount of polarization does not decrease.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a ferroelectric memory device according to the present invention. FIG. 2 is a block diagram showing a memory cell 10-1 to 10-n and a potential setting section 20 shown in FIG.
It is a figure which shows the circuit structure of -1 to 20-n.

In the present embodiment, as shown in FIG.
And memory cells 10 connected to bit lines 40, respectively.
-1 to 10-n, and potential setting units 20-1 to 20-n connected to the control line 90 and setting the potentials of the memory cells 10-1 to 10-n, respectively. The sense amplifier 80 is connected to the bit line 40.

Further, as shown in FIG.
Reference numerals -1 to 10-n denote a ferroelectric capacitor 11 formed with a ferroelectric material sandwiched between two electrodes, a gate terminal connected to a word line 30, a drain terminal connected to a bit line 40, and a source The terminal includes a cell transistor 12 connected to one electrode of the ferroelectric capacitor 11, and a plate line 50 is connected to the other electrode of the ferroelectric capacitor 11. Further, the potential setting unit 20-
1 to 20-n have their gate terminals connected to the control line 90,
The drain terminal is connected to the source terminal of the cell transistor 12, and the source terminal is composed of the potential compensation transistor 21 connected to the plate line 50. Further, a precharge transistor 60 having a gate terminal connected to the precharge line 70, a drain terminal connected to the bit line 40, and a source terminal connected to GND, and a bit line 4
A sense amplifier 80 is provided for detecting and amplifying the potential output above zero.

The operation of the ferroelectric memory device configured as described above will be described below.

FIG. 3 is a timing chart for explaining the operation of the ferroelectric memory device shown in FIGS. The plate line 50 is fixed at Vcc / 2.

First, the precharge line 70 is connected to the power supply potential Vcc.
, The precharge transistor 60 is turned on to precharge the bit line 40 to the GND potential Vss, and then the precharge transistor 60 is turned off to make the bit line 40 floating.

At the same time, the control line 90 is changed from the power supply potential Vcc to G
By setting the potential at the ND potential Vss, the potential at the source terminal of the cell transistor 12 serving as the intermediate node 13 is changed from Vcc / 2 fixed to floating.

Next, the potential of the word line 30 is changed to the GND potential V
ss to Vcc + Vth (Vth: threshold voltage of the cell transistor 12).
2 is made conductive.

Then, a charge corresponding to the polarization state of the ferroelectric capacitor 11 is output to the bit line 40. At this time, if the polarization state of the ferroelectric capacitor 11 is a direction in which the polarization is inverted when the cell transistor 12 is turned on, the amount of change in the potential of the bit line 40 becomes large, and conversely, in a direction where the polarization is not inverted. If there is, the amount of change in potential of the bit line 40 becomes small.

The potential output to the bit line 40 is detected and amplified by the sense amplifier 80.

Thereafter, the read data amplified by the sense amplifier 80 is output to the outside of the memory device via an appropriate buffer (not shown).

When writing to a memory cell, first, a potential corresponding to write data input from outside the memory device is set to the bit line 40.

Next, the potential of the word line 30 is changed to the power supply potential Vcc.
By returning from + Vth to Vss, the cell transistor 1
2 is turned off.

Thereafter, the bit line 40 is re-precharged to the initial state, and at the same time, the potential compensating transistor 21 is turned on, so that the potential at the source terminal of the cell transistor 12 serving as the intermediate node 13 becomes Vcc / 2.
To complete the rewriting and complete one cycle. Even if the bit line 40 is precharged to the power supply potential Vcc instead of the GND potential Vss, the circuit operation is the same.

It should be noted that the present invention is not limited to the above-described embodiment, and within the scope of the technical idea of the present invention,
It goes without saying that the embodiments can be changed as appropriate.

[0060]

Since the present invention is constructed as described above, there is no need to externally provide a refresh cycle, there is no speed overhead, power consumption is small, and the amount of polarization is small. It will not decrease.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a ferroelectric memory device of the present invention.

FIG. 2 is a diagram illustrating a circuit configuration of a memory cell and a potential setting unit illustrated in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the ferroelectric memory device shown in FIGS. 1 and 2;

FIG. 4 is a diagram showing a configuration example of a memory cell of a conventional ferroelectric memory device.

FIG. 5 is a timing chart for explaining an example of the operation of the ferroelectric memory device shown in FIG.

FIG. 6 is a timing chart for explaining another example of the operation of the ferroelectric memory device shown in FIG. 4;

FIG. 7 is a diagram for explaining a decrease in the amount of polarization that occurs in a ferroelectric memory device having a function of short-circuiting between electrodes.

[Explanation of symbols]

 10-1 to 10-n Memory cell 11 Ferroelectric capacitor 12 Cell transistor 13 Intermediate node 20-1 to 20-n Potential setting unit 21 Potential compensation transistor 30 Word line 40 Bit line 50 Plate line 60 Precharge transistor 70 Precharge Line 80 sense amplifier 90 control line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5B024 AA04 BA02 CA07 5F001 AA17 AB20 AF07 5F083 AD69 FR01 GA01 GA05 GA21 GA30 LA03 LA09 LA12 LA16 LA19

Claims (6)

[Claims] 1. A ferroelectric capacitor formed by sandwiching a ferroelectric material between two electrodes, a gate terminal connected to a word line, a drain terminal connected to a bit line, and a source terminal connected to the ferroelectric material. A ferroelectric memory device comprising a cell array comprising a cell transistor connected to one electrode of a capacitor, and a memory cell in which the other electrode of the ferroelectric capacitor is connected to a plate line in a matrix. The plate line is connected to one-half of the power supply level during energization.
2. A ferroelectric material, comprising: a potential setting section fixed to a level of 2 and setting a source terminal of the cell transistor to a half of the power supply level when the memory cell is in a non-selected state. Memory device. 2. The ferroelectric memory device according to claim 1, wherein the potential setting section short-circuits between two electrodes of the ferroelectric capacitor when the memory cell is in a non-selected state. And a source terminal of the cell transistor is set to a half of the power supply level. 3. The ferroelectric memory device according to claim 2, wherein the potential setting unit receives a control signal from an external device at a gate terminal, connects a drain terminal to a source terminal of the cell transistor, and A ferroelectric memory device, wherein a terminal is a potential compensation transistor connected to the plate line. 4. The ferroelectric memory device according to claim 1, further comprising a precharge transistor for precharging said bit line. 5. The method of driving a ferroelectric memory device according to claim 1, wherein a timing at which a source terminal of the cell transistor is set to a half of the power supply level. And a timing for precharging the bit line at the same time. 6. The method for driving a ferroelectric memory device according to claim 1, wherein a timing for floating the source terminal of the cell transistor and a timing for floating the bit line are provided. And a method for driving a ferroelectric memory device.