JP2000214237A - Semiconductor-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor-testing device capable of successively storing, in a normal order, code data being continuously outputted from a DUT (a device to be tested) in an interleave type digital capture memory without depending on the conditions of a pattern program. SOLUTION: A storage data arrangement distribution means 31 is inserted between an FMUX(fail multiplexer) 50 and first and second DCAPs(digital capture memory), receives first and second phase-splitting storage signals being phase-splitted from a DC(digital comparator), detects an effective signal of the phase-splitting storage signal, and alternately distributes and outputs the above first and second phase-splitting code data corresponding to the effective signal and the phase-splitting storage signal into the first and second DCAPs every time the effective signal is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus having storage means for storing a plurality of bits of code data continuously output from a device under test (DUT) in a storage device. In particular, the present invention relates to a semiconductor test apparatus having an interleaved circuit configuration and storing code data output at high speed from a DUT in a storage device.

[0002]

2. Description of the Related Art There is a device in which a data rate of code data continuously output from a DUT reaches several hundred MHz. In order to be able to store this code data continuously,
Digital capture of a given number of interleaved phases
A storage device that can be stored in a memory is configured. In the following description, a specific example of the number of phases is assumed to be a case of a semiconductor test apparatus having a two-phase interleaved digital capture memory, and a high-speed AD conversion that outputs M = 10-bit parallel code data as a DUT. This will be described below using a specific example of a container. Since the semiconductor test apparatus is well-known and well-known in the art, the description of the entire system is omitted.

First, the configuration of the main part of the digital capture memory of the present application will be described with reference to the main part configuration diagram of FIG. 6 and the timing chart of FIG. The main configuration is composed of a pattern generator PG, a waveform shaper FC, an arbitrary waveform generator AWG, a digital comparator DC, a fail multiplexer FMUX, and digital capture memories DCAP1, DCAP2.

[0004] The pattern generator PG generates a predetermined test pattern for performing a DUT test and supplies it to the FC, AWG and DC. The waveform shaper FC receives a test pattern from the PG and supplies a waveform shaped at a predetermined timing by the TG to a logic input / output terminal of the DUT via a driver. The arbitrary waveform generator AWG is, for example, a high-speed DA converter, and includes code data as a test pattern from the PG or a dedicated storage device (DAW (Digital Arbitr
a) The code data from the Waveform Generator)) is continuously received, converted into a corresponding analog signal, and supplied to an analog input terminal of a DUT which is an AD converter.

The analog comparator converts the output signal of M = 10 bits from the DUT into digital data by two analog comparators on the high side (threshold VOH) / low side (threshold VOL). F
Supply L to DC.

[0006] Digital Comparat
or) DC is 10 × from the analog comparator
Receiving two pieces of digital data FH and FL, and receiving ten pieces of corresponding expected value data EXP on the pattern generator side, the corresponding bits of both signals are subjected to a predetermined logical comparison, and are not matched with the expected value ( FAIL) bit is "
The H level is output, and the bit that matches the expected value (PASS) outputs the L level.
Bit data is output regardless of FAIL / PASS. This output is the code data F converted by the DUT.
It matches D0. At this time, in order to store the code data FD0 in the memory, it is necessary to simultaneously generate the storage signal W0 from DC using one unused comparator channel. For this reason, for example, the mnemonic “Z” is described for the comparator channel and “
It is programmed so that an H "signal is generated.

[0007] The fail multiplexer FMUX receives a high-speed fail data string of several hundred MHz and receives 2
It is alternately distributed to low-speed code data by phase interleaving, and is supplied to DCAP1 and DCAP2 at the subsequent stage. That is, upon receiving the high-speed code data D0 column and the storage signal W0 output from the DC, the two-phase low-speed is alternately distributed by the two-phase interleave by the system clock Sclk which is the test cycle of the semiconductor test apparatus. Code data, ie, ODD data (phase-separated code data) FD
1, EVEN data (phase separation code data) FD2, ODD storage signal (phase separation storage signal) W1, and EVEN storage signal (phase separation storage signal) W2 corresponding to subsequent DCAP1,
Supply to DCAP2. Here, from the viewpoint of the user of the semiconductor test apparatus, it is required not to be conscious of being divided into ODD / EVEN and stored in the memory due to the above-described two-phase interleaving circuit. still,
In addition to the above, the FMUX also has a selector function for assigning a desired pin between an input terminal and an output terminal.

[0008] Digital capture memory (Digita
l Capture Memory) The DCAP 1 is one of two-phase interleaving circuits, and its principal configuration includes a write control unit 51, an address generation unit 61, and a memory unit 71, as shown in FIG. It should be noted that a flip-flop for retiming is actually provided at a predetermined position, and a control circuit such as an address switch for reading from the CPU and initializing writing is provided. It is a complicated configuration with a pipeline configuration in order to
It has been omitted for simplicity.

The write control section 51 supplies a write signal 51s to the memory section 71 each time it receives the ODD storage signal W1 from the FMUX. The write signal 51s
Is also a signal for address increment to the address generator 61. The address generator 61 receives the write signal 51s and increments the value of the address counter. The address value 61s of the address counter is supplied to an address input terminal of the memory unit 71. The initial value of the address counter can be externally reset to zero or set to an arbitrary initial value. The memory unit 71 is D
A memory having a predetermined bit width to be stored corresponding to the UT,
Each time the write signal 51s is generated, the ODD data FD1 from the FMUX is continuously stored in the corresponding address.

The other digital capture memory D
CAP2 is the same as DCAP1, and includes a write control unit 52, an address generation unit 62, and a memory unit 72.
Upon receiving the even data FD2 from the FMUX, the data is continuously stored at a corresponding address.

Next, the above operation will be described with reference to the timing chart of FIG. In this case, it is assumed that valid data to be stored is continuous. First, in the description of the pattern program, it is assumed that the storage signal W0 occurs in the section of FIG. 7A, and the six code data FD0 output from the DUT during this period are D1, D2, D3,
D4, D5, D6, and DCAP1, DCA
It is assumed that the initial values of the address values 61s and 62s of the address generator in P2 have been initialized to "0". DU
A desired signal is applied to the analog signal to be applied to T from the arbitrary waveform generator AWG, and the test is performed.

A device test is executed, and a storage signal W0 is generated in a section where valid data in FIG. 7A is continuous (see FIG. 7B). On the other hand, on the DCAP1 side, the code data FD1 on the odd side D1, D3,
D5 (see FIG. 7E) and the corresponding OD
It receives the D storage signal W1 (see FIG. 7D). And the O
Write signal 51s is generated from DD storage signal W1 (FIG. 7F).
To the address value "0" and the first code data D
1 is stored. The address is incremented by 1 at the trailing edge of the write signal 51s to become the address value "1" (see FIG. 7G).
Thereafter, the code data D3 is similarly changed to the address value "1".
Is stored, and the code data D5 is stored in the address value “2”.

On the other DCAP2 side, D2 and D2, which are the even-numbered EVEN data FD2, are interleaved.
4, D6 (see FIG. 7J) and the corresponding EVEN storage signal W2 (see FIG. 7H). Then, a write signal 52s is generated from the EVEN storage signal W2 (see FIG. 7K), and the first code data D2 is stored in the address value "0". The address is incremented by 1 at the trailing edge of the write signal 52s to become the address value "1" (FIG. 7L
reference). Thereafter, similarly, the code data D4 is stored in the address value "1", and the code data D6 is stored in the address value "2".

By the way, in the conventional configuration, there is a problem that the mnemonic description for giving the storage signal W0 cannot be described at an arbitrary position in the description of the pattern program. This will be described with reference to the timing chart of FIG. In this case, it is assumed that six pieces of valid data to be stored exist discontinuously. Note that D99 in the code data FD0 in FIG. 8 indicates invalid data. It is assumed that the storage signal W0 is not generated at the position shown in FIG. 8B and the storage signal W0 is applied to the position shown in FIG. 8C instead. Then, on the DCAP1 side, the code data D4 and the ODD storage signal W1 are distributed to the position of FIG. 8D, and the code data D6 and the ODD storage signal W1 are further distributed to the position of FIG. 8E.
Is distributed. Conversely, DCA
On the P2 side, the code data D5 and EVE are moved to the position of FIG. 8F.
The N storage signal W2 is distributed. As described above, when the pattern program of the storage signal W0 is described such that the two-phase interleave condition is broken, it is found that there is a problem that the storage is not performed in a normal order. The evaluation analysis of the DUT is considered to be stored alternately in both DCAPs.
An irregular storage in which the storage order is changed is not preferable because normal evaluation analysis cannot be performed.

[0015]

As described above, in the prior art, when code data output discontinuously from the DUT is stored, the code data may not be stored in a normal order in the digital capture memories DCAP1 and DCAP2. There are practical difficulties in this regard. Further, there is a drawback in that when creating a pattern program, it is necessary to create a device test program so as to avoid the above-mentioned difficulties. The problem to be solved by the present invention is to receive code data continuously output from a DUT and store the data in an interleaved digital capture memory in a normal order without depending on the conditions of a pattern program. An object of the present invention is to provide a semiconductor test apparatus that can store data sequentially.

[0016]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, a digital comparator (DC), a fail multiplexer (FMUX),
And a first digital capture memory (DCAP) of a system, and output signals of a plurality of bits having a plurality of bits output from a plurality of pins of the device under test in a predetermined cycle in a test cycle are converted into interleaved data by FMUX. Two-phase first and second phase separation code data FD
1, FD2, and a storage signal indicating code data to be stored, which is output from the DC, is also output as two-phase first and second phase separation storage signals W1 and W2 by the FMUX. In a semiconductor test apparatus which receives the two-phase storage signals and sequentially stores the two-phase code data in a predetermined order in two DCAPs, a storage data alignment / distribution means between the FMUX and the first and second DCAPs The stored data alignment / distribution means 31 receives the phase-separated first and second phase-separated storage signals W1 and W2 from the DC and outputs valid signals of the phase-separated storage signals W1 and W2. Detected, and each time the valid signal is detected, the first and second phase-separated code data FD1 and FD2 corresponding to the valid signal and the phase-separated storage signal are alternately distributed and output to the first and second DCAPs. Is characterized by That is a semiconductor test equipment. According to the above invention, the code data continuously output from the DUT can be received and stored in the interleaved digital capture memories DCAP1 and DCAP2 sequentially in a normal order without depending on the conditions of the pattern program. Semiconductor test apparatus can be realized.

FIG. 2 shows a solution according to the present invention. The above-mentioned stored data aligning / distributing means 31 includes the two-phase code data FD1, FD2 and the two-phase storage signal W
1, the phase timing of W2 is set to one phase-divided clock Hcl.
Timing timing means for timing at k2 (for example, flip
Flops 41 and 43), and a state holding means for alternately distributing and outputting the signals. The two-phase storage signals W1s and W2 are received in response to the two-phase storage signals (W1s and W2) after the timing adjustment.
One of them is inverted every time a valid signal is held, and the state holding means is inverted and held.
s, W2 and the switching signal 45 decoded in a predetermined manner
and a switching decoding section 45 for outputting s and outputting both phase-separated code data (FD1s, FD2) and both phase-separated storage signals (W1s, W2) whose phase timings have been timed from the timing timing means. One phase separation code data (FD1s or FD2) and one phase separation storage signal (W1) corresponding to the switching signal 45s from the decoding unit 45.
s or W2) and outputs it to the first DCAP, and selects the other phase-separated storage signal (W1s or W2) and the other phase-separated code data (FD1s or FD2) to generate the second DCP.
The semiconductor test apparatus described above is provided with switching means 90 (for example, multiplexers 47a, 47b, 48a, 48b) for outputting to the AP.

FIG. 9 shows another solution according to the present invention. Second, in order to solve the above problem, the configuration of the present invention includes a digital comparator (DC), a fail multiplexer (FMUX), and one system of digital capture memory (DCAP). An output signal of a plurality of bits output from a plurality of pins in a predetermined cycle of a test cycle is output as two-phase first and second phase-separated code data FD1 and FD2 divided into interleaved data by the FMUX. DC
The storage signal indicating the code data to be stored, which is output from the storage device, is also a two-phase first and second phase separation storage signal W1, W
2 and outputs the two-phase code data and the two-phase storage signal, and arranges and sequentially stores the two-phase code data in one system DCAP in a test cycle generated by the semiconductor test apparatus. Is applied in the case of a low-speed test cycle equal to or less than 1/2 of the highest-speed test cycle of the semiconductor test apparatus, and is provided with storage data alignment / distribution means inserted between the FMUX and one DCAP. The means receives the phase-separated first and second phase-separated storage signals from the FMUX and the first and second phase-separated storage signals, and alternately switches the two phase-separated signals for each system clock Sclk which is a test cycle. There is a semiconductor test apparatus characterized in that the data is output to one system of DCAP.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

In the present invention, an example of a main configuration of the digital capture memory shown in FIG. 1, an example of an internal configuration of the storage data aligning unit of FIG. 2, an example of an internal configuration of the switching decoder of FIG. 3, and FIG. An example of a timing chart illustrating the phase alignment of the interleaved output by Hclk2, and an example of a timing chart illustrating the operation of the stored data alignment unit in FIG.
This will be described below with reference to FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

As shown in FIG. 1, the configuration of the present invention is a configuration in which stored data sorting and distribution means 31 is added to the conventional components. The stored data alignment / distribution means 31 is inserted between the FMUX and the DCAP, receives the phase-separated storage signals W1 and W2 from DC, and when at least one of the phase-separated storage signals W1 and W2 is a valid signal. , The phase separation code data FD1 and FD2 corresponding to the valid signal and the phase separation storage signal W
1 and W2 are alternately redistributed each time a valid signal is detected and output to DCAP1 and DCAP2.

FIG. 2 shows a specific example of the internal configuration of the storage data sorting / distributing means 31, and further description will be given with reference to the timing charts of FIGS. It is assumed that the storage signal W0 and the code data FD0 (see FIGS. 4C and 4D) in FIG. 4 are generated under the same condition as the conventional condition in FIG.
An example of the internal configuration of the stored data sorting and distribution means 31 is shown in FIG.
As shown in (1), it is composed of a timing adjusting unit 80, a switching decoding unit 45, and a switching unit 90. The timing timing means 80 is composed of, for example, flip-flops 41 and 43, and the phase-separated code data F divided into two phases by the FMUX.
D1, FD2 (see FIG. 4F, K) and the phase separation storage signal W
1. Retiming (time-out) is performed to match one phase timing in W2 (see FIGS. 4E and J) with the phase-divided clock Hclk2 (see FIG. 4A). That is, the flip-flop 41 converts the phase-separated code data FD1 to the phase-divided clock H.
Phase separated code data FD1s retimed by clk2
(See FIG. 4H), and the flip-flop 43 outputs a phase-separated storage signal W1s (see FIG. 4G) obtained by retiming the phase-separated storage signal W1 with the phase-divided clock Hclk2.
As a result, the phase-separated signals are timed at the same timing. The clock supplied to both DCAP1 and DCAP2 is the phase-divided clock H used for retiming.
It goes without saying that clk2 is supplied. At this stage, the output order on one side of the phase separation code data FD1s is D1, D3, D4, D6 (see FIG. 4H), and the output order on the other side of the phase separation code data FD2 is D2, D
99, D5 (see FIG. 4K), which is the same as the conventional one.

The switching decoding unit 45 includes state holding means for alternately distributing and outputting the signals. Upon receiving the two-phase storage signals W1s and W2 (see FIGS. 4G and J) after retiming, one of the switching decoding units 45 receives a valid signal each time. A signal obtained by inverting the state holding means is generated, and the state holding signal and the two-phase storage signal W1s,
Upon receiving W2, the switching signal 45s decoded in a predetermined manner is supplied to the selection control input terminal of the switching means 90. This will be further described with reference to a specific configuration example in FIG. As an example of the switching decoding unit 45, the state holding unit 14
0 and a decoding unit 144. State holding means 140
Consists of XOR gates 141 and 143 and a flip-flop 142 in this specific example. XOR gate 141
Indicates that one of the two phase storage signals W1s and W2 is a valid signal "H".
At this time, the "H" signal is supplied to the next-stage XOR gate 143. The XOR gate 143 is the XOR gate 141 of the preceding stage.
Is "L", the flip-flop 142
, And outputs a signal obtained by inverting the Q output state of the flip-flop 142 in the case of "H". As a result, the Q output state of the flip-flop 142 is inverted only when one of the two phase storage signals W1s and W2 is the valid signal "H". This Q output state is transmitted to the decoding unit 1
44 to the a input terminal. Decoding section 144 receives one phase-separated storage signal W1s at an input terminal b, receives the other phase-separated storage signal W2 at an input terminal c, and outputs switching signal 45s decoded under the decoding conditions shown in the truth table. .
If both of the two phase storage signals W1s and W2 are valid signals, they are decoded so as to be distributed alternately.

Next, the switching means 90 shown in FIG. 2 is a four-system two-input one-output selector.
7a, 47b, 48a and 48b. The multiplexer 47a outputs to the DCAP1, receives the two-phase code data FD1s and FD2, and receives the switching signal 4
When 5s is "L", the phase separation code data FD1s is output, and when the switching signal 45s is "H", the phase separation code data FD2 is output. On the other hand, the multiplexer 47b
Is output to DCAP2, receives the two-phase code data FD1s and FD2, and receives the switching signal 45s
Is "H", the phase separation code data FD1s is output, and when the switching signal 45s is "L", the phase separation code data FD2 is output. Multiplexers 48a, 48b
Is the same as above, and the phase-separation storage signals W1s, W2
DCAP1, DCAP corresponding to the switching signal 45s
Select and output to ACP2.

As a result of the provision of the above configuration, the valid signal is alternately redistributed again to DCAP1 and DCAP2 and output. That is, in FIG. 5, the output order on one side of the phase separation code data FD1s is D1, D3, D4, D6.
(See FIG. 5C). The output sequence on the other side of the phase separation code data FD2 is also D2, D99, D5.
(See FIG. 5E) Although the data sequence was disturbed, the data sequence output after passing through the stored data alignment and distribution means 31 of the present invention is the output sequence of the phase separation code data FD1a output to one DCAP1. Are D1, D3, D5 (FIG. 5)
G), and the output order of the phase separation code data FD2b output to the other DCAP2 is D2, D4, D6
(See FIG. 5J). One of the data strings is an output of an odd-numbered data string, and the other is an even-numbered data string, and is output as a target data string that is alternately arranged.

As an application of the realizing means of the present invention, as shown in FIGS. 9 and 10, there is an application configuration example in which the configuration can be constituted by only one system of DCAP. This is applicable when the system clock Sclk, which is the test cycle, is at a low speed of 1/2 or less. Here, assuming that the duty ratio of the phase-divided clock Hclk2 is 50% (see FIG. 11A), a signal inverting means 46 for inverting and controlling the switching signal 45s output from the switching decoding unit 45 with the phase-divided clock Hclk2 is provided. This is feasible. As a result, FIG.
As shown in the time chart of FIG. 11, both of the phase-separated code data and the phase-separated storage signal (see FIGS. 11B and 11C) are alternately switched according to the “H / L” level of the phase-separated clock Hclk2, and the collected data sequence ( 11D and 11E) and output to DCAP1. Thus, the test cycle is 1
In the case of a low speed of / 2 or less, there is no need to provide two systems of DCAP, and only one system of DCAP is required.

[0027]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, the two-phase storage signals W1 output from the FMUX,
By detecting the presence / absence of a valid signal of W2 and alternately redistributing it into odd / even data strings and supplying the data to DCAP1 and DCAP2, code data is stored discontinuously or intermittently. Even in the case of the usage form, the data is stored sequentially in the two-phase DCAP normally without disturbing the storage order. As a result, a great advantage is obtained in that the difficulty of creating a device test program in consideration of the conventional restrictions when creating a pattern program can be solved. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is an example of a main configuration of a digital capture memory according to the present invention.

FIG. 2 is an example of an internal configuration of a stored data sorting unit in FIG. 1;

FIG. 3 is an example of an internal configuration of a switching decoding unit in FIG. 2;

FIG. 4 is a timing chart showing phase adjustment of an interleave output by Hclk2.

FIG. 5 is a timing chart illustrating the operation of a stored data alignment unit.

FIG. 6 is a configuration example of a main part according to a digital capture memory.

FIG. 7 is a timing chart illustrating the operation of FIG. 6;

FIG. 8 is a timing chart in which a trouble occurs due to the configuration of FIG. 6;

FIG. 9 shows another configuration example in which only one system of DCAP is provided and stored.

FIG. 10 is an example of the internal configuration of a stored data sorting unit in FIG. 9;

FIG. 11 is a timing chart illustrating the operation of FIG.

[Explanation of symbols]

DCAP1, DCAP2 Digital capture memory (DCAP) 31 Stored data alignment / distribution means 41, 43, 142 Flip flop 45 Switching decoder 47a, 47b, 48a, 48b Multiplexer 51, 52 Write controller 61, 62 Address generator 71 , 72 memory unit 80 timing adjusting unit 90 switching unit 140 state holding unit 141, 143 XOR gate 144 decoding unit FC waveform shaper FMUX fail multiplexer PG pattern generator

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Claims (3)

[Claims] 1. A digital comparator (DC), a fail multiplexer (FMUX), and first and second systems of two systems.
Digital capture memory (DCAP), and output signals of a plurality of bits output from a plurality of pins of a device under test (DUT) in a predetermined cycle in a test cycle are phase-separated into interleaved data by the FMUX. A storage signal which is output as two-phase first and second phase-separated code data and which indicates code data to be stored and output from the DC is also used by the FMUX as two-phase first and second phase-separated storage signals. A semiconductor test apparatus for receiving the two-phase code data and the two-phase storage signal, and sequentially storing the two-phase code data in a predetermined order in the two DCAPs; A storage data aligning / distributing unit inserted between the two DCAPs, the storage data aligning / distributing unit receiving the phase-separated first and second phase-separated storage signals from the DC, and storing the phase-separated data; A valid signal of the signal is detected, and each time the valid signal is detected, the first and second phase-separated code data and the phase-separated storage signal corresponding to the valid signal are first and second D signals.
A semiconductor test apparatus for alternately outputting to a CAP. 2. A storage data aligning and distributing means: a timing adjusting means for adjusting the phase timings of the two-phase code data and the two-phase storage signals by one of the divided clocks; and a state holding means for alternately distributing and outputting. Receiving the two-phase storage signal after the timing adjustment, when one of the two-phase storage signals is a valid signal, the state holding means is inverted, and the state holding means and the two-phase storage signal are A switching decoding unit for receiving and outputting a switching signal decoded in a predetermined manner; and receiving the two-phase code data and the two-phase storage signal whose phase timing has been adjusted from the timing adjusting unit, and performing the switching from the switching decoding unit. One phase separation code data and one phase separation storage signal corresponding to the signal are selected and the first D
2. The semiconductor test apparatus according to claim 1, further comprising switching means for outputting to the CAP, selecting the other phase-separated storage signal and the other phase-separated code data and outputting the selected signal to the second DCAP. 3. A digital comparator (DC), a fail multiplexer (FMUX), and one system of digital
A capture memory (DCAP), and an output signal of a plurality of bits having a plurality of bits output from a plurality of pins of a device under test (DUT) in a predetermined cycle in a test cycle.
The MUX outputs two-phase first and second phase-separated code data that are phase-separated into interleaved data, and the storage signal output from the DC and indicating the code data to be stored is also output by the FMUX. (1) A semiconductor test apparatus which outputs as a second phase splitting storage signal, receives both phase splitting code data and both phase splitting storing signals, and aligns and stores both phase splitting code data sequentially in one DCAP. Applied when the test cycle generated by the semiconductor test apparatus is a low-speed test cycle that is equal to or less than half of the maximum test cycle of the semiconductor test apparatus, and the stored data is aligned and distributed between the FMUX and one DCAP. Means for storing and aligning and distributing the stored data.
Upon receiving the phase-separated first and second phase-separation storage signals and the first and second phase-separation storage signals from the MUX, the system alternately switches between the two phase-separated signals for each system clock which is a test cycle to provide one system A semiconductor test apparatus for outputting to a DCAP.