JP2000207276A - Image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate common use of an image forming device from among image forming device development projects and design alterations of the device. SOLUTION: This device has an image formation part which performs image forming operation, a CPU 21 which controls the operation of constituent elements for the image formation by a program, a flash ROM 26 which holds the operation program of the CPU 21, an IC card 19 holding a program which can be downloaded to the flash ROM 26, an IC card connecting means 24 to which the IC card 19 is connected, a detecting means 25 which detects the connection of the IC card, and a nonvolatile memory 27 in which user data are recorded. In this case, the device is provided with an address decoder 23, which logically arranges the flash ROM 26, IC card 19, and nonvolatile memory 27 in the memory map of the CPU 21 and decodes the address signal outputted by the CPU 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image forming apparatus, and more particularly, to an image forming apparatus operated by a CPU program.

[0002]

2. Description of the Related Art In a conventional program control of an image forming apparatus, a program is stored in an EPROM.
Is installed in the device and the program is executed. However, when a program needs to be changed due to a bug or the like, the work of replacing the EPROM has occurred. In this EPROM replacement work, the device must be disassembled to a level at which the ROM can be replaced, and especially when the device is a completed product, the replacement work requires an enormous amount of time.

Recently, in order to reduce the replacement work time,
The program has been stored in the flash ROM. At the time of program update, a method of downloading a program from an external storage device such as an IC card to a flash ROM has been adopted, and the program update work time has been greatly reduced. In this case, the addresses of the flash ROM and the IC card on the memory map are exchanged by connecting the IC card, and the main body starts up by the program of the IC card, and the program is downloaded to the flash ROM.

Further, as a future method of using the IC card, a method of using the IC card as an optional program, such as adding a data table of a main program on a flash ROM, has been considered. In this case, the user is
By connecting the card and using the device, functions other than the standard specifications can be used.

Usually, flash ROMs and IC cards are C
Access to these devices is controlled by a chip select signal generated by decoding an address signal output from the CPU by an address decoder and generating the address signal from the CPU.

In recent developments of image forming apparatuses, circuits such as an address decoder are often incorporated in an ASIC around a CPU in order to maintain confidentiality and reduce costs by consolidating circuits. In addition, for the purpose of quality stabilization and cost reduction by sharing development resources, CPU peripheral AS
A method of commonly using an IC for a plurality of development themes is also generally adopted.

[0007]

When such a development method is adopted, the following problems may occur. As an example, a case will be described in which the above development method is adopted under the following three themes.

Theme A: Want to place a small number of large-capacity devices on the CPU memory map Theme B: Want to place a large number of small-capacity devices on the CPU memory map Want to

When an ASIC having an address decoder is commonly used in these three themes, the number of chip select signal outputs required for the theme B is required as the specifications of the address decoder.
Needed as much as needed. There is no problem if the CPU memory space is infinitely large, but since there is actually only a limited space, it is of course possible to change the capacity of each one, depending on how the circuit is assembled. The relationship between the capacities per unit is generally inversely proportional. Then, in the case where the number of chip select signals required for the address decoder theme B are prepared, the chip select signal is newly added by an external circuit in the theme B and C in order to secure the capacity per one in the theme A. May not be able to secure the number of pieces required for the arrangement.

The present invention has been made to solve these problems. By making it possible to arbitrarily change the size of an address space corresponding to each chip select signal, a large-capacity chip select signal is required. Provide an address decoder that can generate a chip select signal with the optimum capacity for the connected device without the need for an external circuit, etc. An object of the present invention is to provide an image forming apparatus that can be used.

[0011]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an image forming section for performing an image forming operation, and a C for controlling the operation of each component of the image forming by a program.
A PU, a flash ROM holding an operation program of the CPU, an IC card holding a program downloadable to the flash ROM, an IC card connecting means for connecting the IC card, and a detection for detecting connection of the IC card Means and a nonvolatile memory for recording user data, the flash RO
M, an IC card, and a non-volatile memory are logically arranged in a memory map of the CPU, and an address decode for decoding an address signal output from the CPU is provided. Each device is transmitted to each device based on a chip select signal generated by the address decode. Is characterized by controlling the access of the chip and changing the size of the address space corresponding to each chip select signal. The size of the address space corresponding to each chip select signal can be specified by selecting a hard pin connected to the address decoder, or the size of the address space corresponding to each chip select signal can be rewritten by software. This is done by a simple register. Therefore, according to the present invention having such a configuration,
By making it possible to arbitrarily change the size of the address space corresponding to each chip select signal, even when a large-capacity chip select signal is required, an external circuit is not required.
Provided is an address decoder that can generate a chip select signal of a capacity statement optimal for a connected device,
An image forming apparatus capable of easily coping with common use and design change between image forming apparatus development themes can be provided.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image forming section for performing an image forming operation, a CPU for controlling the operation of each component of image formation by a program, a flash ROM for holding an operation program of the CPU, and downloading to the flash ROM In an image forming apparatus having an IC card holding a possible program, an IC card connecting means for connecting the IC card, a detecting means for detecting the connection of the IC card, and a nonvolatile memory for recording user data, The ROM, the IC card, and the nonvolatile memory are logically arranged in a memory map of the CPU, and an address decoder for decoding an address signal output from the CPU is provided.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an image forming apparatus to which the present invention is applied. The image forming apparatus 1 shown in FIG.
Main body control board 11, electrophotographic process unit 12, read control unit 13, write control unit 14, display unit 15, specific switch (hereinafter, referred to as specific SW) 16, power supply 17, power supply switch (hereinafter, referred to as power supply SW) 18, and IC card 19
It is configured to include you. When the image forming apparatus 1 having such a configuration is a digital copier, for example, an image signal read by the reading control unit 13 is sent to the writing control unit 14 via the main body control board 11. Then, an electrostatic latent image is formed according to the image signal sent to the writing control 14, and then the image is formed by the electrophotographic processing unit 12.

FIG. 2 is a block diagram showing the configuration of the main body control board 11 of FIG. The control board 20 shown in FIG.
21, reset IC 22, address decoder 23, IC
Card connector 24, IC card connection detecting means 25, flash ROM 26, SRAM 27, device 28-1
To 28-n. Here, FIG. 3 shows an example of a memory map of the CPU 21 of FIG. Note that T
OTAL is 16 Mbytes. As shown in FIG. 7A, in the case of the theme A described above, the number of devices is 5, and the maximum capacity is 4 Mbytes. As shown in FIG. 3B, in the case of the above-described theme B, the number of devices is 16, and the maximum capacity is 1 Mbyte.

Next, FIGS. 4, 5 and 6 show an example of an address decoder using the present invention. FIG. 4 shows a portion that divides a 16-Mbyte address space of the CPU memory map into 16 parts. Thus, the upper 4bi of the CPU address
By decoding t, 16 decoded signals (X
CS). FIG. 5 shows a register group for setting the size of the address space corresponding to each chip select signal output. When the decoder signal generated in FIG. 4 is output as a chip select signal, which decoder signal is to be made valid is set, and the setting information is set to an area designation signal (XCS0AREA, XCS1AREA,..., X).
CSFAREA). FIG. 6 shows an output controller for each chip select signal. The decode signal (X
CS) and the area designation signal (XCS0AREA, X
CS1AREA, ..., XCSFAREA) AND
By performing -OR, the address space is varied by each chip select signal, and is output as an output of a chip select signal (CS signal).

FIG. 7 shows a register setting state for each CS signal in the case of theme A, and FIG. 8 shows a register setting state for each CS signal in the case of theme B. As can be seen from both figures, the size of the address space corresponding to each chip select signal can be arbitrarily changed.

FIG. 9 is a diagram showing an example of the configuration of the address decoder of the present invention. As shown in the figure, a look-up table for specifying an address space for each chip select signal corresponding to the register group in FIG. 5 according to the connection status of the three power supply terminals 91 to 93 to the power supply / GND. Is determined.

FIG. 10 is a diagram showing another example of the configuration of the address decoder of the present invention. As shown in the figure, a group of registers for specifying an address space for each chip select signal.
The output of the register group corresponding to the register group of FIG. 5 is determined. FIG. 11 is a flowchart showing the operation.
In the figure, the power is turned on (step S101).
Then, the boot program based on the default XCS signal is read (step S102). Here, the output of the default XCS signal is determined by clearing / presetting each flip-flop in response to the input of the power-on reset signal in FIG. Then, a register group is set by software (step S10).
3). After the determination, the XCS signal according to the present invention is output (step S104).

The present invention is not limited to the above embodiment, and needless to say, various modifications and substitutions can be made within the scope of the claims.

[0020]

As described above, according to the present invention,
An image forming unit that performs an image forming operation, a CPU that controls the operation of each component of image forming by a program,
A flash ROM holding an operation program of U, an IC card holding a program downloadable to the flash ROM, an IC card connecting means for connecting the IC card, a detecting means for detecting connection of the IC card, a user In an image forming apparatus having a nonvolatile memory for recording data, a flash ROM, an IC card, and a nonvolatile memory are logically arranged in a memory map of a CPU, and an address decode for decoding an address signal output from the CPU is provided. It is characterized in that access to each device is controlled based on a chip select signal generated by the address decoding, and the size of an address space corresponding to each chip select signal is changed. The size of the address space corresponding to each chip select signal is specified by selecting a hard pin connected to the address decoder, or the size of the address space corresponding to each chip select signal can be rewritten by software. This is done by a simple register. Therefore, according to the present invention having such a configuration, by making it possible to arbitrarily change the size of the address space corresponding to each chip select signal, even when a large-capacity chip select signal is required, an external circuit The present invention provides an address decoder that can generate a chip select signal having an optimal capacity statement for a connected device without the need for an image forming apparatus, and can easily cope with common use and design changes between image forming apparatus development themes. A forming device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image forming apparatus to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a main body control board of FIG. 1;

FIG. 3 is a diagram illustrating an example of a memory map of a CPU in FIG. 2;

FIG. 4 is a diagram showing an example of an address decoder using the present invention.

FIG. 5 is a diagram showing an example of an address decoder using the present invention.

FIG. 6 is a diagram showing an example of an address decoder using the present invention.

FIG. 7 is a diagram illustrating a register setting state for each CS signal in the case of theme A;

FIG. 8 is a diagram showing a register setting state for each CS signal in the case of theme B;

FIG. 9 is a diagram illustrating an example of a configuration of an address decoder according to the present invention.

FIG. 10 is a diagram showing another example of the configuration of the address decoder of the present invention.

FIG. 11 is a flowchart showing an operation by software in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image forming apparatus 11 Main body control board 12 Electrophotographic process part 13 Reading control part 14 Writing control part 15 Display part 17 Power supply 19 IC card

Claims (3)

[Claims] An image forming unit for performing an image forming operation, and a C for controlling the operation of each component of the image forming by a program
A PU, a flash ROM holding an operation program of the CPU, an IC card holding a program downloadable to the flash ROM, an IC card connecting means for connecting the IC card, and a detection for detecting connection of the IC card Means and a non-volatile memory for recording user data, wherein the flash ROM, the IC card, and the non-volatile memory are logically arranged in a memory map of the CPU and output from the CPU. An address decode for decoding an address signal is provided, access to each device is controlled based on a chip select signal generated by the address decode, and a size of an address space corresponding to each chip select signal is changed. Image forming apparatus. 2. The image forming apparatus according to claim 1, wherein a size of an address space corresponding to each chip select signal is designated by selecting a hard pin connected to said address decoder. 3. The image forming apparatus according to claim 1, wherein the size of the address space corresponding to each chip select signal is specified by a register rewritable by software.