JP2000201065A - Logic circuit - Google Patents

Abstract

(57) [PROBLEMS] To realize a logic circuit which has been realized by two transistors with one transistor. SOLUTION: In a logic circuit using a PMOS transistor from which a terminal of a back gate can be taken out independently of another transistor, when the logic of the back gate is "1", it is turned off regardless of the logic of the gate. A logic circuit using a PMOS transistor whose threshold voltage is set so that the logic of the back gate is "0" and the logic is ON when the logic of the gate is "0" and is OFF when the logic of the gate is "1".

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit in which a circuit conventionally constituted by two transistors can be constituted by one transistor.

[0002]

2. Description of the Related Art Conventionally, in a MOS transistor, as shown in FIGS. 7A and 7B, an NMOS transistor T11 and a PMOS transistor T12 shown in FIGS. In general, the substrate potential is fixed at the source potential. For this reason, two transistors of the same polarity are connected as shown in FIG. 7C for series connection and as shown in FIG. 7D for parallel connection. In FIGS. 7A to 7D, 1 to
3 is an input terminal, 4 is an output terminal, and 5 is a ground terminal.

First, FIG. 7 (c) shows two NMOS transistors T11 and T11 'connected in series, their gates connected to input terminals 1 and 2, and the source of one transistor T11 connected to input. The terminal 3 is connected, the drain of the other transistor T11 'is connected to the output terminal 4, and the back gate is connected to the ground terminal 5.

In this circuit, when both input terminals 1 and 2 are connected to a power supply level (Vdd), transistors T11 and T11
11 'is turned on, and conduction between the input terminal 3 and the output terminal 4 is established. When the transistors T11 and T11 'are replaced by PMOS transistors, the same operation is performed when both input terminals 1 and 2 are connected to the ground level (GND).

Next, FIG. 7 (d) shows that NMOS transistors T11 and T11 'are connected in parallel, their gates are connected to input terminals 1 and 2, and both transistors T11 and T1 are connected.
The source of 1 'is connected to the input terminal 3, the drain is connected to the output terminal 4, and the back gate is connected to the ground terminal 5.

In this circuit, when one of the input terminals 1 and 2 is connected to the power supply level (Vdd), the voltage V
The transistor on the side where dd is applied to the gate is turned on, and the input terminal 3 and the output terminal 4 conduct. When the transistors T11 and T11 'are replaced with PMOS transistors, the input terminal 1 or 2 is connected to the ground level (GND).
It operates similarly when connected to.

As described above, conventionally, when one of the three input terminals is configured as an input signal terminal and two as control terminals, a series or parallel connection circuit using two transistors is required. Met.

On the other hand, as a circuit technique for controlling the substrate potential, a dynamic threshold CMOS (DTCMO)
S) Circuit is p.3 of REALIZE's low power consumption high speed LSI technology.
Shown at 41. This circuit is a circuit in which the gate terminal and the substrate terminal of the NMOS transistor T11 are connected as shown in FIG. 7 (e), and the threshold voltage of the transistor T11 becomes higher due to the substrate bias effect due to the gate potential. Or lower.

In FIG. 7E, when the gate is connected to the input terminal 1, the source is connected to the input terminal 3, and the drain is connected to the output terminal 4, the input terminal 1 is set to the power supply level (Vdd). When connected, the transistor T11 is turned on and the threshold voltage is reduced, so that the on-resistance is lower than when the substrate terminal is connected to the source. vice versa,
When the input terminal 1 is connected to the ground level (GND), the transistor T11 is turned off and the threshold voltage is increased, so that the off-resistance is larger than when the substrate terminal is connected to the source.

However, even if this circuit is used, when a logic circuit having three input terminals is constructed, the circuit shown in FIGS.
Similarly, two transistors constituting a series circuit and a parallel circuit are required.

[0011]

As described above, conventionally, when a logic circuit having one input terminal, two control terminals, and one output terminal is configured, two transistors are required. .

An object of the present invention is to enable a logic circuit having one input terminal, two control terminals, and one output terminal to be constituted by one transistor.

[0013]

According to a first aspect of the present invention, there is provided a logic circuit using a PMOS transistor capable of taking out a terminal of a back gate independently of another transistor. Is turned off irrespective of the logic of the gate when the logic is "1", the back gate is logic "0", the logic is on when the logic of the gate is "0", and the logic is off when the logic is "1". It was configured using a PMOS transistor whose value voltage was set.

According to a second aspect of the present invention, there is provided a PMO in which a back gate terminal can be taken out independently of other transistors.
In a logic circuit using an S transistor, when the logic of the back gate is "0", the transistor turns on regardless of the logic of the gate, and when the logic of the back gate is "1" and the logic of the gate is "0", the transistor turns on. And turn off when it is "1"
It was configured using a PMOS transistor whose threshold voltage was set.

According to a third aspect of the present invention, there is provided an NMO in which a back gate terminal can be taken out independently of another transistor.
In a logic circuit using an S transistor, when the logic of the back gate is "0", it turns off regardless of the logic of the gate, and it turns on when the logic of the back gate is "1" and the logic of the gate is "1". To turn off when it is "0"
It was configured using an NMOS transistor whose threshold voltage was set.

According to a fourth aspect of the present invention, an NMO in which a terminal of a back gate can be taken out independently of another transistor is provided.
In the logic circuit using the S transistor, when the logic of the back gate is "1", it turns on regardless of the logic of the gate, and when the logic of the back gate is "0" and the logic of the gate is "1", it turns on. To turn off when it is "0"
It was configured using an NMOS transistor whose threshold voltage was set.

According to a fifth aspect of the present invention, there is provided a PMO in which a terminal of a back gate can be taken out independently of other transistors.
In a logic circuit using S transistors, the threshold voltage when the back gate is Vdd is Vt, and the decrease in the threshold voltage when the back gate is GND is ΔVt.
In this case, a PMOS transistor was used in which Vt was set to satisfy (−Vdd−ΔVt) <Vt <−Vdd.

According to a sixth aspect of the present invention, there is provided a PMO capable of taking out a back gate terminal independently of other transistors.
In a logic circuit using S transistors, the threshold voltage when the back gate is Vdd is Vt, and the decrease in the threshold voltage when the back gate is GND is ΔVt.
In this case, a PMOS transistor is used in which Vt is set to (−Vdd + ΔVt) <Vt <0.

According to a seventh aspect of the present invention, there is provided an NMO in which a back gate terminal can be taken out independently of other transistors.
In a logic circuit using S transistors, the threshold voltage when the back gate is GND is Vt, and the decrease in threshold voltage when the back gate is Vdd is ΔVt.
In this case, the Vt is set using an NMOS transistor in which Vdd <Vt <(Vt + ΔVt).

According to an eighth aspect of the present invention, there is provided an NMO in which the back gate terminal can be taken out independently of other transistors.
In a logic circuit using S transistors, the threshold voltage when the back gate is GND is Vt, and the decrease in threshold voltage when the back gate is Vdd is ΔVt.
In this case, an NMOS transistor was used in which Vt was set to 0 <Vt <(Vt−ΔVt).

A ninth invention is directed to the PMOS transistor of the first or fifth invention and the NM of the eighth invention according to the fourth or other invention.
The back gates of the OS transistors were commonly connected to form a first input terminal, the gates were commonly connected to form a second input terminal, and the drains were commonly connected to form an output terminal.

A tenth invention is directed to the PMOS transistor of the second or sixth invention and the N-type transistor of the third or seventh invention.
By connecting the back gates of the MOS transistors in common,
, The gates are commonly connected to form a second input terminal, and the drains are commonly connected to form an output terminal.

[0023]

FIG. 1 is a diagram showing a logic circuit according to a first embodiment of the present invention. This shows a logic circuit composed of one PMOS transistor T1 having a high threshold voltage. The gate of the transistor T1 is connected to the input terminal 1, the back gate is connected to the input terminal 2, and the source is set to the input terminal 3. The drain is connected to the output terminal 4.

Here, the power supply voltage is Vdd, the threshold voltage of the transistor T1 is Vt, and the decrease in the threshold voltage when the back gate (input terminal 2) is connected to the ground level (GND) is ΔVt. When the threshold voltage Vt
Is set to (−Vdd−ΔVt) <Vt <−Vdd. For example, Vdd = 0.4V, ΔVt = 0.2
When V, Vt = -0.5V.

Now, let Vdd be logic "1" and GND be logic "0". When the back gate (input terminal 2) is logic "1" when the source (input terminal 3) is logic "1", the transistor T1 is equivalent to the back gate connected to the source. The threshold voltage is Vt
Since | Vdd | <| Vt |, the gate (input terminal 1) is logic “1”,
Regardless of which of "0", the transistor T1 remains off.

Next, if the back gate (input terminal 2) is logic "0", the threshold voltage of the transistor T1 becomes Δ
Since Vt + ΔVt | <Vdd, the transistor T1 is turned on when the gate (input terminal 1) is at logic “0”, but not turned on when it is at logic “1”.

That is, the transistor T1 is turned on only when the signals at the input terminals 1 and 2 both become logic "0", and turned off otherwise. This is the same operation as the logical operation when the NMOS transistors T11 and T11 'in FIG. 7C are replaced with PMOS transistors.

[Embodiment 2] FIG. 2 shows Embodiment 2 of the present invention.
FIG. 3 is a diagram showing a logic circuit of FIG. This shows a logic circuit composed of one PMOS transistor T2 having a low threshold voltage. The gate of the transistor T2 is connected to the input terminal 1, the back gate is connected to the input terminal 2, and the source is set to the input terminal 3. The drain is connected to the output terminal 4.

Here, the threshold voltage Vt is set to (−Vdd + ΔVt) <Vt <0. For example, when Vdd = 0.4V and ΔVt = 0.2V, Vt = −0.1V.

Now, logic (1) is applied to the source (input terminal 3).
When the back gate (input terminal 2) is logic "1" when the signal of (1) is applied, the transistor T1 is equivalent to the back gate connected to the source, the threshold voltage is Vt, and | Since Vt | <| Vdd |, the transistor T1 is turned on when the input terminal 1 is at logic "0", and turned off when it is at logic "1".

Next, if the back gate (input terminal 2) is logic "0", the threshold voltage of the transistor T1 becomes Δ
Vt, and 0 <| Vt + ΔVt |, so that the transistor T1 is turned on regardless of whether the input terminal 1 is logic “0” or “1”.

That is, the transistor T2 is turned off only when the signals at the input terminals 1 and 2 are both logic "1", and turned on otherwise. This is because the NMOS transistors T11 and T11 'of FIG.
Is replaced by a PMOS transistor.

[Embodiment 3] FIG. 3 shows Embodiment 3 of the present invention.
FIG. 3 is a diagram showing a logic circuit of FIG. This shows a logic circuit composed of one NMOS transistor T3 having a high threshold voltage. The gate of the transistor T3 is the input terminal 1, the back gate is the input terminal 2, and the source is the input terminal 3. The drain is connected to the output terminal 4.

Here, the power supply voltage is Vdd, the threshold voltage of the transistor T3 is Vt, and the decrease in the threshold voltage when the back gate (input terminal 2) is connected to the power supply level (Vdd) is ΔVt. When the threshold voltage Vt
Is set to Vdd <Vt <(Vt + ΔVt). For example, Vdd = 0.4V, ΔVt = 0.2
When V, Vt = 0.5V.

Now, the source (input terminal 3) is at logic "0".
, The back gate (input terminal 2) is at logic “0”.
Then, the transistor T3 is equivalent to the back gate connected to the source, the threshold voltage of which is Vt, and Vdd <Vt, so that the gate (input terminal 1) has a logic "1",
Regardless of which of "0", the transistor T1 remains off.

Next, if the back gate (input terminal 2) is logic "1", the threshold voltage of the transistor T3 becomes Δ
Since Vt decreases by (Vt−ΔVt) <Vdd, the transistor T3 is turned on when the gate (input terminal 1) is at logic “1”, but is turned off when it is at logic “0”.

That is, the transistor T3 is turned on only when the signals at the input terminals 1 and 2 are both at logic "1", and is turned off otherwise. This is an operation equivalent to the logical operation of FIG. 7C described above.

[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.
FIG. 3 is a diagram showing a logic circuit of FIG. This shows a logic circuit composed of one NMOS transistor T4 having a low threshold voltage. The gate of the transistor T4 is connected to the input terminal 1, the back gate is connected to the input terminal 2, and the source is set to the input terminal 3. The drain is connected to the output terminal 4.

Here, the threshold voltage Vt is set to 0 <Vt <(Vdd-ΔVt). For example, when Vdd = 0.4V and ΔVt = 0.2V, Vt = 0.1V.

Now, logic "0" is applied to the source (input terminal 3).
When the back gate (input terminal 2) is at logic "0" when the signal of (1) is applied, the transistor T4 is equivalent to the back gate connected to the source, and its threshold voltage is Vt. Since <Vdd, the transistor T1 is turned on when the input terminal 1 is at logic "1", and turned off when the input terminal 1 is at logic "0".

Next, if the back gate (input terminal 2) is logic "1", the threshold voltage of the transistor T4 becomes Δ
Since Vt decreases by (Vt−ΔVt) <0, the transistor T4 is turned on regardless of whether the input terminal 1 is at logic “0” or “1”.

That is, the transistor T4 is turned off only when the signals at the input terminals 1 and 2 both become logic "0", and turned on otherwise. This is an operation equivalent to the above-described logical operation of FIG.

[Fifth Embodiment] FIG. 5A shows a logic circuit according to a fifth embodiment of the present invention. Here, the high threshold voltage PMOS transistor T1 shown in FIG.
The NOR circuit is constituted by using the low threshold voltage NMOS transistor T4 shown in FIG. That is, the back gates of the transistors T1 and T4 are connected to the input terminal 11,
The gate is connected to the input terminal 12, the drain is connected to the output terminal 13, the source of the transistor T1 is connected to the power supply terminal 14, and the source of the transistor T4 is connected to the ground terminal 15.

The high threshold PMOS transistor T1 is
When the input terminal 11 is at logic "1", it is turned off regardless of the logic of the input terminal 12, and when the input terminal 11 is at logic "0", it is turned on only when the input terminal 12 is at logic "0".

When the input terminal 11 is at logic "1", the input terminal 12 is turned on irrespective of the logic "1" or "0" of the low threshold transistor T4, and the input terminal 11 is at logic "0". In the case of, it is turned on only when the input terminal 12 is at logic "1".

Therefore, only when both the input terminals 11 and 12 are at logic "0", the logic at the output terminal 13 becomes "1", otherwise it becomes "0" and the NOR operation is realized. That is, the function of the conventional NOR circuit shown in FIG. 5B can be realized with two transistors. FIG.
In (b), T21 and T22 are PMOS transistors, and T23 and T24 are NMOS transistors.

[Sixth Embodiment] FIG. 6A shows a logic circuit according to a fourth embodiment of the present invention. Here, the low threshold voltage PMOS transistor T2 shown in FIG.
The NAND circuit is configured using the NMOS transistor T3 having the high threshold voltage shown in FIG. That is, the back gates of the transistors T2 and T3 are connected to the input terminal 11
The gate to the input terminal 12 and the drain to the output terminal 13
And the source of the transistor T2 is connected to the power terminal 14
The source of the transistor T3 is connected to the ground terminal 15.

The low threshold PMOS transistor T2 is
When the input terminal 11 is at logic "0", it is turned on regardless of the logic of the input terminal 12, and when the input terminal 11 is at logic "1", it is turned on only when the input terminal 12 is at logic "0".

When the input terminal 11 is at logic "0", the input terminal 12 is turned off irrespective of the logic "1" or "0", and the input terminal 11 is at logic "1". In the case of, it is turned on only when the input terminal 12 is at logic "1".

Therefore, only when both the input terminals 11 and 12 are at logic "1", the logic at the output terminal 13 becomes "0", otherwise, it becomes "1" and the NAND operation is realized. That is, the function of the conventional NAND circuit shown in FIG. 6B can be realized with two transistors. In FIG. 6B, T31 and T32 are PMOS transistors, and T33 and T34 are NMOS transistors.

[0051]

As described above, according to the present invention, the conventional CMO
The number of transistors required in the S logic circuit can be reduced by half.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram according to a fourth embodiment of the present invention.

FIG. 5A is a circuit diagram of a fifth embodiment of the present invention, and FIG. 5B is a circuit diagram of a conventional example having the same function.

FIG. 6A is a circuit diagram of a sixth embodiment of the present invention, and FIG. 6B is a circuit diagram of a conventional example having the same function.

FIGS. 7A to 7E are explanatory diagrams of connection of a conventional transistor.

[Explanation of symbols]

 1-3, 11, 12: input terminal 4, 13: output terminal 5, 14: power supply terminal 15: ground terminal

Claims (10)

[Claims] In a logic circuit using a PMOS transistor whose terminal of a back gate can be taken out independently of another transistor, when the logic of the back gate is "1", it turns off regardless of the logic of the gate; A logic circuit using a PMOS transistor whose threshold voltage is set so that the logic of the back gate is "0" and the logic is on when the logic of the gate is "0" and turned off when the logic of the gate is "1". . 2. A logic circuit using a PMOS transistor capable of taking out a terminal of a back gate independently of another transistor. When the logic of the back gate is "0", the logic circuit is turned on regardless of the logic of the gate. A PMOS transistor whose threshold voltage is set so that the logic of the back gate is "1" and the logic of the gate is "0", and the logic is ON and the logic of the gate is OFF when the logic is "1". circuit. 3. A logic circuit using an NMOS transistor from which a terminal of a back gate can be taken out independently of another transistor, wherein when the logic of the back gate is "0", it turns off regardless of the logic of the gate. An NMOS transistor whose threshold voltage is set so that the logic of the back gate is "1" and the logic of the gate is "1" and turned on when the logic of the gate is "0" and turned off when the logic is "0". circuit. 4. A logic circuit using an NMOS transistor from which a terminal of a back gate can be taken out independently of another transistor, wherein when the logic of the back gate is "1", it turns on regardless of the logic of the gate. An NMOS transistor whose threshold voltage is set so that the logic of the back gate is "0" and the logic of the gate is "1" and turned on and the logic of the gate is turned off when the logic is "0". circuit. 5. A logic circuit using a PMOS transistor capable of taking out a terminal of a back gate independently of another transistor, wherein the threshold voltage when the back gate is at Vdd is V.
t, when a decrease in the threshold voltage when the back gate is GND is ΔVt, a PMOS transistor in which the Vt is set to (−Vdd−ΔVt) <Vt <−Vdd is used. Logic circuit. 6. A logic circuit using a PMOS transistor capable of taking out a terminal of a back gate independently of another transistor, wherein the threshold voltage when the back gate is Vdd is V.
t, a logic circuit using a PMOS transistor in which Vt is set to (−Vdd + ΔVt) <Vt <0, where ΔVt is a decrease in threshold voltage when the back gate is GND. 7. A logic circuit using an NMOS transistor capable of taking out a terminal of a back gate independently of another transistor, wherein the threshold voltage when the back gate is GND is V
t, a logic circuit using an NMOS transistor in which Vt is set to Vdd <Vt <(Vt + ΔVt), where ΔVt is a decrease in threshold voltage when the back gate is at Vdd. 8. A logic circuit using an NMOS transistor capable of taking out a terminal of a back gate independently of another transistor, wherein the threshold voltage when the back gate is GND is V
t, a logic circuit using an NMOS transistor in which Vt is set to 0 <Vt <(Vt−ΔVt), where ΔVt is a decrease in threshold voltage when the back gate is at Vdd. 9. The PMOS transistor according to claim 1 or 5 and the back gate of the NMOS transistor according to claim 4 or 8 are commonly connected to form a first input terminal, and the gates are commonly connected to form a second input terminal. And a drain commonly connected to form an output terminal. 10. The PMOS transistor according to claim 2 or 6 and the back gate of the NMOS transistor according to claim 3 or 7 are commonly connected to form a first input terminal, and the gates are commonly connected to form a second input terminal. And a drain commonly connected to form an output terminal.