JP2000200884A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable transistors to be easily connected together by wiring. SOLUTION: A semiconductor device comprises an element which is equipped with a first insulating film formed on a semiconductor substrate 1, a gate electrode G formed on the first insulating film, an opening 9a provided inside the gate electrode G, a first impurity region 10 formed inside the semiconductor substrate 1 under the opening 9a, and a second impurity region 11 formed in a region outside the gate electrode G. By this setup, a channel region which carriers pass through is formed between the first impurity region 10 and the second impurity region 11. When the elements are provided to form a memory cell, the second impurity regions 11 of them are connected together to be used as a common line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art DRAMs and SRAs are used as semiconductor memory devices.
M, flash memory, and the like. DRAM is MOS
It is common to have a memory cell in which a capacitor is connected to a transistor. Among the elements constituting the MOS transistor, the gate electrode is formed integrally with the word line, and one of the two impurity diffusion layers is connected to a capacitor, and the other is connected to a bit line. In general, the bit line is configured to be drawn out from the impurity diffusion layer onto the field insulating film, or to be drawn out from the impurity diffusion layer through the contact hole onto the interlayer insulating film. These techniques are described in, for example, JP-A-62-145765 and JP-A-3-270168.
No., published in Japanese Unexamined Patent Publication No.

[0003]

However, when the bit lines are arranged along the field insulating film, the area of the field insulating film is limited by the bit lines. Further, when the bit line is formed on the interlayer insulating film, the bit line is drawn upward from between the capacitors, which causes a reduction in the area of the capacitor. The purpose of the present invention is
An object of the present invention is to provide a semiconductor device capable of further promoting integration and a method for manufacturing the same.

[0004]

SUMMARY OF THE INVENTION The above objects are attained by a first insulating film formed on a semiconductor substrate, a gate electrode formed on the first insulating film, and a gate electrode formed inside the gate electrode. A semiconductor device comprising: an element having an opening, a first impurity region formed in the semiconductor substrate below the opening, and a second impurity region formed in a region outside the gate electrode. Settle by device. In the above-described semiconductor device, an annular channel region exists between the first impurity region and the second impurity region. In the above-described semiconductor device, the element includes:
It is a MOS transistor. In this case, the plurality of MOS transistors are formed on the semiconductor substrate, and the plurality of MOS transistors are
They may be connected to each other via an impurity region. In the above-described semiconductor device, a capacitor is connected to the second impurity region.
In the above-described semiconductor device, a floating gate and a second insulating film are sequentially formed between the gate electrode and the first insulating film from the semiconductor substrate side. Next, the operation of the present invention will be described. According to the present invention, there is provided an element in which an opening is formed in a gate electrode, a first impurity region is formed in a semiconductor substrate below the opening, and a second impurity region is formed in the semiconductor substrate around the gate electrode. That is, a channel region through which carriers pass is formed between the first impurity region and the second impurity region. When a memory cell is formed by forming a plurality of such elements, the second impurity regions can be connected to each other and used as a common line, and the common line can be formed on a field insulating film, This eliminates the need for formation on an element, which contributes to higher integration of a semiconductor device.

[0005]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. 1 to 3 are plan views showing an embodiment of the present invention, FIGS. 4 to 6 are cross-sectional views taken along line II of the embodiment of the present invention, and FIGS. 7 to 9 are embodiments of the present invention. FIG. 2 is a sectional view taken along line II-II in FIG. First, FIG.
And one conductivity type (p-type or n-type) as shown in FIG.
In a main surface of a silicon substrate (semiconductor substrate) 1, a first field insulating film 2 called LOCOS is formed in a region surrounding a plurality of stripe-shaped first regions A extending in the X-ray direction.
To form The LOCOS is formed by oxidizing the surface of the silicon substrate 1 using a silicon nitride mask (not shown). Note that before forming the first field insulating film 2, one conductivity type impurity for channel cutting may be ion-implanted into the silicon substrate 1 in a region not covered by the mask. With the mask removed, FIGS.
As shown in FIG. 1A, a thin base oxide film 3 is formed on the surface of the silicon substrate 1 in the first region A.

Next, a silicon nitride film 4 is formed on the first field insulating film 2 and the silicon substrate 1. And
By patterning the silicon nitride film 4 by a photolithography method, as shown in FIGS. 4B and 7B, the second region B is separated from the edge of the first field oxide film 2 by a predetermined distance. Is a striped silicon nitride film 4 extending in the X direction. The second area B is the first area A
It is a region that is narrower than the first region A and is set inside both edges of the first region A. Then, as shown in FIG. 4B, using the silicon nitride film 4 and the first field insulating film 2 as a mask, a reverse conductive region is formed in a region between the first field insulating film 2 and the silicon nitride film 4. Ion implantation of a mold impurity. Thereby, opposite conductivity type regions are formed at both edges of the first region A. The impurity of the opposite conductivity type is an n-type impurity such as arsenic or phosphorus when the silicon substrate 1 is p-type, and a p-type impurity such as boron when the silicon substrate 1 is n-type. . Subsequently, as shown in FIG. 4C, the surface of the silicon substrate 1 is thermally oxidized by using the stripe-shaped silicon nitride film 4 as an oxidation-resistant mask. Thereby, the thickness of the first field insulating film 2 is increased and the first region A
Among them, the surface of the silicon substrate 1 not covered with the silicon nitride film 4 is thermally oxidized to form a second field oxide film 5. The second field insulating film 5 is thinner than the first field insulating film 2 and the first field insulating film 2
From the edge of the first region A.
Note that a first impurity diffusion layer 6 is formed below the second field oxide film 5. Thereafter, when the silicon nitride film 4 is selectively removed with phosphoric acid or the like, its planar shape becomes a state as shown in FIG. 1B, and the second region B of the silicon substrate 1 is substantially exposed.

Next, after the underlying oxide film 3 is removed with a hydrofluoric acid solution, the silicon substrate 1 exposed from the first region A is removed.
A gate insulating film 7 is formed on the surface of the substrate. Gate insulating film 7
Uses, for example, silicon oxide formed by thermal oxidation or the like. Subsequently, as shown in FIGS. 5A and 8A, a conductive film (for example, a silicon film containing impurities) is formed on the first and second field insulating films 2 and 5 and the gate insulating film 7. 8 is formed by a CVD method, and a coating insulating film 9 made of silicon nitride, silicon oxide, or silicon nitride oxide is formed on the conductive film 8 by a CVD method. continue,
The coating insulating film 9 and the conductive film 8 are continuously patterned by a photolithography method, and are patterned as shown in FIGS.
(B) As shown in FIG. 8B, the conductive film 8 is patterned into a shape of a word line WL extending in a substantially stripe shape in the Y direction (that is, the direction intersecting the X direction). A plurality of word lines WL are formed in parallel in the X direction at intervals. The covering insulating film 9 is formed on the word line WL.
Exists. The word line WL functions as the gate electrode G in the second region B. The gate electrode G has an opening 9a inside the second region B. For example, the gate electrode G
May have a substantially round shape having an opening 9a at the center as shown in FIG. 2A, or a stripe shape having a slit (rectangular) opening (not shown). . In FIG. 2A, the gate electrolyte G has a shape like a ring that swells in the X direction more than the word line WL.

Next, as shown in FIGS. 5 (c) and 8 (c), using the covering insulating film 9, the gate electrode G, the first and second field oxide films 2, 5 as a mask, A region of the second region B that is not covered by the gate electrode G, that is, the gate electrode G
The impurity of the opposite conductivity type is ion-implanted into the silicon substrate 1 in the peripheral region and the region in the opening 9a. A second impurity diffusion layer 10 is formed on the silicon substrate 1 below the opening 9 of the silicon substrate 1 into which the impurity has been implanted, and a third impurity diffusion layer 10 is formed on the silicon substrate 1 around the gate electrode G. The diffusion layer 11 is formed. Thus, as shown in FIG. 2A, the MOS transistor T is formed by the gate insulating film 3, the gate electrode G, and the second and third impurity diffusion layers 10 and 11.
r is configured. In the MOS transistor Tr, a voltage is applied between the second and third impurity diffusion layers 10 and 11 and the voltage of the gate electrode G is controlled, so that the second and third impurity diffusion layers 10 and 11 The movement of carriers between them is controlled. Since the third impurity diffusion region 11 is connected to the first impurity diffusion layer 6, the third impurity diffusion layer 11 of each of the plurality of MOS transistors Tr formed in one second region B has the third impurity diffusion region. 2 field insulating film 5
Are connected to each other through a first impurity diffusion layer 6 below the first impurity diffusion layer 6. Accordingly, the outer peripheral shape of the channel region of the MOS transistor Tr around the first impurity diffusion layer 6 is substantially circular, square, rhombic, or the like. Also, the first
The impurity diffusion layer 6 and the third impurity diffusion layer 11 are bulk wirings and are used as bit lines BL. Thereby, the third impurity diffusion layer 11 and the first impurity diffusion layer 6 constituting the MOS transistor function as a bit line or a part thereof.

Next, after forming an insulating film made entirely of silicon nitride, silicon oxide or silicon nitride oxide,
This insulating film is subjected to anisotropic etching in the vertical direction, so that the side surfaces of the word line WL and the gate electrode G and the gate electrode are formed as shown in FIGS. 2B, 6A and 9A. Insulating sidewalls 12 and 13 are formed on the inner peripheral surface of the opening 9a in G, respectively. If it is desired that the second impurity diffusion layer 10 and the third impurity diffusion layer 11 have an LDD structure, a high-concentration impurity is added to the silicon substrate 1 at this stage.
Ion implantation. At this time, the side walls 12, 1
3 and the gate electrode G function as a mask. When only the third impurity diffusion layer 11 is to have the LDD structure, the opening 9a in the gate electrolyte G is covered with a resist in advance. Subsequently, a high-melting-point metal film such as tantalum, cobalt, or titanium is formed on the whole, and thereafter, the high-melting-point metal film is reacted with the silicon substrate 1 in the second region B by heating, as shown in FIG. As shown in FIG. 9B, a high melting point metal silicide film 14 is formed on the surfaces of the second and third impurity diffusion layers 10 and 11, and thereafter, the unreacted high melting point metal film is removed. Such a technique is generally called salicide. If it is not desired to form a high melting point metal silicide on the silicon substrate 1 in the opening 9a, the opening 9a may be covered with a resist to prevent silicidation. In this case, the resist in the opening 9a is removed after completing the salicide process, exposing the second impurity diffusion layer 10 from the opening 9a. Next, as shown in FIG. 3A, after an interlayer insulating film 16 is entirely formed, a hole 16a for exposing the opening 9a inside the gate electrode G is formed in the interlayer insulating film 16 by photolithography. The hole 16a has a size on the gate electrode G to expose the opening 9a.

Next, after a conductive film (for example, impurity-containing silicon, high melting point metal, etc.) is formed on the whole, it is patterned and electrically connected to each second impurity diffusion layer 10 through each hole 16a. The storage electrode 17 of the capacitor Q is formed. Further, after the surface of the storage electrode 17 is covered with the dielectric film 18, a counter electrode 19 of a capacitor is formed on the storage electrode 17 so as to sandwich the dielectric film 18. The counter electrolyte 19 is made of, for example, an impurity-containing silicon film, a metal, or the like. As described above, a capacitor Q as shown in FIGS. 3B, 6C and 9C is formed on each gate electrode G in the second region B by the second impurity diffusion of each MOS transistor. It is formed to be electrically connected to the layer. The shape of the capacitor Q extends upward as shown in FIG. 6C in the Y direction in which the word line WL extends, and as shown in FIG. 8C in the X direction in which the band-shaped active region A extends. Will spread downward. That is, the shape of the capacitor Q is horseshoe-shaped, and the surface area is larger than that of the cylindrical capacitor. As described above, the opening 9 is formed inside the gate electrode G.
a, a second impurity diffusion layer 10 serving as a source (or drain) is formed on the silicon substrate 1 below the opening 9a, and a drain (or source) is provided on the silicon substrate 1 around the gate electrode G. Since the third impurity diffusion layer 11 is formed, the third impurity diffusion layer 11 is
Can be connected to each other via the impurity diffusion layer 6. Therefore, a plurality of third impurity diffusion layers 11 can be used as bit lines. In the above embodiment, the DRAM having the structure in which the capacitor Q is formed on the MOS transistor Tr has been described.
The MOS transistor Tr described above can be applied to another memory device, a logic circuit, or another semiconductor circuit. In the above-described embodiment, when an annular floating gate made of silicon is formed below the gate electrode G, a structure of a flash memory or an EEPROM can be formed instead of the MOS transistor Tr. At this time, the gate electrode G is used as a control gate, is insulated from the floating gate via a gate insulating film, and a tunnel insulating film is formed between the floating gate and the silicon substrate 1. In particular, when used for a flash memory, it is preferable to adopt a structure in which a memory erasing voltage is applied to the second impurity diffusion layer 10 through the opening 9a.

[Brief description of the drawings]

FIG. 1 is a plan view (part 1) illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a plan view (part 2) illustrating a process for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a plan view (part 3) illustrating a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention, taken along the line II of FIG.
It is.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention, taken along the line II of FIG.
It is.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention, taken along line II of FIG. 1A (part 3);
It is.

FIG. 7 is a cross-sectional view (part 1) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, as viewed from the line II-II in FIG.

FIG. 8 is a cross-sectional view (part 2) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, as viewed from the line II-II in FIG.

FIG. 9 is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the embodiment of the present invention, as viewed from the line II-II in FIG.

[Explanation of symbols]

1: silicon substrate, 2, 5: field insulating film, 6, 1
0, 11: impurity diffusion layer, 7: gate insulating film, 8: conductive film, 9: covering insulating film, 9a: opening, 12, 13: insulating sidewall, 14: refractory metal silicide, 16
... Interlayer insulating film, 16a ... Hole, G ... Gate electrode, Tr
... MOS transistors, WL ... word lines, BL ... bit lines.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792

Claims (6)

[Claims] A first insulating film formed on a semiconductor substrate;
A gate electrode formed on the first insulating film; an opening formed in the gate electrode; a first impurity region formed in the semiconductor substrate below the opening; And a second impurity region formed in the first region. 2. The semiconductor device according to claim 1, wherein an annular channel region exists between said first impurity region and said second impurity region. 3. The semiconductor device according to claim 1, wherein said element is a MOS transistor. 4. The semiconductor device according to claim 1, wherein a plurality of said MOS transistors are formed on said semiconductor substrate.
4. The semiconductor device according to claim 3, wherein the semiconductor devices are connected to each other via the second impurity region. 5. The semiconductor device according to claim 1, wherein a capacitor is connected to said second impurity region. 6. The semiconductor device according to claim 1, wherein a floating gate and a second insulating film are sequentially formed from the semiconductor substrate side between the gate electrode and the first insulating film.
13. The semiconductor device according to claim 1.