JP2000200836A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: To prevent receding of a boundary portion between an active region and an element isolation region in the case of two types of gate insulating films. An element isolation region formed on a main surface of a semiconductor substrate, and a semiconductor substrate defined by the element isolation region.
A MISFET including an active region 4a, 4b and a gate electrode 9 formed on the active region 4a, 4b via a gate insulating film 5, 8, respectively. Are formed thinner than the gate insulating film 5 to form two types of gate insulating films, and the gate insulating film 8 in the boundary region 7 between the active region 4b and the element isolation region 3 is formed.
Is formed so as to have a thickness substantially equal to the thickness of the gate insulating film 5. The gate insulating film 8 is formed by etching the gate insulating film 5 using a photoresist film having an opening smaller than the plane pattern of the active region 4b as a mask.
It is formed by an oxidizing treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a technology effective when applied to a semiconductor device having two types of gate insulating films on the same substrate.

[0002]

2. Description of the Related Art Large scale integrated circuits (LSIs)
MISFET (Metal) that constitutes an Integrated Circuit
Insulator Semiconductor Field Effect Transistor)
Among them, a MISFET constituting an input / output circuit is supplied with a power supply from outside and a voltage determined by the input / output standard. On the other hand, it is necessary to apply different voltages to the MISFET constituting the internal circuit in order to optimize its performance. For example, DRAM (Dynamic Random Access Me
(mory), it is more advantageous to apply a higher voltage to the MISFET in the memory cell than to the peripheral circuit in order to lengthen the data retention time. On the other hand, in a logic LSI such as a microcomputer, the voltage applied to the MISFET of the internal circuit needs to be set lower than the input voltage in order to reduce power consumption.

Incidentally, in order to prevent dielectric breakdown of the gate of the MISFET, it is necessary to keep the electric field intensity applied to the gate insulating film at about 4 MV / cm. Therefore, when only one type of gate insulating film is formed on a semiconductor substrate (hereinafter, referred to as one type of gate insulating film process), the thickness should be designed according to a value required for a high-voltage part. become. In this case, in the low voltage portion, the electric field intensity is reduced, so that the driving capability of the transistor is reduced. As a result, there is a problem that the processing speed of the LSI is reduced.
In order to prevent this, it is necessary to make the gate insulating film in the low voltage part relatively thin while keeping the gate insulating film in the high voltage part relatively thick. That is, two or more types of gate insulating films having different designed thicknesses are formed on the semiconductor substrate.

A technique for forming two types of gate insulating films having different design thicknesses on the same substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-0939678 (first document) and Japanese Patent Application Laid-Open No. 2-15374. It is described in a gazette (second document).

[0005] In the first document, there is a MISF for low voltage.
A technique is disclosed in which the gate insulating film of the ET is made thinner than the gate insulating film of the MISFET for high voltage, and the gate electrodes are formed in the same layer for low voltage and for high voltage. According to the literature, a MISFET having gate insulating films having different thicknesses is formed by performing a first gate oxidation, removing a gate insulating film other than a portion where a finished film thickness is increased, and then performing a second gate oxidation. Techniques are disclosed. Hereinafter, a technique for separately forming two types of thicknesses of the gate insulating film will be described.

First, an element isolation film is formed on a semiconductor substrate pulled up by the Czochralski (hereinafter referred to as CZ) method.
After forming a well and a sacrificial oxide film, respectively, and performing ion implantation for adjusting the threshold voltage in the same manner as in the single-gate insulating film process, a first gate insulating film is formed. Subsequently, after selectively forming an etching mask on the region where the finished film thickness of the gate insulating film is to be increased, a gate insulating film which is not covered with the mask is formed using a solution having an effect of etching the insulating film. Remove the film. Then, after removing the etching mask and performing cleaning, a second gate oxidation is performed. At this time, in the region covered by the mask, further gate oxidation is performed with the insulating film formed by the first gate oxidation remaining, so that a gate insulating film thicker than the region not covered by the mask is formed. You. After that, the semiconductor device is completed through the same steps as the one-type gate insulating film process.

[0007]

However, the above-mentioned 2
The present inventor has found that there are the following problems in the process technology of the seed gate insulating film.

That is, in a region where a thin gate insulating film (second gate insulating film) formed by the second gate oxidation is formed, a thick gate insulating film (first gate insulating film) formed by the first gate oxidation is formed. Since the (gate insulating film) is etched, one more etching and cleaning process is performed than in the region where the first gate insulating film is formed. For this reason, the isolation region in the region where the second gate insulating film is formed is excessively etched, and the end of the isolation region recedes from the surface. This will be described in detail with reference to the drawings. FIG. 13 and FIG. 14 are cross-sectional views for explaining the problem of the present invention.

As described in the section of the prior art,
To form a MISFET having two types of gate insulating films on the same substrate, first, as shown in FIG. 13A, an element isolation region 102 is formed on a main surface of a semiconductor substrate 101, Active region 1 surrounded by element isolation region 102
On the surface of the substrate 03, for example, a silicon oxide film is formed by using a thermal oxidation method, and a thick first gate insulating film 104 is formed.

Next, an M having a first gate insulating film 104 is formed.
A region where an ISFET (first MISFET) is to be formed is covered with a photoresist film 105 (FIG. 13B), and the first gate insulating film 104 is etched using the photoresist film 105 as a mask (FIG. 13C). At this time,
The boundary of the photoresist film 105 serving as a mask is formed on the element isolation region 102 in consideration of a margin such as misalignment of photolithography. For this reason,
As shown in FIG. 13C, a recess 106 is formed at a boundary between the active region 103 and the element isolation region 102 in a region where a MISFET (second MISFET) having a thin gate insulating film is formed later. That is, the second MISFET
In the region where the first MISFET is formed, one more etching process is performed than in the region where the first MISFET is formed. In this etching step, the silicon oxide film is slightly excessively etched (over-etched) in consideration of an etching margin, and a cleaning step for removing an etching residue is added.
The element isolation region 102 made of a silicon oxide film is shaved deeper than the active region 103 to form a recess 106.

Next, a silicon oxide film is formed using, for example, a thermal oxidation method, and a thin second gate insulating film 107 is formed in a region where the second MISFET is formed (FIG. 14).
(A)). Next, a conductive film serving as a gate electrode, for example, a polycrystalline silicon film 108 is deposited on the entire surface of the semiconductor substrate 101 (FIG. 14B). Next, the gate electrode 109 is formed by patterning the polycrystalline silicon film 108 (FIG. 14).
(C)).

However, during this patterning, the second
Since the recessed portion 106 is formed at the boundary between the active region 103 and the element isolation region 102 in the region where the MISFET is formed, there is a possibility that the etching residue 110 of the polycrystalline silicon film is generated. This etching residue 110 causes a leak between the gate electrode 109 and a wiring to be formed later, and causes a reduction in reliability of the semiconductor device.

The gate electrode 1 is formed in the recess 106.
The electric field of 09 concentrates and causes the deterioration of the gate breakdown voltage.
This is a factor that lowers the reliability of the semiconductor device.

If the etching residue 110 and the gate breakdown voltage are significantly deteriorated, they may cause a defect of the semiconductor device and lower the production yield of the semiconductor device.

Although the case where the element isolation region 102 is formed by shallow trench element isolation is shown here, the LOCOS
(Local Oxidation of Silicon) method causes the same problem.

An object of the present invention is to prevent receding of a boundary portion between an active region and an element isolation region when two or more MISFETs having different film thicknesses are formed on the same substrate (in the case of two types of gate insulating films). It is in.

Another object of the present invention is to prevent the gate breakdown voltage from deteriorating at the boundary between the active region and the element isolation region in the case of using two types of gate insulating films.

It is still another object of the present invention to prevent a material constituting a gate electrode from being left unetched at a boundary portion between an active region and an element isolation region in the case of a two-type gate insulating film.

Still another object of the present invention is to improve the reliability and yield of a semiconductor device in the case of using two types of gate insulating films.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0021]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor device according to the present invention includes a substrate made of a semiconductor or a substrate having a semiconductor layer on its surface, first and second active regions on the main surface of the substrate defined by element isolation regions, A first MISFET including a first gate electrode formed on one active region via a first gate insulating film, and a pair of first semiconductor regions formed across a channel region below the first gate electrode; A second MISFET including a second gate electrode formed on the region with a second gate insulating film interposed therebetween and a pair of second semiconductor regions formed sandwiching a channel region below the second gate electrode. The first gate insulating film has a first thickness on the first active region, and the second gate insulating film has a thickness substantially equal to the first thickness in a peripheral region of the second active region. Equally, in the second active area And it has a thickness smaller than the first thickness on the side region.

According to such a semiconductor device, the thickness of the second gate insulating film is formed smaller than that of the first gate insulating film in the region inside the second active region, and the function of the two-type gate insulating film is secured. can do. At the same time, in the outer peripheral region of the second active region, the film thickness is substantially equal to the thickness of the first gate insulating film, that is, the first gate insulating film is formed to be thicker. Concentration can be eased. This can prevent the breakdown voltage at the boundary between the second gate insulating films while ensuring the functions of the two types of gate insulating films, thereby improving the reliability and yield of the semiconductor device.

Note that the thickness of the second gate insulating film in the boundary region of the second active region below the second gate electrode can be made substantially equal to the thickness in the inner region. That is,
The thickness of the second gate insulating film at the boundary region between the second active region and the element isolation region does not need to be thick at all the boundary regions, but at the boundary region below the second gate electrode. Can be made as thin as the inner region. If the second gate insulating film in the boundary region below the second gate electrode is thick, the region functioning as the gate electrode of the second MISFET is defined by the inner region where the thickness of the second gate insulating film is small. , The gate width of the second MISFET is reduced. In order to secure a necessary gate width, it is necessary to increase the area of the active region, which is not preferable from the viewpoint of improving the degree of integration. However, by reducing the thickness of the second gate insulating film in the lower boundary region of the second gate electrode, the gate width of the second MISFET is determined by the width of the active region, which is convenient for improving the degree of integration. On the other hand, the etch residue of the gate electrode material does not occur or is limited to the periphery of the second gate electrode. For this reason, generation of a leak current due to the remaining etch is not a problem.

In this case, the thin region of the second gate insulating film in the boundary region substantially matches the width of the second gate electrode, is smaller than the width of the second gate electrode, or is smaller than the width of the second gate electrode. It can be slightly wider than the width.

In this case, the gate width of the second MISFET is defined by the width of the second active region.

Note that the film thickness on the first active region is formed substantially uniformly. Here, “substantially uniform” is expressed as “uniform” in the sense that the thickness on the second active region is not intended to be positively changed to the Z level. That is, even if the film actually has a distribution in the film thickness, it is included in a substantially uniform range on the assumption that a significant change is not caused in the performance of the transistor.

(2) The method of manufacturing a semiconductor device according to the present invention
(A) forming an element isolation region on a main surface of a substrate made of a semiconductor or a substrate having a semiconductor layer on a surface thereof to form first and second active regions; and (b) on the first and second active regions. Forming a first gate insulating film, (c) forming a photoresist film on the first gate insulating film, and forming the photoresist film such that the boundary between the exposed portion and the light shielding portion is mainly on the second active region. Exposing the photoresist film using a mask having the following pattern to pattern the photoresist film, (d) etching the first gate insulating film on the second active region using the photoresist film as a mask, and (e) etching the photoresist film. Removing and cleaning the surface of the substrate, forming a second gate insulating film on the second active region, (f) first and second
Depositing a conductive film on the gate insulating film, patterning the conductive film, and forming a first gate electrode on the first active region;
Forming a second gate electrode on the second active region.

According to such a method of manufacturing a semiconductor device, the removal of the first gate insulating film on the second active region is performed by using a mask having a pattern in which the boundary between the exposed portion and the light shielding portion is mainly on the second active region. Therefore, the boundary region between the second active region and the element isolation region is not etched, and no recession occurs in the boundary region. As a result, the second
Deterioration of the gate withstand voltage of the MISFET or residual etching of the gate electrode material does not occur, and the reliability and yield of the semiconductor device can be improved.

The boundary between the light-exposed portion and the light-shielded portion of the mask in the step (c) is mainly located on the element isolation region in the region below the first structure and the second gate electrode on the second active region. A second configuration, a third configuration on the element isolation region in a region below and around the second gate electrode, and a third configuration on only a part of the region below the second gate electrode on the element isolation region. 4 can be adopted.

According to this manufacturing method, it is possible to manufacture a semiconductor device in which the etching residue of the conductive film does not remain at the boundary between the second active region and the element isolation region.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Embodiment 1 FIGS. 1 to 8 are plan views or sectional views showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps. In addition,
The sectional views taken along the line bb or the line cc shown in the plan view are shown in (b) and (c), respectively.

First, for example, a p-type specific resistance of 10 Ωcm
Prepare a semiconductor substrate 1 made of about single crystal silicon,
For example, a thin silicon oxide film (not shown) having a thickness of about 10 nm formed by wet oxidation at about 850 ° C. and a silicon nitride film (not shown) having a thickness of about 140 nm formed by, for example, a CVD (Chemical Vapor Deposition) method. Is deposited on the semiconductor substrate 1. Here, a semiconductor substrate 1 made of single crystal silicon is exemplified, but an SOI (Silicon On Insulator) substrate having a single crystal silicon layer on the surface or a dielectric substrate such as glass or ceramics having a polycrystalline silicon film on the surface is used. You may.

Next, the silicon nitride film and the silicon oxide film are patterned using a photoresist film having a pattern as shown in FIG. 1A as a mask, and the semiconductor substrate 1 is dry-etched using the silicon nitride film as a mask. Thereby, a shallow groove 2 having a depth of about 300 to 400 nm is formed in the semiconductor substrate 1 in the element isolation region. On the inner wall of the shallow groove 2, for example, a silicon oxide film having a thickness of about 10 nm by wet oxidation at about 850 to 900 ° C. may be formed in order to remove a damaged layer caused by the dry etching.

Next, for example, a silicon oxide film (not shown, deposited by a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.
A TEOS oxide film is deposited in a thickness of about 300 to 400 nm, and the TEOS oxide film is polished by a CMP method to remove the TEOS oxide film in a region other than the shallow groove 2. The element isolation region 3 is formed while leaving the oxide film (FIG. 1B). Active regions 4a and 4b are formed on the main surface of semiconductor substrate 1 surrounded by element isolation region 3. As will be described later, a relatively thick gate insulating film is formed in the active region 4a, and a thin gate insulating film is formed in the active region 4b.

Before polishing by the CMP method, the T
The EOS oxide film may be subjected to sintering (baking) by dry oxidation at about 1000 ° C., for example. Further, before the polishing by the CMP method, a silicon nitride film is formed in the region of the shallow groove 2 to prevent a dishing phenomenon in which the TEOS oxide film in the region of the shallow groove 2 is excessively polished.

Next, the silicon oxide film and the silicon nitride film remaining on the surface of the semiconductor substrate 1 are removed by, for example, wet etching using hot phosphoric acid, and the semiconductor substrate is cleaned using a HF (hydrofluoric acid) cleaning solution. 1. Clean the surface. Thereafter, the semiconductor substrate 1 is wet-oxidized at, for example, about 850 ° C., and a relatively thick gate insulating film 5 (first gate insulating film) having a relatively large thickness is formed on the surfaces of the active regions 4a and 4b (FIG. 2).

Next, a photoresist film 6 having a pattern as shown in FIG. 3A is formed on the gate insulating film 5 (FIG. 3B). The opening 6b of the photoresist film 6
It is formed smaller than the active region 4b. That is, the boundary region 7 between the active region 4 b and the element isolation region 3 is formed so as to be covered with the photoresist film 6.

Next, the gate insulating film 5 on the active region 4b is etched using the photoresist film 6 as a mask (FIG. 4). Further, the photoresist film 6 is removed by ashing or the like, and the semiconductor substrate 1 is cleaned using an HF (hydrofluoric acid) -based cleaning solution to clean the surface of the active region 4b. Here, since the boundary region 7 between the active region 4b and the element isolation region 3 is covered with the photoresist film 6, the boundary region 7
Is not etched. Further, since the gate insulating film 5 remains in the boundary region 7, it is not etched by cleaning. For this reason, the silicon oxide film in the boundary region 7 is not excessively etched and the above-described recessed portion is not formed. As a result, the gate breakdown voltage does not decrease due to the receded portion or the etching residue of the gate electrode material described later does not remain in the boundary region 7, so that the reliability and the yield of the semiconductor device can be improved.

Next, the semiconductor substrate 1 is wet-oxidized at, for example, about 850 ° C. to form a gate insulating film 8 (second gate insulating film) on the surface of the active region 4b (FIG. 5). Since the gate insulating film 5 is already formed in the active region 4a, the thickness of the gate insulating film 5 is increased by this wet oxidation step, while a new gate insulating film 8 is formed in the active region 4b. Will be. Therefore, the gate insulating film 5
Is thicker than the gate insulating film 8. Thus, the gate insulating films 5 and 8 having two different thicknesses are formed on the same semiconductor substrate 1. The gate insulating film 8 on the active region 4b is formed thicker in the boundary region 7 than on the inside. Thus, the thickness of the gate insulating film 8 is
, The gate breakdown voltage of the second MISFET formed in this region can be improved.

The active regions 4a and 4b may be formed with well regions into which impurities according to the conductivity type are introduced. The well region is formed by, for example, an ion implantation method.

Although not particularly limited, after the gate insulating films 5 and 8 are formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere. Alternatively, nitrogen may be segregated at the interface between the gate insulating films 5 and 8 and the semiconductor substrate 1 (oxynitriding process). When the thicknesses of the gate insulating films 5 and 8, particularly the thickness of the gate insulating film 8, are reduced to, for example, about 7 nm, distortion generated at the interface between the two due to a difference in thermal expansion coefficient with the semiconductor substrate 1 becomes apparent, and hot carriers are generated. Trigger. Semiconductor substrate 1
Nitrogen segregated at the interface with the silicon nitride mitigates this distortion, and thus the oxynitridation can improve the reliability of the extremely thin gate insulating films 5 and 8.

Next, for example, a polycrystalline silicon film (not shown) is deposited on the entire surface of the semiconductor substrate 1, and this polycrystalline silicon film is patterned into a plane pattern as shown in FIG. 9 (FIG. (B),
(C)). When the polycrystalline silicon film is patterned, no recess is formed in the boundary region 7 as shown in FIG. For this reason, the etching residue of the polycrystalline silicon film does not occur, and the reliability and yield of the semiconductor device can be improved. Further, as shown in FIG.
Since the gate insulating film 8 is formed thick in the boundary region 7 of b, the insulation between the gate electrode 9 and the active region 4b is ensured, and the gate breakdown voltage can be kept high. The polycrystalline silicon film can be deposited by, for example, a CVD method. In place of the polycrystalline silicon film, the gate electrode 9 may be a polycrystalline silicon film, a laminated film of an intermediate layer such as a tungsten nitride film and a tungsten film, or
It can be composed of a laminated film of a polycrystalline silicon film and a metal silicide film such as tungsten silicide.

Then, impurities are ion-implanted into the semiconductor substrate 1 to form the semiconductor region 10 in a self-aligned manner with the gate electrode 9 (FIG. 7). The semiconductor region 10 functions as a source / drain region of the MISFET. Depending on the conductivity type of the MISFET to be formed, for example, phosphorus or arsenic is implanted for an n-channel MISFET, and boron is implanted for a p-channel MISFET. Although not shown, it goes without saying that a photoresist film is formed on the semiconductor substrate 1 and a region into which ions are implanted can be selected using the photoresist film as a mask. After that, an insulating film such as a silicon oxide film or a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1 and is anisotropically etched to form a sidewall spacer on the side surface of the gate electrode 9. The high-concentration impurity semiconductor region can be formed by ion implantation using the spacer and the gate electrode 9 as a mask. In this case, the introduction of impurities into the semiconductor region 10 is kept at a low concentration, and the low-concentration semiconductor region 10 and the high-concentration impurity semiconductor region constitute a so-called LDD (Lightly Doped Drain).

Finally, an insulating film 11 covering the gate electrode 9 is formed, and a wiring 12 is formed on the insulating film 11 (FIG. 8). The wiring 12 is connected to the semiconductor region 10 via a connection hole opened in the insulating film 11 on the semiconductor region 10. The insulating film 11 is made of, for example, SOG (Spin On Glass).
It can be a laminated film of a film and a TEOS oxide film, the surface of which is, for example, CMP (Chemical Mechanical Polishing).
g) It can be flattened by the method. The wiring 12 can be formed by patterning an aluminum film formed by, for example, a sputtering method using a photolithography technique. The wiring 12 may be formed of a laminated film of a titanium nitride film, an aluminum film, and a titanium nitride film. Also,
The wiring 12 may be connected to the semiconductor region 10 via a plug. The plug can be formed of a stacked film of a titanium film, a titanium nitride film, and a tungsten film. Thus, the semiconductor device of the present embodiment can be formed.

It should be noted that the semiconductor device of the present embodiment is
When applied to an M (Dynamic Random Access Memory), a MISFET is used as a selection MISFET or a MISFET of a peripheral circuit, a bit line is formed in the same layer as the wiring 12, and an information storage capacitor is formed in an upper layer of the MISFET. After that, a second-layer wiring, a third-layer wiring, and the like can be formed, but detailed description is omitted. In addition, the semiconductor device of the present embodiment is formed by using a static random access memory (SRAM).
), When applied to a logic circuit, etc., the second
Although a wiring layer higher than the layer, the third layer wiring and the like can be formed, a detailed description is omitted. Further, the semiconductor device of the present embodiment is replaced with an EEPROM (Electric Erasable Read Only Memory).
In the case of applying y), after forming a tunnel oxide film and a floating gate electrode, an interlayer insulating film between the floating gate electrode and the control gate electrode is formed in the same layer as the gate insulating film 5, and the control gate electrode is formed. The gate electrode 9 can be formed in the same layer as above, and a wiring layer higher than the second layer, the third layer wiring, etc. can be formed, but detailed description is omitted.

According to the semiconductor device of the present embodiment, the thickness of the gate insulating film 8 in the boundary region 7 at the boundary between the active region 4b and the element isolation region 3 is larger than that in the inner region. The gate breakdown voltage of the MISFET formed in 4b is not deteriorated, and the reliability and yield of the semiconductor device can be improved. In addition, there is no etching residue of the material of the gate electrode 9 in the boundary region 7, so that the reliability and the yield of the semiconductor device can be improved.

(Embodiment 2) FIGS. 9 and 10 are plan views or sectional views showing an example of a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

The manufacturing method of this embodiment is the same as that of the first embodiment.
Are the same as the steps up to FIG. Therefore, the description is omitted.

Next, on the gate insulating film 5 shown in FIG. 2, a photoresist film 13 having a pattern as shown in FIG.
To form Most of the opening 13b of the photoresist film 13 is formed smaller than the active region 4b as in the first embodiment, but the opening 13b is formed in the boundary region 7 where the gate electrode 9 is formed later. An overhang region 13c is formed on the substrate. Since such an overhang region 13c is provided, in the gate insulating film 5 etching process described below, the gate insulating film 5 is also etched on a part of the boundary region 7.

Next, the gate insulating film 5 is etched using the photoresist film 13 as a mask. The cross section taken along the line bb in FIG. 9A after the etching is the same as that in FIG. FIG. 9B shows a cross section taken along the line cc in FIG. 9A. In the present embodiment, since the photoresist film 13 has the overhanging region 13c, a part of the gate insulating film 5 and the element isolation region 3 is etched in the boundary region 7 as shown in FIG. Is formed.
However, the recessed portion 14 is formed only in the portion of the overhang region 13c, and no recessed portion is formed in the other boundary region 7 as in the first embodiment.

Next, the photoresist film 13 is removed, and a gate insulating film 8 is formed as in the first embodiment (FIG. 9).
(C)).

Next, as in the first embodiment, for example, a polycrystalline silicon film is deposited and patterned to form a gate electrode 9 (FIGS. 10A and 10B). FIG.
The cross section taken along the line bb in (a) is the same as that in FIG. FIG. 10A is a cross-sectional view taken along the line cc in FIG.
(B). Thus, the boundary region 7 of the active region 4b
In this case, the gate insulating film 5 is etched to the outside of the active region 4b.
Is formed thinly over the entire width. For this reason, the gate width of the MISFET formed in the active region 4b is determined by the width of the active region 4b.
The required gate width of the ISFET can be secured. Thus, the design margin of the semiconductor device can be increased and the design can be facilitated. Since the thickness of the gate insulating film 8 in the boundary region 7 other than the lower region of the gate electrode 9 is formed thick as in the first embodiment, the etching residue of the gate electrode 9 material is the same as in the first embodiment. Does not occur. As a result, in addition to the above effects, it is possible to eliminate factors that lower the reliability and the yield of the semiconductor device due to the unetched portion.

Subsequent steps are the same as those in the first embodiment, and a description thereof will be omitted.

In the second embodiment, the pattern of the photoresist film 13 is formed such that the overhanging region 13c substantially overlaps the pattern of the gate electrode 9.
As shown in FIG. 1, the width of the overhang region 13c can be configured to be larger than the width of the pattern 15 of the gate electrode 9. Further, as shown in FIG. 12, the width of the overhang region 13c can be configured to be smaller than the width of the pattern 15 of the gate electrode 9. By configuring the pattern of the photoresist film 13 in this manner, it is possible to provide a margin for pattern alignment and to increase a process margin.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, the case where the element isolation region 3 is formed in the shallow groove 2 has been described.
The present invention can be applied to a case where the element isolation region is formed by the LOCOS method or the element isolation region is formed in the U groove.

Further, the present invention relates to a DRAM, an SRAM, an E
The present invention can be applied to any MIS-type transistor included in an EPROM (including a so-called flash memory), a logic element, or the like.

[0060]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In the case of two types of gate insulating films, it is possible to prevent the receding portion at the boundary between the active region and the element isolation region.

(2) In the case of a two-type gate insulating film, deterioration of the gate breakdown voltage at the boundary between the active region and the element isolation region can be prevented.

(3) In the case of a two-type gate insulating film, the etching residue of the material forming the gate electrode at the boundary between the active region and the element isolation region can be prevented.

(4) It is possible to improve the reliability and the yield of the semiconductor device in the case of using two types of gate insulating films.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view, respectively, showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps;

FIG. 2 is a sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps.

3A and 3B are a plan view and a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps;

FIG. 4 is a cross-sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps.

FIG. 5 is a sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps.

6A and 6B are a plan view and a cross-sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps;

FIG. 7 is a sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps.

FIG. 8 is a sectional view illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of the manufacturing steps.

FIG. 9 is a plan view (a) and a cross-sectional view ((b) and (c)) showing an example of a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of the manufacturing steps.

FIG. 10 is a plan view showing an example of a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of the manufacturing steps;
And a sectional view (b).

FIG. 11 is a plan view showing another example of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 12 is a plan view showing still another example of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a problem of the present invention.

FIG. 14 is a cross-sectional view for explaining a problem of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Shallow groove 3 Element isolation region 4a, 4b Active region 5 Gate insulating film 6 Photoresist film 6b Opening 7 Boundary region 8 Gate insulating film 9 Gate electrode 10 Semiconductor region 11 Insulating film 12 Wiring 13 Photoresist film 13b Opening 13c Overhang region 14 receding portion 15 gate electrode pattern 101 semiconductor substrate 102 device isolation region 103 active region 104 first gate insulating film 105 photoresist film 106 receding portion 107 second gate insulating film 108 polycrystalline silicon film 109 gate electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F048 AA05 AA07 AB01 AC03 BA16 BB05 BB08 BB09 BB12 BB16 BC06 BF16 BG12 BG14 DA20 DA25 DA27

Claims (7)

[Claims] A semiconductor substrate or a substrate having a semiconductor layer on a surface thereof; first and second active regions on a main surface of the substrate defined by an element isolation region; A first MIS including a first gate electrode formed via one gate insulating film and a pair of first semiconductor regions formed sandwiching a channel region below the first gate electrode;
An FET including a FET, a second gate electrode formed on the second active region with a second gate insulating film interposed therebetween, and a pair of second semiconductor regions formed sandwiching a channel region below the second gate electrode. A first gate insulating film having a first thickness on the first active region, wherein the second gate insulating film has an outer peripheral region of the second active region. A semiconductor device having a second film thickness substantially equal to the first film thickness in an inner region of the second active region and smaller than the first film thickness. 2. The semiconductor device according to claim 1, wherein a thickness of the second gate insulating film in a boundary region of the second active region below the second gate electrode is equal to a thickness of the inner region. A semiconductor device characterized by being substantially equal. 3. The semiconductor device according to claim 2, wherein the thin region of the second gate insulating film in the boundary region has a first configuration substantially equal to a width of the second gate electrode. A second configuration narrower than the width of the gate electrode, or a third configuration wider than the width of the second gate electrode;
A semiconductor device having any one of the above configurations. 4. The semiconductor device according to claim 2, wherein a gate width of said second MISFET is defined by a width of said second active region. 5. A step of (a) forming an element isolation region on a main surface of a substrate made of a semiconductor or a substrate having a semiconductor layer on its surface, and forming first and second active regions; (b) forming the first and second active regions. And forming a first gate insulating film on the second active region; and (c) forming a photoresist film on the first gate insulating film, and forming a boundary between the exposed portion and the light shielding portion of the photoresist film. Exposing the photoresist film using a mask having a pattern mainly on the second active region and patterning the photoresist film; (d) the first gate insulating film on the second active region using the photoresist film as a mask (E) removing the photoresist film, cleaning the surface of the substrate, and then forming a second gate insulating film on the second active region; (f) etching the first and second films; 2nd game Depositing a conductive film on the insulating film and patterning the conductive film to form a first gate electrode on the first active region and a second gate electrode on the second active region; A method for manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 5, wherein a boundary between the light-exposed portion and the light-shielded portion of the mask in the step (c) is mainly located on the second active region. Configuration, a second configuration above the element isolation region in a region below the second gate electrode, and a third configuration above the element isolation region in a region around and below the second gate electrode A fourth region on the element isolation region only in a part of a region below the second gate electrode;
The manufacturing method of the semiconductor device characterized by any one of the above configurations. 7. The method of manufacturing a semiconductor device according to claim 5, wherein no etching residue of the conductive film remains at a boundary between the second active region and the element isolation region. A method for manufacturing a semiconductor device, comprising: