JP2000200829A - Method for manufacturing semiconductor device having trench element isolation region - Google Patents

Abstract

(57) [Summary] (Problem corrected) [Problem] A trench element isolation capable of controlling a shape of a recess at an upper end portion of an insulating layer, which is generated when a portion of the insulating layer protruding from an upper surface level of a Si substrate is isotropically etched. A method for manufacturing a semiconductor device having a region is provided. SOLUTION: A pad layer 12 is formed on a surface of a Si substrate 10, and a mask layer 14 is formed on a surface of the pad layer. The mask layer and the pad layer are etched into a predetermined pattern, and as the mask layer 14 moves away from the Si substrate 10,
Etch into a reversely inclined shape spreading outward. Using the mask layer as a mask, the Si substrate is anisotropically etched to expose the surface end of the element formation region to form a trench 16.
Next, by oxidizing the surface of the exposed substrate, the Si substrate 1
0 is formed in a circular shape at the upper edge portion, and the trench 16 is further formed.
Is filled with an insulating layer to form a trench element isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an element isolation groove.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements, for example, MOS transistors, it is necessary to miniaturize a region for separating semiconductor elements. In order to achieve the miniaturization of this region, a trench element isolation technique for providing a groove (hereinafter referred to as a "trench") on a substrate between semiconductor elements and filling the trench with an insulating material to isolate the semiconductor elements from each other has been studied. Have been. An example of this technique will be described below.

FIGS. 24 to 27 are cross-sectional views schematically showing steps of forming a trench element isolation region 123 using a conventional trench element isolation technique.

First, as shown in FIG. 24, after a pad layer 112 and a stopper layer 114 are sequentially deposited on a silicon substrate 110, a resist pattern R10 having a predetermined pattern is formed on the stopper layer 114. Using the resist layer R10 as a mask, the stopper layer 114 is etched.

Then, as shown in FIG. 25, the resist layer R10 is removed by ashing, and the silicon substrate 110 is etched using the stopper layer 114 as a mask to form a trench 116. After that, the exposed surface of the silicon substrate 110 in the trench 116 is thermally oxidized to form a trench oxide film 118.

Next, an insulating layer 120 is deposited on the entire surface so as to fill the trench 116, and as shown in FIG. 26, the insulating layer 120 is planarized using the stopper layer 114 as a mask. Next, the stopper layer 114 is removed using hot phosphoric acid.

In a subsequent step, the insulating layer 120 is
A portion protruding from the level of the upper surface of the silicon substrate 110 is isotropically etched to form a trench isolation region 123 as shown in FIG.

However, when trench element isolation region 123 is formed as described above, depression 125 is formed at the upper end of insulating layer 120 as shown in FIG.

[0009] As shown in FIG. 28, the depression 125 has a steep slope of the silicon substrate 110 and the insulating layer 120 in the depression 125. If the inclination is steep, the gate electrode material remains in the recess 125 in the etching of the gate electrode material for forming the gate electrode. If the gate electrode material remains in the recess 125, a problem such as a short circuit occurs.

[0010]

SUMMARY OF THE INVENTION The present invention relates to an insulating layer,
Provided is a method for manufacturing a semiconductor device having a trench element isolation region capable of controlling a shape of a recess at an upper end portion of an insulating layer, which is generated when a portion protruding from a level protruding from an upper surface of a silicon substrate is isotropically etched. Is to do.

[0011]

A method of manufacturing a semiconductor device having a trench element isolation region according to the present invention includes the following steps (a) to (f).

(A) forming a pad layer on the surface of a silicon substrate; (b) forming a mask layer on the surface of the pad layer; and (c) forming the mask layer and the pad layer into a predetermined pattern. An etching step, wherein the mask layer is etched in a reverse tapered shape that spreads outward as the distance from the silicon substrate increases.
(D) etching the silicon substrate using the mask layer as a mask to form an element isolation groove, wherein the silicon substrate is anisotropically etched to form a surface of a region of the silicon substrate where an element is to be formed; Exposing an end portion, (e) oxidizing the exposed surface of the silicon substrate to make an upper edge portion of the silicon substrate a rounding shape, and (f) insulating layer in the element isolation groove. Filling trenches to form trench element isolation regions.

The present invention mainly has the following three advantages.

(1) First, in the steps (c), (d) and (e), the upper edge portion (hereinafter referred to as “edge portion”) of the silicon substrate can be formed into a rounding shape. Therefore, the edge portion can be formed into a rounding shape by a simple process without adding a special step.

(2) Second, the width of the exposed portion of the end portion,
By changing the oxidation conditions and the like, the radius of curvature of the edge having a rounding shape can be easily controlled, and the edge can be formed into a rounding shape having a large radius of curvature as necessary.

(3) Third, when the edge portion is rounded so that the portion of the insulating layer protruding from the level of the upper surface of the silicon substrate (hereinafter referred to as "protruding portion") is isotropically etched. In this case, the depression at the upper end of the insulating layer can be reduced as compared with the case where the edge is not rounded.

In the mask layer formed in the step (c), an angle formed between a side surface of the mask layer and a surface of a region of the silicon substrate where an element is formed (hereinafter, referred to as an “element formation region”) is It is preferably 70 to 85 °. The end of the surface of the element formation region can be more reliably exposed.

The etching in the step (d) is preferably reactive ion etching.

The width of the exposed end of the surface of the element formation region formed in the step (d) is 10 to 55 nm in consideration of a preferable radius of curvature of the edge having a rounding shape. Preferably, it is more preferably 10 to 30 nm.

By forming the edge portion in a rounded shape, it is possible to obtain an operational effect such that the electrode material filled in the recess can be reliably removed when etching the electrode material for forming the gate electrode. Can be.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(Structure of Device) A semiconductor device having a trench element isolation region obtained by the manufacturing method of the present invention will be described.

FIG. 23 shows a semiconductor device (hereinafter, referred to as “semiconductor device”) 100 having a trench element isolation region obtained by the manufacturing method of the present invention.

The semiconductor device 100 shown in FIG. 23 has a trench element isolation region 23, an n-type MOS element 80 and a p-type M element.
OS element 82 is included.

The trench element isolation region 23 is a region formed by filling the trench 16 provided in the silicon substrate 10 with the insulating layer 20. Trench element isolation region 23 has a role of isolating between MOS elements and defining an element region. With the trench element isolation region 23 as a boundary, a p-type retrograde well 32 is formed in one element region, and an n-type retrograde well 30 is formed in the other element region.

On the p-type retrograde well 32, n
A type MOS element 80 is formed, and a p-type MOS element 82 is formed on the n-type retrograde well 30.

The n-type MOS device 80 has a gate oxide film 28
, A gate electrode 46 and an n-type impurity diffusion layer 50.

The gate oxide film 28 in the n-type MOS device 80 is formed on the p-type retrograde well 32. On this gate oxide film 28, a gate electrode 46 is formed. The gate electrode 46 includes a polycrystalline silicon layer 40 and a metal silicide layer 42 formed on the polycrystalline silicon layer 40. Then, a sidewall insulating film 70 is formed so as to cover the gate oxide film 28 and the sidewall of the gate electrode 46.

The n-type impurity diffusion layer 50 constitutes a source / drain region. Then, the n-type impurity diffusion layer 50
Comprises an LDD structure having a low concentration n-type impurity diffusion layer 50a and a high concentration n-type impurity diffusion layer 50b.

The p-type MOS element 82 is formed on the gate oxide film 28
, A gate electrode 46 and a p-type impurity diffusion layer 60.

The gate oxide film 28 in the p-type MOS element 82 is formed on the n-type retrograde well 30. Gate electrode 46 and sidewall insulating film 70
Are the same as those of the n-type MOS element 80.

The p-type impurity diffusion layer 60 is the same as the n-type impurity diffusion layer 50 except that it is p-type.

(Manufacturing Process) Next, a manufacturing process of the semiconductor device 100 shown in FIG. 22 will be described. Figure 1
FIG. 21 shows a manufacturing process of the semiconductor device 100.

(1) Formation of Trench First, description will be made with reference to FIG. Silicon substrate 10
The pad layer 12 is formed thereon. The material of the pad layer 12 can be, for example, SiO ₂ , SiON, or the like. When the pad layer 12 is made of SiO ₂ , it can be formed by a thermal oxidation method, a CVD method, or the like.
When N is used, it can be formed by a CVD method or the like. The thickness of the pad layer 12 is, for example, 5 to 20 n.
m.

Next, a mask layer 14 is formed on the pad layer 12.
To form As the stopper layer 14, for example, a silicon nitride layer, a polycrystalline silicon layer, an amorphous silicon layer, or a multilayer composed of at least two selected from the group consisting of a silicon nitride layer, a polycrystalline silicon layer, and an amorphous silicon layer A structure or the like can be given, and a known method such as a CVD method can be given as a forming method.
The mask layer 14 has a thickness sufficient to function as a stopper in the subsequent chemical mechanical polishing (CMP), for example, a thickness of 50 to 200 nm.

On the mask layer 14, a resist pattern R1 having a predetermined pattern is formed. As shown in FIG. 2, the resist layer R1 is opened above a region where the trench 16 is to be formed.

Next, as shown in FIG.
Is used as a mask to etch the mask layer 14. In this etching, the shape of the mask layer 14 is made to have a shape that spreads outward as the distance from the silicon substrate 10 increases, that is, an inverted taper shape. Mask layer 1 having reverse taper shape
The angle Θ between the side surface of the substrate 4 and the surface of the silicon substrate 10 is preferably 70 to 85 °, more preferably 75 to 80 °. As an etching method for forming the mask layer 14 into a reverse tapered shape, for example, when the mask layer 14 is a polycrystalline silicon layer, it is preferable to use a chlorine-based gas as an etchant. When the mask layer 14 is etched, the pad layer 12 is simultaneously etched.

Next, the resist layer R1 is removed by ashing. Next, as shown in FIG. 3, using the mask layer 14 as a mask, the silicon substrate 10 is anisotropically etched to expose the end of the surface of the element formation region,
6 is formed. The method of anisotropic etching is not particularly limited as long as it is an etching method that exposes the end of the surface of the element forming region. For example, anisotropic etching using a mixed gas of Cl ₂ and O ₂ as an etchant is used. And the like. The width of the exposed end of the surface of the element formation region varies depending on the device design, but is preferably 10 to 55 nm, more preferably 10 to 30 nm. The depth of the trench 16 varies depending on the device design, but is, for example, 300 to 500 nm.

Next, as shown in FIG. 4, the exposed surface of the silicon substrate 10 in the trench 16 is oxidized by a thermal oxidation method to form an oxide film (hereinafter referred to as "trench oxide film") 18.
To form Further, by exposing the end of the surface of the element formation region, the thermal oxidation causes the edge (the upper edge of the silicon substrate 10) to be round-oxidized to have a rounding shape. In this way, when the edge portion has a rounding shape, the radius of curvature of the edge portion can be increased. The radius of curvature can be controlled by changing the width of the exposed end portion of the element formation region, oxidation conditions, and the like.

The thermal oxidation method is not particularly limited, but is preferably a dry oxidation method. The dry oxidation is preferably performed in an atmosphere of oxygen, or in an atmosphere of a mixed gas of oxygen and an inert gas such as nitrogen or argon. The temperature in the thermal oxidation is preferably in the range of 1050 to 1150 ° C.

(2) Filling Trench with Insulating Layer and Flattening Insulating Layer As shown in FIG. 5, an insulating layer 20 is deposited on the entire surface so as to fill the trench 16. Insulating layer 2
A film thickness of 0 buries the trench 16 and covers at least the mask layer 14, for example, 500 to 800 n
m. The material of the insulating layer 20 is made of, for example, silicon oxide. Examples of a method for depositing the insulating layer 20 include a high-density plasma CVD method, a thermal CVD method, and a TEOS plasma CVD method.

Next, as shown in FIG.
Flatten by the MP method. This planarization is performed by the mask layer 14.
Repeat until is exposed. That is, the insulating layer 20 is planarized using the mask layer 14 as a stopper.

Next, as shown in FIG.
Is removed using, for example, a hot phosphoric acid solution.

Next, although not shown, the pad layer 12 is etched using an etchant such as hydrofluoric acid. During this etching, a part of the protrusion 22 is also etched.

Next, as shown in FIG. 8, a sacrificial oxide film 24 is formed on the exposed surface of the substrate. Sacrificial oxide film 24
Has a thickness of, for example, 10 to 30 nm.

(3) Formation of Well Subsequently, as shown in FIG. 9, a resist layer R2 having a predetermined pattern is formed on the surface of the insulating layer 20 filling the sacrificial oxide film 24 and the trench 16. Resist layer R2
Are opened so that the surface of the region to be an n-well is exposed. Using this resist layer R2 as a mask, phosphorus,
An n-type retrograde well 30 is formed in the silicon substrate 10 by injecting an n-type impurity such as arsenic into the silicon substrate 10 one or more times. The retrograde well refers to a well having a peak of the impurity concentration of the well at a deep position in the silicon substrate 10.

Next, as shown in FIG.
4 and the surface of the insulating layer 20 filling the trench 16,
A resist layer R3 is formed. The resist layer R3 is opened so that the surface of the region to be a p-well is exposed.
Using the resist layer R3 as a mask, a p-type impurity such as boron is
By implanting 0, a p-type retrograde well 32 is formed in the silicon substrate 10.

Next, as shown in FIG.
4 is etched using an etchant such as hydrofluoric acid. At this time, a part of the protruding portion 22 is also etched, and thus, the trench element isolation region 23 is formed. Then, the insulating layer 2 is formed through the above-described step of etching the pad layer 12 and the step of etching the sacrificial oxide film 24.
0, at the top end, as shown in FIG.
5 results.

FIG. 23 is an enlarged sectional view schematically showing the depression 25 in FIG. By comparing FIG. 23 and FIG. 28, it is found that the present embodiment in which the edge portion has a rounding shape is
And the slope of the insulating layer 20 becomes gentler, and the depression 2
It can be seen that No. 5 is formed by a gentler surface than the recess 125 according to the conventional example. The function and effect of this will be described later in detail.

(4) Formation of Gate Electrode Next, as shown in FIG.
An oxide film 26 is formed on the element region defined by 3. A part of the oxide film 26 becomes a gate oxide film 28.

As shown in FIG. 13, a polycrystalline silicon layer 40 is formed on insulating layer 20 and oxide film 26 by a CVD method or the like. The polycrystalline silicon layer 40 is doped. By forming the polycrystalline silicon layer 40, the depression 25 is also filled with polycrystalline silicon.

A metal silicide layer 42 is formed on the surface of polycrystalline silicon layer 40. Examples of the material of the metal silicide layer 42 include silicide such as tungsten, titanium, and molybdenum, and examples of the method for forming the silicide layer 42 include a stampering method.

Thereafter, a silicon oxide layer 44 is formed on the surface of the metal silicide layer 42. As a method for forming the silicon oxide layer 44, for example, a CVD method or the like can be given.

As shown in FIG. 14, the silicon oxide layer 44
A resist layer R4 is formed so as to cover a region where the gate electrode 46 is to be formed. Next, the silicon oxide layer 44 is etched using the resist layer R4 as a mask.

After that, as shown in FIG. 15, the resist layer R4 is removed by ashing.

Next, as shown in FIG. 16, using the silicon oxide layer 44 as a mask, the metal silicide layer 42 and the polycrystalline silicon layer 40 are etched. Thus, a gate electrode 46 composed of the polycrystalline silicon layer 40 and the metal silicide layer 42 is formed. When the polycrystalline silicon layer 40 is etched, the inclination of the silicon substrate 10 and the insulating layer 20 in the depression 25 is made gentle, so that the polycrystalline silicon filled in the depression 25 can be surely removed. , No polycrystalline silicon remains in the depression 25. Therefore, it is possible to reliably prevent a short circuit.

(5) Formation of Source / Drain As shown in FIG. 17, a resist layer R5 covering the n-type retrograde well 30 is formed. Using the resist layer R5 as a mask, phosphorus or the like is ion-implanted into the p-type retrograde well 32 to form a low-concentration n-type impurity diffusion layer 50a constituting source / drain regions.

After removing the resist layer R5, a resist layer R6 covering the p-type retrograde well 32 is formed as shown in FIG. Using the resist layer R6 as a mask, boron or the like is ion-implanted into the n-type retrograde well 30 to form a low-concentration p-type impurity diffusion layer 60a constituting source / drain regions.

Next, after removing the resist layer R6, the CV
An insulating layer (not shown), for example, a silicon nitride film, a silicon oxide film, or the like is formed on the entire surface by the D method or the like.
Next, as shown in FIG. 19, the sidewall insulating film 70 is formed by anisotropically etching the insulating layer by reactive ion etching or the like.

Next, as shown in FIG. 20, a resist layer R7 covering the n-type retrograde well 30 is formed. Using the resist layer R7, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as phosphorus is
Ions are implanted into the p-type retrograde well 32 to form a high-concentration n-type impurity diffusion layer 50b. This allows
An n-type impurity diffusion layer 50 having an LDD structure is formed.

Next, after removing the resist layer R7, FIG.
As shown in FIG. 1, a resist layer R8 covering the p-type retrograde well 32 is formed. Using the resist layer R8, the gate electrode 46, and the sidewall insulating film 70 as a mask, an impurity such as boron is ion-implanted into the n-type retrograde well 30 to form a high-concentration p-type impurity diffusion layer 60b. I do. Thereby, the p-type impurity diffusion layer 60 having the LDD structure is formed.

Next, the resist layer R8 is removed by ashing to complete the semiconductor device 100 according to the present embodiment as shown in FIG.

The characteristic feature of this embodiment is that the edge portion is formed into a rounding shape by a method including the following steps.

That is, 1) a step of etching the mask layer 14 in a reverse taper shape, and 2) anisotropic etching of the silicon substrate 10 using the mask layer 14 as a mask, thereby forming an end portion of the surface of the element formation region. Is exposed, and a trench 16 is formed, and 3) a step of oxidizing the exposed surface of the silicon substrate 10 has a rounded edge portion.

According to this method, except that the etching of the mask layer 14 and the etching of the silicon substrate 10 for forming the trench 16 are performed under specific conditions, the edge portion is formed in a rounding shape in the same manner as the conventional method. Can be Therefore, the present embodiment has an advantage that the edge portion can be formed in a rounding shape by a simple process without adding a special step.

Further, in the present embodiment, the radius of curvature of the edge portion having the rounding shape can be easily controlled for the following reason. If necessary, the rounding shape having the large radius of curvature can be changed. This has the advantage that an edge portion having the same can be obtained.

First, since the edge of the element formation region is exposed and is not covered with the stopper layer 14 as in the conventional example, the edge is oxidized when the edge is oxidized.
Because it is not affected.

Second, since the end of the element formation region is exposed, the oxidized species easily enters the edge, and the oxidation time can be shortened.

Since the width of the recess 25 is increased by forming the edge portion in a rounding shape, the ratio of width to depth (width / depth) can be reduced, and the recess 25 is made gentle. be able to. Therefore, when etching the electrode material (for example, polycrystalline silicon) thereafter, the electrode material filled in the recess 25 can be reliably removed, and as a result, a short circuit of the circuit can be reliably prevented. .

Further, as shown in FIG.
It has a shape that spreads outward toward the silicon substrate 10, and the end of the protruding portion 22 covers the end of the element formation region. Since such an end of the protruding portion 22 exists, the inclination of the insulating layer in the recess 25 can be surely made gentle.

The above embodiment can be variously modified without departing from the gist of the present invention.

[0072]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view schematically showing steps of a method of manufacturing the semiconductor device according to the embodiment.

FIG. 3 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 4 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 5 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 6 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 7 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 8 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 9 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 10 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 11 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 12 is a cross-sectional view schematically showing a step of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 13 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the embodiment.

FIG. 14 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 15 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 16 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 17 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 18 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 19 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 20 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 21 is a cross-sectional view schematically showing a step of the method for manufacturing the semiconductor device according to the embodiment.

FIG. 22 is a cross-sectional view schematically showing a semiconductor device according to an embodiment.

FIG. 23 is a schematic cross-sectional view in which the depression in FIG. 11 is enlarged.

FIG. 24 is a cross-sectional view schematically showing steps of a method of manufacturing a semiconductor device according to a conventional example.

FIG. 25 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 26 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 27 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 28 is an enlarged schematic cross-sectional view of the depression in FIG. 27;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Pad layer 14 Mask layer 16 Trench 18 Trench oxide film 20 Insulating layer 22 Projection 23 Trench element isolation region 24 Sacrificial oxide film 25 Indentation 26 Oxide film 28 Gate oxide film 30 n-type retrograde well 32 p-type Retrograde well 40 polycrystalline silicon layer 42 metal silicide layer 44 silicon oxide layer 46 gate electrode 50 n-type impurity diffusion layer 50a low concentration n-type impurity diffusion layer 50b high concentration n-type impurity diffusion layer 60 p-type impurity diffusion layer 60a Low-concentration p-type impurity diffusion layer 60b High-concentration p-type impurity diffusion layer 70 Sidewall insulating film 80 n-type MOS element 82 p-type MOS element 100 Semiconductor device

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device having a trench element isolation region including the following steps (a) to (f). (A)
Forming a pad layer on the surface of the silicon substrate, (b)
Forming a mask layer on the surface of the pad layer;
(C) etching the mask layer and the pad layer into a predetermined pattern, and etching the mask layer into an inversely tapered shape that spreads outward as the distance from the silicon substrate increases; Etching the silicon substrate using the mask layer as a mask to form an element isolation groove, anisotropically etching the silicon substrate, and removing an edge of a surface of a region of the silicon substrate where an element is formed. Exposing, (e) oxidizing the exposed surface of the silicon substrate to make an upper edge portion of the silicon substrate a rounding shape, and (f) filling the element isolation trench with an insulating layer. Forming a trench element isolation region. 2. The mask layer formed in the step (c) according to claim 1, wherein an angle between a side surface of the mask layer and a surface of a region of the silicon substrate where an element is formed is 70 to 200. A method for manufacturing a semiconductor device having a trench element isolation region of 85 °. 3. The method of manufacturing a semiconductor device having a trench element isolation region according to claim 1, wherein the etching in the step (d) is reactive ion etching. 4. The method according to claim 1, wherein the width of the exposed end of the surface of the region of the silicon substrate where the element is formed, formed in the step (d), is: A method for manufacturing a semiconductor device having a trench element isolation region of 10 to 55 nm.