JP2000196374A - Switching amplifier using ΔΣ modulation - Google Patents

Abstract

[PROBLEMS] To respond to a 1-bit signal obtained by a ΔΣ modulation circuit 23, a semiconductor power amplifying element in a constant voltage switch 24 operates in a saturation region, and switches a high voltage from a power supply. , A switching amplifier 2 that amplifies an acoustic signal with high efficiency by smoothing with an LPF 25.
1 enables input of a digital 1-bit signal. SOLUTION: A 1-bit signal source 22 is fetched together with the 1-bit signal and a clock signal used for generating the 1-bit signal, and converted into a timing signal synchronized with the 1-bit signal created by a timing control circuit 31. In response, matching block 32 samples the input 1-bit signal, and in adder 33, ΔΣ on the subsequent stage
The feedback signal obtained by defining the operations of the modulation circuit 23 and the constant voltage switch 24 by the timing signal is subtracted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching amplifier using .DELTA..SIGMA. Modulation which is preferably implemented in relation to an audio signal and which can amplify the audio signal and the like with high efficiency.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an electrical configuration of a switching amplifier 1 using a typical prior art .DELTA..SIGMA. Modulation. An analog input audio signal from the analog signal source 2 is input to the switching amplifier 1, and
Σ Converted into a 1-bit digital signal by the modulation circuit 3.

The ΔΣ modulation circuit 3 is provided, for example, in FIG.
As shown in the figure, an integration configured to include a cascade-connected high-order integrator for sequentially integrating the input audio signal, and an adder for mutually adding outputs from the respective integrators. An adder / adder group 4, a quantizer 5 for quantizing an output from the adder of the integrator / adder group 4 into a 1-bit signal,
A delay unit 6 for delaying the one-bit signal from the quantizer 5 by one bit, a digital / analog converter 7 for digital-to-analog conversion of the one-bit signal from the delay unit 6,
And an adder 8 for subtracting an audio signal fed back from the digital / analog converter 7 from an input audio signal from the analog signal source 2. Thereby, feedback control is realized so that the 1-bit signal from the quantizer 5 corresponds to the input analog audio signal.

The 1-bit signal from the quantizer 5 is supplied to a constant voltage switch 9, and a pulse signal of a predetermined constant voltage corresponding to the generated 1-bit signal is converted into an analog audio signal by a low-pass filter 10. After being demodulated, it is output and sonicated by the speaker 11.

The switching amplifier 1 configured as described above does not use the linear region (unsaturated region) of the semiconductor power amplifying element as in the conventional amplifier, but uses the semiconductor power amplifier used in the constant voltage switch 9. Since the amplification element is used in a non-linear range (saturation range), there is an advantage that power amplification can be performed with extremely high efficiency.

[0006]

On the other hand, the 1-bit signal obtained by the ΔΣ modulation has an effective frequency band by appropriately selecting the coefficients of the integrators and adders in the integrator / adder group 4. It has an excellent feature that a frequency characteristic can be set according to a sound source or the like, such as widening or widening a dynamic range. For this reason, CDs (compact discs) and DVDs
(Digital Video Discs)
With the adoption of bit signals, commercialization is about to begin next year.

Therefore, the switching amplifier 1 described above
In this case, it is desired to directly input a 1-bit signal.
Even if the analog converter 7 is deleted and the 1-bit signal is simply fed back to the adder 8, the rising or falling timing of the fed-back 1-bit signal can be calculated as follows.
There is a problem that the rising or falling timing of the input audio signal from the signal source and the sampling timing of the integrator / adder group 4 do not match each other, and a normal operation cannot be performed.

An object of the present invention is to provide a switching amplifier using ΔΣ modulation that can perform a normal operation on a 1-bit signal input.

[0009]

Means for Solving the Problems Δ according to the invention of claim 1
In a switching amplifier using Σ modulation, a ΔΣ modulation circuit ΔΣ modulates an input signal, and in response to the modulated signal, a switching circuit switches a predetermined constant voltage from a power supply, and the switching output is converted to an analog signal by a low-pass filter. In the switching amplifier using ΔΣ modulation, the input signal is a 1-bit signal, and the Δ 信号 modulation is performed in response to a clock signal from an input signal source.
A timing control circuit that generates a timing signal that defines the operation timing of the modulation circuit and the switching circuit; a feedback loop that feeds back an output signal of the switching circuit to an adder at an input stage of the ΔΣ modulation circuit; Input 1
A matching circuit for inputting a unit pulse whose time axis is defined by the timing signal to the ΔΣ modulation circuit in response to the bit signal.

According to the above configuration, the switching amplifier is supplied with a 1-bit signal as an input signal to be subjected to ΔΣ modulation such as an audio signal, and a clock input terminal is provided in accordance with the input signal. A clock signal from a source is input from the clock input terminal to the timing control circuit. The timing signal generated by the timing control circuit defines the sampling timing of the integrator / adder group and the quantizer in the ΔΣ modulation circuit and ON / O of the switching circuit.
FF timing is defined. Thereby, the ΔΣ
From the output side of the quantizer to the adder at the input stage of the modulation circuit,
Alternatively, the timing of the feedback signal provided from the output side of the switching circuit via the attenuator is also defined.

On the other hand, the input 1-bit signal is also generated by the matching circuit into an accurate unit pulse whose time axis is defined in response to the timing signal. And the timing of the feedback signal coincide with each other, and a normal operation as a switching amplifier can be realized for a 1-bit signal input.

Further, the switching amplifier using ΔΣ modulation according to the invention of claim 2 comprises: a noise level detecting means for detecting a quantization noise level of the input 1-bit signal;
The quantization noise level of the ΔΣ modulation circuit is stored in advance for each of a plurality of combinations of the coefficients in the ΔΣ modulation circuit, and a desired dynamic range is obtained in response to the detection result of the noise level detection means. And a coefficient selecting means for selecting a combination of coefficients in the ΔΣ modulation circuit so that the quantization noise level of the ΔΣ modulation circuit is smaller than the quantization noise level of the input 1-bit signal. .

According to the above configuration, the input signal is a one-bit signal, so that the input one-bit signal and the switching amplifier have quantization noise characteristics. Will be. As described above, the quantization noise characteristic can be changed by changing the coefficients of the integrator and the adder in the ΔΣ modulation circuit. The combination of the coefficients is selected so that the quantization noise level on the switching amplifier side is lower than the quantization noise level of the input 1-bit signal.

That is, when the frequency at which the quantization noise level reaches a peak value, for example, V1, up to a desired frequency band of the input 1-bit signal is F1, for example, the dynamic range is a level defined by the peak value V1. When a peak value of the quantization noise level, for example, V2 appears at a frequency outside the desired frequency band of the input 1-bit signal, for example, F2, the switching amplifier side, even if exceeding the peak value V2, The combination of the coefficients is selected so that the level does not exceed the level defined by the peak value V1 within the desired frequency band.

Therefore, within the desired dynamic range, the quantization noise level on the switching amplifier side does not exceed the quantization noise level of the input 1-bit signal.
At least, the dynamic range of the input 1-bit signal can be secured.

Furthermore, in the switching amplifier using ΔΣ modulation according to the third aspect of the present invention, for example, as shown in FIG.
A constant voltage source; a first switch for connecting the capacitor to the constant voltage source in the first half of the input 1-bit signal; and a positive / negative switch for the capacitor in the second half of the input 1-bit signal. A second switch for connecting a terminal to each of the positive and negative output lines; and a second switch for selectively driving the positive and negative output lines to a pair of output terminals, one polarity or the other polarity, in response to the input 1-bit signal. And a third switch connected by an input stage of the ΔΣ modulation circuit. Is smaller by a predetermined ratio determined by

According to the above arrangement, the capacitor is charged to the predetermined voltage accurately by the constant voltage source in the first half of the input 1-bit signal, and this voltage is charged in the second half of the input 1-bit signal. In addition, one polarity or the other polarity is output between the pair of output terminals. That is, for example, when the voltage of the constant voltage source is set to +5 V, +5 V or -5 V is output to the output terminal. Therefore, the accurate unit pulse is output from the output terminal.

The integrated value of the unit pulse is adjusted by an attenuator or the like interposed in a feedback loop so as to be smaller by a predetermined ratio than the integrated value of the feedback value. -Oscillation due to excessive input to the adder group can be prevented.

In the switching amplifier using Δ 用 い る modulation according to the present invention, the timing control circuit takes in a clock signal from the input signal source and removes a jitter component; PL
A clock signal comprising: a multiplier for forming an L loop for making a frequency of an output signal of the PLL circuit an integral multiple of a predetermined number; and a phase adjuster for defining a switching timing of an output from the multiplier. A timing signal having a frequency that is an integral multiple of the timing signal is generated.

According to the above configuration, the jitter component of the clock signal is first removed in the PLL circuit. The P
The multiplier oscillates a signal of a predetermined integer multiple with respect to the output signal of the LL circuit. The PLL circuit has a frequency divider corresponding to the reciprocal of the multiplier. From the loop, a signal having a constant wavelength and an integer multiple of the clock signal is output. The timing of this signal is adjusted by the phase adjuster, and is output as the timing signal. Thus,
Oversampling can be realized on the ΔΣ modulation circuit side without losing the accuracy of the input 1-bit signal, and a band wider than the transmission band of the input 1-bit signal can be secured.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an electrical configuration of a switching amplifier 21 according to one embodiment of the present invention.
The switching amplifier 21 of the present invention includes a 1-bit signal source 2
Thus, the 1-bit signal source 22 outputs a 1-bit signal and a clock signal used to generate the 1-bit signal. You. In this switching amplifier 21, the ΔΣ modulation circuit 23 includes a constant voltage switch 24, and responds to the 1-bit signal obtained by the quantizer 35 to
4 is similar to the switching amplifier 1 shown in FIG. 7 in that a predetermined constant voltage from a power supply is switched, the switching output is converted into an analog audio signal by a low-pass filter 25, and the sound is converted from a speaker 26. .

The clock signal is input to a timing control circuit 31, which is described later.
As a result, the timing signal is generated at a predetermined integer multiple of the clock signal and stabilized at a constant period. On the other hand, the one-bit signal is input to a matching circuit 32, in which a time axis is defined by the timing signal as described later.
The input 1-bit signal is converted into a predetermined integer multiple of unit pulses corresponding to a high level or a low level of the input 1-bit signal, and ΔΣ
The signal is provided to the modulation circuit 23.

In the ΔΣ modulation circuit 23, the unit pulse is subjected to a subtraction of a feedback signal described later in an adder 33, and is provided to an integrator / adder group 34. The integrator / adder group 34 is composed of, for example, an integrator and an adder using a switched capacitor as disclosed in Japanese Patent Application No. 9-266981 previously proposed by the present applicant. Is added to the quantizer 35.
Are quantized by 1 bit. The operation timing of the switches in the integrator / adder group 34, that is, the sampling timing and the sampling timing of the quantizer 35 are defined by the timing signal.

A one-bit signal varying from a predetermined small amplitude, for example, between 0 V and 5 V, from the quantizer 35 is input to the constant voltage switch 24, and a signal having a large amplitude is supplied by a high voltage from the power supply, for example, 100V. And is given to the low-pass filter 25. The constant voltage switch 24
Is also provided as a feedback signal to the adder 33 via an attenuator 36.

FIG. 2 is a block diagram showing an example of the configuration of the timing control circuit 31. The timing control circuit 31 includes a PLL circuit 41, a frequency multiplier 42, and a phase adjuster 43. The PLL circuit 41 and the frequency doubler 42 form a PLL loop.
In accordance with the control voltage from the LL circuit 41, a signal having a frequency that is a predetermined integer multiple of the clock signal from the one-bit signal source 22 is oscillated. This oscillation signal is fed back to the PLL circuit 41, is divided by a frequency divider in the PLL circuit 41, and is compared with the clock signal in phase.

Therefore, the oscillation signal of the frequency doubler 42 is a signal obtained by removing the jitter component from the clock signal and having the predetermined integral multiple of the clock signal. This multiplier 42
Of the oscillation signal is subjected to phase adjustment in a phase adjuster 43, and the matching circuit 32,
The integrator / adder group 34, the quantizer 35, and the constant voltage switch 24 are provided. Therefore, the timing signal becomes a clock signal from the 1-bit signal source, that is, a signal that is a predetermined integer multiple of the 1-bit signal without deteriorating the accuracy of the 1-bit signal, and the 1-bit signal is over-synchronized. Will be sampled and the 1
A wider transmission band is secured in the switching amplifier 21 than the transmission band of the bit signal.

FIG. 3 is a block diagram showing an example of the configuration of the matching circuit 32. This matching circuit 32
Is realized by a switched capacitor, and both terminals of the capacitor C are connected to the first switches S11 and S12.
Are connected to the input terminals P11 and P12, respectively. A predetermined voltage, for example, 5 V, is applied from the constant voltage source 44 to the input terminals P11 and P12. Both terminals of the capacitor C are also connected to a second switch S2.
1 and S22, the positive and negative output lines φ
1 and φ2.

The output line φ1 on the high level side is selectively connected to output terminals P21 and P22 via third switches S311 and S321, respectively. Similarly, the low-level output line φ2 is connected to the third switch S32
2, S312 and output terminals P21, P2, respectively.
2 is selectively connected.

The switches S11 and S12 and the switches S21 and S22 are operated in opposite phases to each other by the inverter B1 with respect to the timing signal.
The operation patterns are shown as "1" and "1" in FIG.
Indicated by “2”. Also, switches S311 and S312,
The switches S321 and S322 operate in opposite phases to each other with respect to the 1-bit signal by the inverter B2, and their operation patterns are indicated by "H" and "L".

FIG. 4 is a timing chart for explaining the operation of the matching circuit 32 configured as described above. In FIG. 4, for simplicity of explanation,
Although the timing signal is assumed to have the same frequency as the clock signal from the 1-bit signal source 22, due to the above-described oversampling, the switches S11, S12; S21, S22 are actually within the period of the 1-bit signal.
Performs the ON / OFF operation of the predetermined integral multiple.

As shown in FIG. 4, when the timing signal and the clock signal have the same frequency,
In the first half period of the input 1-bit signal, for example, the switches S11 and S12 are turned on, and the switches S21 and S22 are turned on.
Is turned off, and the switch S11,
S12 is turned off, and switches S21 and S22 are turned on.

On the other hand, when the input 1-bit signal is at the high level, the switches S311 and S312 are turned on, the switches S321 and S322 are turned off, and the output terminal P21
Is connected to the high-level output line φ1, and the output terminal P22 is connected to the low-level output line φ2.
On the other hand, when the input 1-bit signal is at the low level, the switches S311 and S312 are turned off, the switches S321 and S322 are turned on, the output terminal P21 is connected to the low-level output line φ2, and the output terminal P2
2 is connected to the high-level output line φ1.

Therefore, in the first half of the input 1-bit signal, the switches S11 and S12 are turned on, and the capacitor C is charged to 5V by the constant voltage source 44. At this time, the switches S21 and S22 are set to O
The output voltage Vout between the output terminals P21 and P22 is 0V.

On the other hand, when the input 1-bit signal is at a high level in the latter half cycle of the input 1-bit signal, the output voltage Vout becomes +5 V,
-5V when the input 1-bit signal is low level
Becomes Thus, from the matching circuit 32,
In synchronization with the timing signal, a unit pulse having a constant integrated value of the peak value and the pulse width is a one-bit signal output V
Output as out.

The feedback signal is subtracted from the output Vout in the adder 33.
Here, with respect to the output Vout having an amplitude of ± 5 V, the output from the constant voltage switch 24 having an amplitude of ± 100 V is attenuated by an attenuator 36 to be the feedback signal. The attenuation rate of the attenuator 36 is such that the integrated value of the peak value and the pulse width in the feedback signal is
The output Vout is selected so as to be larger by a predetermined ratio than the integrated value of the peak value and the pulse width of the output Vout, and the ratio is determined by the oscillation limit of the integrator / adder group 34. Thus, the oscillation is suppressed because the integrated value of the feedback signal is larger than the integrated value of the output Vout of the one-bit signal from the matching circuit 32.

Referring to FIG. 1, the 1-bit signal and clock signal from 1-bit signal source 22 are also applied to noise level detection circuit 37. On the other hand, a preset coefficient unit 38 is provided in association with the integrator / adder group 34, and a plurality of types of respective coefficient groups a of each integrator and adder stored in the preset coefficient unit 38 are provided. , B, and c are selectively set to corresponding integrators and adders in the integrator / adder group 34 via a switch 39 in response to a switching signal from the noise level detection circuit 37. .

Each of the coefficient groups a, b, and c is an oscillation limit value, that is, a value that defines the upper limit of the level of the transmission area, noise, that is, a value that defines the lower limit of the level of the transmission area, and an effective frequency. It is determined in advance according to how much weight is assigned to which parameter among parameters such as a band, that is, a transmittable frequency band, and stored in the preset coefficient unit 38.

FIG. 5 is a block diagram showing a configuration example of the noise level detection circuit 37. The input 1-bit signal is sampled in synchronization with the clock signal in the latch unit 45, and the frequency analysis unit 46 converts the sampled binary data from the sampled binary data in real time using, for example, FFT (fast Fourier transform). Is extracted.

The minimum value holding section 47 separates the changing transmission signal component from the unchanged quantization noise component by holding the minimum value. That is, the minimum value of each held spectrum is determined as the quantization noise floor component.

The noise distribution determination unit 48 determines a quantization noise distribution from the hold value of the minimum value hold unit 47,
A noise level in the transmission area, that is, a dynamic range and an effective frequency band are estimated. On the other hand, when the coefficient groups a, b, and c preset in the preset coefficient unit 38 are set in the noise distribution determination unit 48, the quantization noise distribution on the switching amplifier 21 side is set in advance. The coefficients are stored so that the noise floor of the switching amplifier 21 does not protrude within the dynamic range of the input 1-bit signal.

That is, a coefficient group previously set in the integrator / adder group 34, for example, a is a coefficient group that emphasizes the effective frequency band, and the quantization noise level of the switching amplifier 21 is as shown in FIG. As shown, when the effective frequency band F1 = 20 kHz and the dynamic range D1 = −90 dB within the effective frequency band F1,
If the quantization noise level of the input 1-bit signal is set, for example, to emphasize the dynamic range, and the effective frequency band F2 = 15 kHz and the dynamic range D2 = 100 dB as shown in FIG. Signal quantization noise floor and switching amplifier 21
And the higher of the two results in the quantization noise distribution of the output audio signal, and as shown in FIG. 6C, both the effective frequency band and the dynamic range are impaired. Would.

On the other hand, by switching the coefficient group to, for example, b, as shown in FIG. 6D, the effective frequency band F3 and the dynamic range D3 are respectively changed to the effective frequency band F1 and the dynamic range D3.
It is ensured to be equal to 1 and changed so that quantization noise is distributed in the remaining area.

As described above, in the switching amplifier 21 according to the present invention, the clock signal is first taken in from the 1-bit signal source 22 in response to the conversion of the input signal into a 1-bit signal.
Based on the timing signal generated by the timing control circuit 31, the sampling timing of the matching circuit 32, the integrator / adder group 34, and the quantizer 35 is defined, and the switching operation of the constant voltage switch 24 is controlled. １ modulation can be performed by directly inputting a 1-bit signal reproduced from a CD or DVD.

Further, the timing control circuit 31 generates a timing signal having a frequency of a predetermined integer multiple synchronized with the clock signal, whereby the input 1
The oversampling of the bit signal is realized and the input 1
The effective frequency band and the dynamic range on the switching amplifier 21 side can have a sufficient margin with respect to the transmission frequency band and the dynamic range of the bit signal.

Further, the integral value of the feedback signal from the attenuator 36 is increased by a predetermined ratio with respect to the integral value of the output Vout of the unit pulse generated by the matching circuit 32, and the feedback subtraction value is made larger than the input signal. Since it is made large, oscillation due to excessive input to the integrator / adder group 34 can be prevented.

Further, the noise level detection circuit 37 detects the quantization noise floor of the input 1-bit signal, and the integrator / adder group 34 so that the noise floor of the switching amplifier 21 does not protrude within the dynamic range. Is performed, the dynamic range of the input 1-bit signal can be secured even when the oversampling is not performed.

[0048]

According to the switching amplifier using Δ ス イ ッ チ ン グ modulation according to the first aspect of the present invention, as described above, a Δ 変 調 modulation circuit switches a constant voltage by a modulation signal obtained by Δ 入 力 modulating an input signal, and the switching is performed. In a switching amplifier using ΔΣ modulation in which an output is converted into an analog signal by a low-pass filter and output, a clock signal used to generate the 1-bit signal is captured in order to convert the input signal into a 1-bit signal. In response to the timing signal generated based on the clock signal, the matching circuit generates an accurate unit pulse whose time axis is defined from the input 1-bit signal. The feedback signals obtained by operating the integrators / adder groups and the quantizers in the modulation circuit are added.

Therefore, the timing of the unit pulse coincides with the timing of the feedback signal, and a normal operation as a switching amplifier can be realized for a 1-bit signal input.

Further, the switching amplifier using ΔΣ modulation according to the second aspect of the present invention detects the quantization noise level of the input 1-bit signal as described above, and within the desired dynamic range, the switching amplifier side. The combination of the coefficients of the integrator and the adder in the ΔΣ modulation circuit is selected so that the quantization noise level becomes smaller than the quantization noise level of the input 1-bit signal.

Therefore, within the desired dynamic range, at least the dynamic range of the input 1-bit signal is ensured without the quantization noise level on the switching amplifier side exceeding the quantization noise level of the input 1-bit signal. Can be.

Furthermore, in the switching amplifier using ΔΣ modulation according to the third aspect of the present invention, as described above, for example, the matching circuit includes a capacitor, a constant voltage source, and a half of the first half of the input 1-bit signal. A first switch for connecting the capacitor to the constant voltage source in a cycle, and a second switch for connecting the positive and negative terminals of the capacitor to the positive and negative output lines in the latter half of the input 1-bit signal, respectively. , Selectively driven in response to the input 1-bit signal, the positive and negative output lines being connected to a pair of output terminals,
A third switch connected with one polarity or the other polarity so that an accurate unit pulse is output, and furthermore, an integrated value of the unit pulse is output to the input stage of the ΔΣ modulation circuit. The integrated value of the feedback value by the feedback loop subtracted by the adder is reduced by a predetermined ratio determined by the oscillation limit.

Therefore, oscillation due to excessive input to the integrator / adder group in the ΔΣ modulation circuit can be prevented.

According to a fourth aspect of the present invention, in the switching amplifier using ΔΣ modulation, as described above, the timing control circuit includes a PLL circuit that takes in a clock signal from the input signal source and removes a jitter component. , The PL
A multiplier configured to form an L circuit and a PLL loop, the frequency of the output signal of the PLL circuit being a predetermined integral multiple, and a phase adjuster defining switching timing of the output from the multiplier; A timing signal having a frequency that is an integral multiple of the clock signal is generated.

Therefore, oversampling can be realized on the ΔΣ modulation circuit side without losing the accuracy of the input 1-bit signal, and a band wider than the transmission band of the input 1-bit signal can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a switching amplifier using ΔΣ modulation according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a timing control circuit in the switching amplifier shown in FIG.

FIG. 3 is a block diagram showing one configuration example of a matching circuit in the switching amplifier shown in FIG. 1;

FIG. 4 is a timing chart for explaining an operation of the matching circuit shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration example of a noise level detection circuit in the switching amplifier shown in FIG.

FIG. 6 is a waveform chart for explaining the operation of the noise level detection circuit shown in FIG.

FIG. 7 is a block diagram illustrating the electrical configuration of a typical prior art switching amplifier using ΔΣ modulation.

[Explanation of symbols]

Reference Signs List 21 switching amplifier 22 1-bit signal source 23 ΔΣ modulation circuit 24 constant voltage switch (switching circuit) 25 low-pass filter 26 speaker 31 timing control circuit 32 matching circuit 33 adder 34 integrator / adder group 35 quantizer 36 attenuator (feedback) Loop) 37 noise level detection circuit (noise level detection means) 38 preset coefficient unit (coefficient selection means) 39 switch (coefficient selection means) 41 PLL circuit 42 frequency multiplier 43 phase adjuster 44 constant voltage source 45 latch unit 46 frequency analysis Unit 47 minimum value hold unit 48 noise distribution determination unit C capacitor S11, S12 switch (first switch) S21, S22 switch (second switch) S311, S312; S321, S322 switch (third switch) φ1, φ2 output line

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) UW01

Claims (4)

[Claims] A .DELTA..SIGMA. Modulation circuit modulates an input signal by .DELTA..SIGMA., And a switching circuit switches a predetermined constant voltage from a power supply in response to the modulation signal. The switching output is converted to analog by a low-pass filter and output. A switching amplifier using ΔΣ modulation, wherein the input signal is a 1-bit signal, and a timing control circuit for generating a timing signal defining operation timing of the ΔΣ modulation circuit and the switching circuit in response to a clock signal from an input signal source A feedback loop that feeds back the output signal of the switching circuit to the adder at the input stage of the ΔΣ modulation circuit; A unit pulse whose axis is specified is input to the ΔΣ modulation circuit A switching circuit using Δ modulation. 2. A noise level detecting means for detecting a quantization noise level of the input 1-bit signal; and a quantization noise level by the ΔΣ modulation circuit for each of a plurality of combinations of coefficients in the ΔΣ modulation circuit. The quantization noise level by the ΔΣ modulation circuit is smaller than the quantization noise level of the input 1-bit signal within a desired dynamic range in response to the detection result of the noise level detection means. In addition, the Δ
2. The method according to claim 1, further comprising: a coefficient selection unit that selects a combination of coefficients in the modulation circuit.
ス イ ッ チ ン グ Switching amplifier using modulation. 3. An integrated value of the unit pulse is smaller by a predetermined ratio determined by an oscillation limit than an integrated value of a feedback value by a feedback loop subtracted by an adder of an input stage in the ΔΣ modulation circuit. 3. The switching amplifier according to claim 1, wherein the switching amplifier uses Δ ス イ ッ チ ン グ modulation. 4. A timing control circuit comprising: a PLL circuit for receiving a clock signal from the input signal source and removing a jitter component; and forming a PLL loop with the PLL circuit, and controlling a frequency of an output signal of the PLL circuit in advance. And a phase adjuster that regulates the switching timing of the output from the multiplier, and generates a timing signal having a frequency that is an integral multiple of the clock signal. A switching amplifier using ΔΣ modulation according to claim 1.