JP2000195885A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a highly reliable solder joint and to control the thickness of an electrode / barrier metal layer in a semiconductor device in which a semiconductor element and a circuit board are flip-chip joined with Pb-free solder. The purpose is to make it unnecessary and to contribute to the reduction of manufacturing costs. SOLUTION: Ni-Cr, Ni is formed on a semiconductor element 11.
-Mo or Ni-W alloy film is formed as the first electrode / barrier metal layer 13a by electroless plating, and the Ni-Cr, Ni-Mo or Ni-W alloy film is also formed on the circuit board 21 as the second electrode. The first electrode / barrier metal layer 13a is formed by electroless plating as an electrode / barrier metal layer 24a.
A solder bump 15a of Pb-free solder is formed on a, and the solder bump 15a is pressed against the second electrode / barrier metal layer 24a to perform flip chip bonding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element and a circuit board are flip-chip bonded with lead (Pb) -free solder containing tin (Sn) as a main component. The present invention relates to a technique for forming an electrode used for bonding.

[0002]

2. Description of the Related Art In recent years, with the high-density mounting of electronic components,
As the number of input / output terminals has increased and the pitch between terminals has been reduced, a flip-chip bonding method, which has a shorter wiring length and can perform collective bonding, has been used as a bonding method between an LSI chip and a substrate. It has become mainstream.

In flip chip bonding, a metal bump (typically, a solder bump) formed on an electrode (pad) of an LSI chip is connected to a corresponding electrode (pad) on a circuit board.
To directly bond the bare chip of the semiconductor element and the substrate. As a material for forming the solder bump, an alloy of Pb and Sn, particularly a solder containing Pb as a main component (hereinafter, referred to as “Pb-based solder” for convenience) has been often used. One example using such a Pb-based solder is shown in FIG.

FIG. 1 schematically shows a configuration of a flip chip bonding portion in a semiconductor device according to a conventional example in the form of a sectional view.

In the figure, reference numeral 11 denotes a semiconductor element formed on a silicon (Si) substrate constituting a main body of a semiconductor chip;
2 is a titanium (Ti) film, 13 is a nickel (Ni) film, 1
4 is a Pb-based solder (for example, Pb-5% Sn) solder bump, 21 is a circuit board made of alumina, aluminum nitride (AlN) or resin, 22 is a chromium (Cr) film, 2
Reference numeral 3 denotes a copper (Cu) film, 24 denotes a Ni film, and 25 denotes a gold (Au) film.

As shown in the figure, an electrode layer used for soldering between the semiconductor element 11 and the circuit board 21 is an aluminum (Al) electrode (not shown) on the Si substrate of the semiconductor element 11. Ti film 12 and N
The i-film 13 has a film configuration, and the circuit board 21 has a Ni film 24 and an Au film 25 on the Cr / Cu films 22 and 23 constituting the wiring layer in this order.

As a process for manufacturing such a semiconductor device, first, an electrode layer is formed on each of the semiconductor element 11 and the circuit board 21, and then a solder bump 14 is formed on the electrode layer on the semiconductor element 11. Solder bump 1
4 is pressed against the electrode layer on the circuit board 21 as indicated by a thick arrow to perform flip chip bonding. At this time, the solder material (solder bump 1) used for flip chip bonding is used.
Since the content of Sn contained in 4) is about 5% by weight, that is, most of the composition is Pb,
A good solder joint can be formed when flip-chip joining is performed.

However, Pb has many isotopes, and these isotopes are intermediate products or final products in the decay series of uranium (U) and thorium (Th), and helium (He) ) Α-rays are generated from Pb in the solder due to the α-decay that releases atoms. And that α
It has recently been reported that lines reach semiconductor devices (CMOS devices) and cause soft errors. Further, it is known that Pb melts out due to acid rain when it flows into the soil, which affects the environment. Therefore, solder that does not use Pb also from an environmental point of view (hereinafter, referred to as “Pb-free solder”).
Is strongly required.

Therefore, as an example of such a Pb-free solder, a solder containing Sn as a main component having a relatively small amount of radioactive impurities (hereinafter referred to as "Sn-based solder" for convenience) has begun to be used. This Sn-based solder uses silver (A
g), bismuth (Bi), antimony (Sb), zinc (Zn), indium (In) and the like are mixed or added. The amount to be mixed or added differs depending on the temperature hierarchy of the solder material to be used. However, in a solder joint of a CMOS element or the like, a relatively high temperature of 200 ° C. or more containing 90% or more of the Sn composition ratio is included. A melting point solder material is used.

In the following description, "%" means "% by weight" unless otherwise specified.

[0011]

However, when an Sn-based solder having a composition ratio of Sn of 90% or more is used, the film configuration / film thickness of the electrode layer as shown in the above-described conventional example (see FIG. 1). When solder bonding is performed, Ni (13, 24) or Cu (23) of the material constituting each electrode layer reacts with Sn in the solder bumps 14 during the temperature cycle at the time of solder bonding, so that the material in the solder is removed. And Ni-Sn, Cu
An intermetallic compound such as -Sn is formed. As a result, the Ni layer having the largest film thickness in the electrode layer on the semiconductor element 11 is formed.
In particular, the thickness of the film 13 is reduced, the bonding strength is reduced, bumps are broken or broken, and failures such as poor bonding and non-conduction are caused during a reliability test such as a thermal cycle test. There has been a problem that the reliability of the solder joint is reduced.

The present applicant has previously proposed a technique for addressing such a problem (for example, Japanese Patent Application Laid-Open No. H10-413).
No. 03). In this proposed technique, the diffusion of Ni of the material constituting the electrode layer into the solder material is delayed or prevented. As a means for this, a Ni film and a Cr film are formed in layers. This is used as an electrode / barrier metal layer, and this electrode / barrier metal layer is formed by a vacuum deposition method or a sputtering method, and the Cr film is made thinner (200 to 2000 °). That is, the presence of the Cr film can suppress Ni from diffusing into the Sn-based solder. Also, S
By making use of the characteristic that n and Cr do not form a solid solution and do not form an intermetallic compound, and by reducing the thickness of the Cr film, the function as a barrier metal can be maintained without impairing the reliability of the solder joint.

However, in this proposed technique, the electrode /
Since the barrier metal layer is formed in a laminated structure, Ni
It is necessary to control the thickness of the film or the Cr film to an optimum thickness, and there is a disadvantage that the processing for that is complicated. In addition, since the electrode / barrier metal layer is formed by a vacuum deposition method, a vacuum device is required, and there is a disadvantage that the manufacturing cost is increased. Therefore, there is room for improvement.

The present invention has been made in view of the above-mentioned problems in the prior art, and realizes a highly reliable solder joint, eliminates the need for controlling the thickness of the electrode / barrier metal layer, and reduces the manufacturing cost. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can contribute.

[0015]

According to the present invention, there is provided, according to the present invention, a semiconductor device in which a semiconductor element and a circuit board are flip-chip bonded with Pb-free solder containing Sn as a main component. Forming a Ni-Cr, Ni-Mo or Ni-W alloy film containing Ni as a main component on the semiconductor element by electroless plating as a first electrode / barrier metal layer; Ni on
Is formed by electroless plating as a second electrode / barrier metal layer, and the Pb-free solder is formed on the first electrode / barrier metal layer. A method for manufacturing a semiconductor device is provided, wherein a solder bump is formed, and the flip-chip bonding is performed by pressing the solder bump against the second electrode / barrier metal layer.

According to the method of the present invention, each electrode / barrier metal layer of a semiconductor element to be flip-chip bonded and a circuit board is made of Ni--Cr, N by electroless plating.
Since the i-Mo or Ni-W alloy film is provided, the following effects are expected.

First, in the single-layer Ni film structure as shown in the prior art shown in FIG. 1, Ni forms a Ni--Sn intermetallic compound at the time of soldering, and then further forms a lower layer in the solder. Is supplied, and a new growth of a Ni—Sn intermetallic compound layer is repeated. For this reason,
When heated several times above the melting point of the solder, the Ni-Sn layer grows more and more, resulting in the disadvantage that the Ni layer disappears after the process is completed.

On the other hand, in the present invention, Ni—Cr, Ni
-Mo or Ni-W alloy film, Cr, Mo,
Since the metal such as W is a material showing a binary alloy phase diagram of a total solid solution type with Ni, the metal is uniformly mixed with Ni in the alloy at a composition ratio containing Ni as a main component as in the present invention. Exists in a state where On the other hand, S which is the main component of solder
n is equal to or higher than the melting point of the above metal (Cr, Mo, W) (1
(000 ° C. or higher), they do not react and do not mix. As a result, when soldering is performed on these electrodes, an Ni-Sn intermetallic compound is formed during the reaction between the electrodes and the solder bumps during heating of the soldering. , Mo, and W have the effect of suppressing the diffusion of Ni, the diffusion rate of Ni into the solder decreases, and the Ni layer does not disappear due to diffusion even after the soldering is completed. That is, by suppressing the diffusion of Ni into the Sn-based solder (Pb-free solder), it is possible to realize a highly reliable solder joint.

Further, since the first and second electrodes / barrier metal layers (alloy films) are formed by electroless plating,
Metals (Ni, Cr, Mo, W) are evenly distributed in the film,
Since the layered structure does not have the structure as in the prior art (Japanese Patent Application Laid-Open No. 10-41303), it is not necessary to control the film thickness.

Further, since the first and second electrodes / barrier metal layers (alloy films) are formed by electroless plating, a vacuum apparatus as disclosed in the prior art (Japanese Patent Application Laid-Open No. 10-41303) is used. This is unnecessary, and the manufacturing cost can be reduced.

Regarding the method of forming an alloy film, it is difficult to control the composition of the film by ordinary electrolytic plating.
In the vacuum deposition method and the sputtering method described in Japanese Patent Application Laid-Open No. 0-41303, the composition of the film becomes a laminated structure, and after all of Ni is diffused into the solder, each single layer of Cr, Mo, and W comes into contact with Sn. However, there is a problem that the solder material (in this case, Sn, which is a main component of the solder) is repelled to cause chipping of the bumps.
By doing so, such a problem can be solved.

According to a preferred embodiment of the present invention,
Pb-free solder bumps are formed by a transfer bump forming method. In this method, solder bumps are formed from a solder paste, or a solder alloy is formed on a predetermined electrode by a vapor deposition method to form a solder bump. There is a merit that the effect is great in a situation where the melting time is long and the metal of the electrode / barrier metal layer is more easily diffused.

[0023]

FIG. 2 is a cross-sectional view schematically showing a configuration of a flip chip joint in a semiconductor device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a semiconductor element formed on a Si substrate constituting a main body of a semiconductor chip, 12 denotes a Ti film,
13a is an electrode / barrier metal layer (N
Ni-Cr, Ni-Mo or Ni-W containing i as a main component
Alloy film), 14 is an Au film, 15a is a Sn-based solder (P
b free solder) solder bump, 21 is alumina, A
1N or resin circuit board, 22 is a Cr film, 23 is a Cu film, 24a is an electrode / barrier metal layer (Ni-Cr, Ni-Mo or Ni-W alloy containing Ni as a main component) which is a feature of the present invention. Film), 25 denotes an Au film.

In the semiconductor device according to the present embodiment, as a basic process, an electrode / barrier metal layer 13a is formed on a semiconductor element 11 by electroless plating.
An electrode / barrier metal layer 24a is formed on the electrode / barrier metal layer 13a by electroless plating, and a solder bump 15a is formed on the electrode / barrier metal layer 13a. Can be made.

[0026]

EXAMPLE Next, a specific example based on the embodiment of FIG. 2 will be described with reference to Tables 1, 2 and 3 shown below. Tables 1 to 3 show that the content of Cr, Mo, or W in the alloy film forming the electrode / barrier metal layers 13a and 24a is 5% for the first to third examples.
The composition of each metal material (Sn, Ag, Bi, Sb, Zn, In) constituting the solder bump 15a and the flip-chip bonding with respect to each sample at 20% and 40% (35% in the case of W) The relationship between the result of the heat cycle test performed later and the bonding state is shown in comparison with the case of the conventional example.

First Embodiment Table 1 Sample Solder Composition Thermal Cycle Joint Ni Residual Film No. ( Μm ) Cr-5-1 Sn-57Bi-1Ag 300 or more good 4 Cr-5-2 Sn-3.5Ag-5Zn 300 or more good 4 Cr-5-3 Sn-5Sb 300 or more good 4 Cr-5-4 Sn -3.5Ag 300 or more good 4 Cr-5-5 Sn-3.5Ag-5In 300 or more good 4 Cr-20-1 Sn-57Bi-1Ag 300 or more good 4 Cr-20-2 Sn-3.5Ag-5Zn 300 or more good 4 Cr-20-3 Sn-5Sb 300 or more good 4 Cr-20-4 Sn-3.5Ag 300 or more good 4 Cr-20-5 Sn-3.5Ag-5In 300 or more good 4 Cr-40-1 Sn -57Bi-1Ag 300 Good 4 Cr-40-2 Sn-3.5Ag-5Zn 300 Good 4 Cr-40-3 Sn-5Sb 300 Good 4 Cr-40-4 Sn-3.5Ag 300 Good 4 Cr-40-5 Sn -3.5Ag-5In 300 Good 4 Ni-1 Sn-3.5Ag 200 OK 0-1 Ni-2 Sn-48Bi-1Ag 100 OK 0 Conventional example Ni-3 Sn-5Sb 200 OK 0-1 Ni-4 Sn-3.5 Ag-5Zn 150 OK 0 Ni-5 Sn-3.5Ag-5In 150 OK 0 For the semiconductor element 11, a Ti film 12 is formed to about 1000 ° , and then the Cr content is 5%, 20% and 40%.
% Of Ni-Cr alloy film (electrode / barrier metal layer 13a) was formed by electroless plating to a thickness of about 6 μm.
Then, after forming the Au film 14 at about 500 °, solder bumps 15a having the respective compositions shown in Table 1 were formed on the electrodes by the Dimple Plate (DP) method, which is one type of transfer bump formation method. At this time, Pb in the impurities in Sn in the alloy
Was set to 1 ppm or less. Further, the α dose in Sn used was 0.01 cph / cm ² or less. Note that cph represents count / time.

On the other hand, in the same manner as in the case of the semiconductor element 11, the Cr / C
Ni-Cr alloy films (electrode / barrier metal layer 24a) of each composition are formed on the u films 22 and 23 by electroless plating to a thickness of 6 μm.
The Au film 25 was formed to about 500 °.

Next, after the semiconductor element 11 and the circuit board 21 are aligned, a flux is applied to the solder bumps 15a, and the solder bumps 15a are placed in a conveyor furnace in a nitrogen atmosphere (250 ° C.
The semiconductor element 11 and the circuit board 21 were flip-chip bonded at 300 ° C.).

The diameter of the solder bump 15a is 70 to 1
00 μm, pitch between bumps is 150 to 210 μm
And

The reliability was evaluated by measuring the initial resistance immediately after bonding and continuing the heat cycle test (-55 ° C. to 125 ° C.) up to 300 cycles while measuring the resistance every 50 cycles. Was.

As a result, the content of Cr was 5% or 20%.
In the case of (1), a solder joint having a life of 300 cycles or more could be formed, and when the content of Cr was 40%, a solder joint having a life of 300 cycles could be formed. Further, the film thickness of Ni (remaining film thickness) after soldering could be reduced to three times or more as compared with the conventional example, that is, the diffusion amount of Ni could be reduced to one third or less of the conventional example.

Second Embodiment Table 2 Sample Solder Composition Thermal Cycle Joint Ni Residual Film No. ( Μm ) Mo-5-1 Sn-57Bi-1Ag 300 or more good 4 Mo-5-2 Sn-3.5Ag-5Zn 300 or more good 4 Mo-5-3 Sn-5Sb 300 or more good 4 Mo-5-4 Sn -3.5Ag 300 or more good 4 Mo-5-5 Sn-3.5Ag-5In 300 or more good 4 Mo-20-1 Sn-57Bi-1Ag 300 or more good 4 This example Mo-20-2 Sn-3.5Ag-5Zn 300 or more good 4 Mo-20-3 Sn-5Sb 300 or more good 4 Mo-20-4 Sn-3.5Ag 300 or more good 4 Mo-20-5 Sn-3.5Ag-5In 300 or more good 4 Mo-40-1 Sn -57Bi-1Ag 300 Good 4 Mo-40-2 Sn-3.5Ag-5Zn 300 Good 4 Mo-40-3 Sn-5Sb 300 Good 4 Mo-40-4 Sn-3.5Ag 300 Good 4 Mo-40-5 Sn -3.5Ag-5In 300 Good 4 Ni-1 Sn-3.5Ag 200 OK 0-1 Ni-2 Sn-48Bi-1Ag 100 OK 0 Conventional example Ni-3 Sn-5Sb 200 OK 0-1 Ni-4 Sn-3.5 Ag-5Zn 150 OK 0 Ni-5 Sn-3.5Ag-5In 150 OK 0 For the semiconductor element 11, a Ti film 12 is formed on the order of 1000 ° , and then the Mo content is 5%, 20% and 40%.
% Of a Ni-Mo alloy film (electrode / barrier metal layer 13a) was formed to a thickness of about 6 μm by electroless plating.
Then, after forming the Au film 14 at about 500 °, solder bumps 15a having the respective compositions shown in Table 2 were formed on the electrodes by the DP method. At this time, the content ratio of Pb in the impurities in Sn in the alloy was set to 1 ppm or less. Also, α in Sn
The dose was 0.01 cph / cm ² or less.

On the other hand, in the same manner as in the case of the semiconductor element 11, the Cr / C
Ni-Mo alloy films (electrode / barrier metal layer 24a) of each composition are formed on the u films 22 and 23 by electroless plating to a thickness of 6 μm.
The Au film 25 was formed to about 500 °.

Next, after aligning the semiconductor element 11 with the circuit board 21, a flux is applied to the solder bumps 15a, and the solder bumps 15a are placed in a conveyor furnace in a nitrogen atmosphere (250 ° C.
The semiconductor element 11 and the circuit board 21 were flip-chip bonded at 300 ° C.).

The diameter of the solder bump 15a is 70-1.
00 μm, pitch between bumps is 150 to 210 μm
And

The reliability was evaluated by measuring the initial resistance immediately after bonding and continuing the heat cycle test (-55 ° C. to 125 ° C.) up to 300 cycles while measuring the resistance every 50 cycles. Was.

As a result, the content of Mo was 5% or 20%.
When the Mo content was 40%, a solder joint having a life of 300 cycles or more could be formed, and when the Mo content was 40%, a solder joint having a life of 300 cycles could be formed. Further, the film thickness of Ni (remaining film thickness) after soldering could be reduced to three times or more as compared with the conventional example, that is, the diffusion amount of Ni could be reduced to one third or less of the conventional example.

Third Example Table 3 Sample Solder Composition Thermal Cycle Joint Ni Residual Film No. ( Μm ) W-5-1 Sn-57Bi-1Ag 300 or more good 4 W-5-2 Sn-3.5Ag-5Zn 300 or more good 4 W-5-3 Sn-5Sb 300 or more good 4 W-5-4 Sn -3.5Ag 300 or more good 4 W-5-5 Sn-3.5Ag-5In 300 or more good 4 W-20-1 Sn-57Bi-1Ag 300 or more good 4 Example W-20-2 Sn-3.5Ag-5Zn 300 or more good 4 W-20-3 Sn-5Sb 300 or more good 4 W-20-4 Sn-3.5Ag 300 or more good 4 W-20-5 Sn-3.5Ag-5In 300 or more good 4 W-35-1 Sn -57Bi-1Ag 300 Good 4 W-35-2 Sn-3.5Ag-5Zn 300 Good 4 W-35-3 Sn-5Sb 300 Good 4 W-35-4 Sn-3.5Ag 300 Good 4 W-35-5 Sn -3.5Ag-5In 300 Good 4 Ni-1 Sn-3.5Ag 200 OK 0-1 Ni-2 Sn-48Bi-1Ag 100 OK 0 Conventional example Ni-3 Sn-5Sb 200 OK 0-1 Ni-4 Sn-3.5 Ag-5Zn 150 OK 0 Ni-5 Sn-3.5Ag-5In 150 OK 0 For the semiconductor element 11, a Ti film 12 is formed to about 1000 ° , and then the W content is 5%, 20% and 35%.
Ni-W alloy film (electrode / barrier metal layer 1)
3a) was formed about 6 μm by electroless plating. Then, after forming the Au film 14 at about 500 °, the solder bumps 15a having the respective compositions shown in Table 3 were formed on the electrodes by the DP method. At this time, Pb in the impurities in Sn in the alloy
Was set to 1 ppm or less. Further, the α dose in Sn used was 0.01 cph / cm ² or less.

On the other hand, in the same manner as in the case of the semiconductor element 11, the Cr / C
On the u films 22 and 23, Ni—W alloy films of each composition (electrode /
A barrier metal layer 24a) was formed by electroless plating to a thickness of about 6 μm, and an Au film 25 was formed to a thickness of about 500 °.

Next, after the semiconductor element 11 and the circuit board 21 are aligned, a flux is applied to the solder bumps 15a, and the solder bumps 15a are placed in a conveyor furnace in a nitrogen atmosphere (250 ° C.
The semiconductor element 11 and the circuit board 21 were flip-chip bonded at 300 ° C.).

The diameter of the solder bump 15a is 70 to 1
00 μm, pitch between bumps is 150 to 210 μm
And

The reliability was evaluated by measuring the initial resistance immediately after bonding and continuing the heat cycle test (-55 ° C. to 125 ° C.) up to 300 cycles while measuring the resistance every 50 cycles. Was.

As a result, when the W content is 5% or 20%, a solder joint having a life of 300 cycles or more is obtained.
When the W content was 35%, a solder joint having a life of 300 cycles could be formed. Further, the film thickness of Ni (remaining film thickness) after soldering could be reduced to three times or more as compared with the conventional example, that is, the diffusion amount of Ni could be reduced to one third or less of the conventional example.

FIG. 3 schematically shows an application example of the semiconductor device manufactured according to the first to third embodiments.
In the illustrated example, a cross-sectional structure of a semiconductor device manufactured in the form of a semiconductor package 30 is shown.

As shown in FIG.
Is a method in which a semiconductor chip (bare chip of a semiconductor element) 10 is flip-chip bonded to a circuit board 21 (Cr / Cu films 22 and 23 constituting a wiring layer) with solder bumps 15a, and then sealed with a cap 31. Wiring layer (22, 2
The external lead 32 connected to 3) is connected to the circuit board 21.

FIG. 4 schematically shows another application example of the semiconductor device manufactured according to the above-described first to third embodiments. In the illustrated example, the semiconductor device manufactured in the form of a multi-chip module 40 is shown. The external configuration of the device is shown.

As shown in the figure, the multi-chip module 40 is configured by mounting a plurality of semiconductor chips 10 on a circuit board 21 with solder bumps 15a.

[0049]

As described above, according to the present invention, P
When performing flip-chip bonding with Sn-based solder compatible with b-free soldering, highly reliable solder bonding can be realized, and the control of the film thickness of the electrode / barrier metal layer is not required, and the manufacturing cost is reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a configuration of a flip chip bonding portion in a semiconductor device according to a conventional example.

FIG. 2 is a cross-sectional view schematically illustrating a configuration of a flip chip bonding portion in a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing an application example of the semiconductor device according to the embodiment of FIG. 2;

FIG. 4 is a diagram schematically showing another application example of the semiconductor device according to the embodiment of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip 11 ... Semiconductor element 12 ... Ti film 13a ... Electrode / barrier metal layer (Ni-Cr, Ni-M
o ... Ni-W) 14 ... Au film 15a ... Solder bump 21 ... Circuit board (alumina, AlN or resin) 22 ... Cr film 23 ... Cu film 24a ... Electrode / barrier metal layer (Ni-Cr, Ni-M)
o or Ni-W) 25 ... Au film 30 ... Semiconductor package 40 ... Multi-chip module

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device in which a semiconductor element and a circuit board are flip-chip bonded with a lead-free solder containing tin as a main component, wherein nickel containing nickel as a main component is provided on the semiconductor element. An alloy film of chromium, nickel-molybdenum or nickel-tungsten is formed as a first electrode / barrier metal layer by electroless plating, and nickel mainly composed of nickel is formed on the circuit board;
Forming an alloy film of chromium, nickel-molybdenum or nickel-tungsten as a second electrode / barrier metal layer by electroless plating; forming the lead-free solder bump on the first electrode / barrier metal layer; A method of manufacturing a semiconductor device, wherein the flip-chip bonding is performed by pressing a solder bump against the second electrode / barrier metal layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the solder bump of the lead-free solder is formed by a transfer bump forming method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the lead-free solder containing tin as a main component comprises at least one metal selected from silver, bismuth, antimony, zinc, and indium. In this composition, the content of tin is 40 to 95% by weight, the content of bismuth is 1 to 60% by weight, and the content of silver, antimony, zinc and indium is 0.1 to 10% by weight, respectively. A method for manufacturing a semiconductor device, wherein the method is selected in the range described above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said alloy film forming said first and second electrodes / barrier metal layers is made of nickel-chromium. Characterized in that the content of is selected in the range of 0.1 to 40% by weight. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the alloy film forming the first and second electrodes / barrier metal layers is nickel-molybdenum. Characterized in that the content of is selected in the range of 0.1 to 40% by weight. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the alloy film forming the first and second electrodes / barrier metal layers is made of nickel-tungsten. 0.1 to 3
A method of manufacturing a semiconductor device, wherein the method is selected in a range of 5% by weight. 7. A semiconductor device manufactured in the form of a semiconductor package using the semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1. 8. A semiconductor device manufactured in the form of a multi-chip module by mounting a plurality of semiconductor devices manufactured by the method of manufacturing a semiconductor device according to claim 1 on a circuit board. .