JP2000188720A - Driving device for solid-state imaging device - Google Patents

Abstract

(57) [Abstract] [Problem] While making a solid-state imaging device multifunctional and complex,
The number of pins as an IC package is reduced, and low power consumption is realized. Kind Code: A1 A digital signal processing IC supplies serial data synchronized with a clock and a pulse necessary for signal reading of a solid-state imaging device to the solid-state imaging device, and the clock and pulse on the solid-state imaging device are based on the clock and pulse. The serial / parallel converter 516 and the register 517
To realize the multi-functional solid-state imaging device 51 with a small number of pins.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a solid-state image sensor which sets and updates various parameters required for the solid-state image sensor using serial data.

[0002]

2. Description of the Related Art A solid-state image sensor is formed as a CMOS sensor, and its driving pulse is greatly simplified as compared with a CCD. In the conventional CCD sensor, when the horizontal is two phases and the vertical is four phases, there are a positive-phase horizontal drive pulse H1, a negative-phase horizontal drive pulse H2, and a horizontal reset pulse RS as high-speed transfer pulses, and a vertical reset pulse RS as low-speed transfer pulses. There were reset pulses V1-V4. This is because the CCD sequentially reads out signals by a method of transferring charges.

On the other hand, a CMOS sensor has a built-in logic circuit such as a timing signal generator TG and a shift register for generating a pulse necessary for reading in an image sensor. ,
Only the sensor clock SCK, the horizontal reference pulse HP and the vertical reference pulse VP are required.

This is because, in a CMOS sensor, a switch is turned on / off by a binary control signal group generated by a logic circuit in an image sensor to select and read a signal. Compared with the CCD sensor, the driving pulse of the CMOS sensor is very simple, and even when the same video signal is obtained, a small number of driving pulses = pins (terminals)
One advantage was the need for numbers.

On the other hand, a recent image pickup device is provided with a multi-function by a vertical / horizontal inversion readout, a pixel thinning-out mode drive and the like, and a noise reduction circuit (CD) called correlated double sampling.
S), a gain control amplifier, an A / D converter for converting an analog signal to a digital signal, and the like are built in, and the number of pins has been increased by compounding. This tendency is particularly strong in CMOS sensors in which various analog or digital circuits can be integrated into one chip.

However, an A / D that can reduce power consumption by simply setting pins for vertical inversion, setting pins for horizontal inversion, setting pins for pixel thinning mode, gain setting pins for a gain control amplifier, and standby operation. When an on / off setting pin, a digital video signal output pin, and the like are added, the number of pins as a solid-state imaging device increases.

[0007] In this case, the meaning of integrating the CMOS sensor and other circuits into one chip is diminished. The solid-state imaging device receives an optical image on the surface of the chip, performs photoelectric conversion, and reads out and outputs it.
The number of pins cannot be easily increased.

FIG. 5 shows a CMO as a conventional solid-state imaging device.
It is a figure showing an example of a drive using an S sensor. The solid-state imaging device 51 includes a light receiving unit 511 that performs photoelectric conversion,
A timing signal generator 512 for controlling the light receiving unit and generating various pulses for obtaining a video signal, and a noise canceling circuit 5 for removing noise from the obtained video signal
13 and an output amplifier 514.

In order to obtain a video signal, a solid-state image sensor 51
Clock SC required for signal reading from outside
K, a horizontal reference pulse HP, and a vertical reference pulse VP. In addition, an electronic shutter pulse ES for controlling the accumulation time by an electronic shutter, and an up / down inverter signal U for performing upside-down inversion reading setting.
Supply DI.

In the example of FIG. 5, since the solid-state imaging device 51 is not multifunctional and complex, the reading operation of the video signal can be realized by the above five clocks and pulses. The clock SCK, the horizontal reference pulse HP, the vertical reference pulse VP, the electronic shutter pulse ES, and the up / down inverter signal UDI are generated and supplied by a digital signal processing IC 52 which is a separate chip. The analog video signal AS output from the output amplifier 514 is converted into a digital video signal by the A / D converter 522 after the noise is removed by the CDS circuit 521 that performs noise cancellation for each pixel in the digital signal processing IC 52. The digital signal processing circuit 523 performs signal processing.

A CDS circuit 521, an A / D converter 522,
Also in the digital signal processing circuit 523, the clock C
K and pulses Pa and Pb are required, which can generate a timing signal TG and a synchronizing pulse SG in the digital signal processing IC 52 in a TG / SG generator 514, respectively, and supply them simultaneously with the solid-state imaging device 51.

As described above, the electronic shutter is incorporated in the light receiving section 511, or the solid-state image pickup element 51 of one chip employing a CMOS sensor as the light receiving section is used. Therefore, the electronic shutter pulse ES and the up / down inverter signal UD are provided.
I is required, resulting in an increase in the number of pins. An increase in the number of pins inevitably leads to an increase in power consumption.

FIG. 6 shows another conventional solid-state image pickup device driving device having more functions and multiple functions. In this case, the CDS circuit 515 is taken into the solid-state imaging device 51 from the digital signal processing IC 52. Therefore, the serial / parallel converter 516, the register 51
7, while adding the configuration of the gain control amplifier 518,
Using the chip select CS, the serial clock SK, and the serial data DI, driving and setting of a configuration added by a normal method of setting a 3-wire serial register are performed.

In this case, the CS, SK, and DI pins are newly added because the CDS circuit 515 and the gain control amplifier 518 are newly incorporated in the solid-state imaging device 51. The electronic shutter pulse ES and the up / down inverter signal UDI required in the above can be generated by the serial / parallel converter 516 and the register 517 in the solid-state image sensor 51 in the solid-state image sensor 51. Although the number of pins for ES and UDI can be reduced by this, the number of pins is still seven, one pin more than that of FIG. 5, resulting in an increase in power consumption, which means that the solid-state imaging device is multifunctional and complex. It will fade.

[0015]

In the above-mentioned conventional solid-state image pickup device driving device, if other circuits are incorporated on the same chip as the solid-state image pickup device to achieve multi-functionality, the integrated circuit becomes multi-pin. There are problems in that not only the outer shape of the package is increased and the cost is increased, but also the power consumption is increased.

The present invention provides a driving device for a solid-state imaging device capable of reducing the number of pins as an IC package and reducing power consumption while multiplying and combining the solid-state imaging device.

[0017]

In order to solve the above-mentioned problems, a driving apparatus for a solid-state image pickup device according to the present invention provides a solid-state image pickup device for supplying a minimum clock and pulse required for signal reading operation from the outside. In order to set various parameters on the image sensor, only serial data synchronized with the minimum necessary clock and pulse is simultaneously supplied.

Further, in a solid-state imaging device for supplying a minimum clock and pulse required for signal reading operation from the outside, a group of pulses necessary for receiving serial data by the clock and pulse is formed on the imaging device. It can be generated by a timing signal generator, serial / parallel converted on the image sensor, and stored as various parameters in a register on the image sensor.

According to each of the above-described means, serial data synchronized with a clock and a pulse necessary for signal reading of the solid-state image sensor are supplied to the solid-state image sensor, and the clock and pulse are supplied to the solid-state image sensor based on the clock and the pulse. By performing serial / parallel conversion and updating the register, the multi-functional solid-state imaging device 51 is realized with a small number of pins.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a system diagram for explaining a first embodiment of the present invention. In this embodiment, the number of pins of the package is reduced while incorporating the same functions as the conventional FIG. 6, and the same components as those in FIG. 6 are denoted by the same reference numerals.

That is, 51 is a solid-state image sensor. The solid-state imaging device 51 controls the light receiving unit 511 with various pulses generated by the timing signal generator 5121 to obtain a video signal. Further, the timing signal generator 5121 includes:
Serial / parallel conversion circuit 516 and register 51
The pulse group necessary for updating 7 is generated. Light receiving unit 511
The output of the CDS circuit 515 and the gain control amplifier 5
18, and an output amplifier 102.

TG / SG of digital signal processing IC 52
The serial data DI generated by the generation unit 5241 includes the clock SCK, the horizontal reference pulse HP, and the vertical reference pulse VP necessary for the signal read operation, and the solid-state image sensor 5.
Feed to 1. The timing signal generator 5121 in the solid-state imaging device 51 has a chip select CS and a clock CK.
Are grouped into a clock SCK, a horizontal reference pulse HP,
The pulse group that is generated based on the vertical reference pulse VP and is a serial signal is supplied to a serial / parallel converter 516 that converts a parallel signal. The set values of various parameters that have been serial / parallel converted by the chip select CS, clock CK, and serial data DI are as follows:
Write to register 517. The output of register 517 is
Timing signal generator 5121 and gain control amplifier 5
18 to realize a read operation of a video signal according to a desired setting.

As described above, since the chip select CS and the clock SCK are generated by the timing signal generator 5121 in the solid-state image sensor 51, the chip select CS and the clock SCK from the digital signal processing IC 52 to the solid-state image sensor 51 are generated. Is unnecessary, and as a result, there is no need to provide the solid-state imaging device 51 with pins receiving these supplies. This can reduce the number of pins and power consumption.

FIG. 2 is a timing chart for explaining a second embodiment of the present invention. In this embodiment, the capacity of the register 517 in FIG. 1 is increased, and various settings can be made.

That is, FIG.
An example of the bits is shown, and when the chip select CS is at the H level, the serial clock SK of D12 to D11
The serial data DI of D0 is taken in. In the serial data DI, D11 sets up / down inversion, D10 sets up left / right inversion, D9 to D6 sets the electronic shutter speed, and D5 to D0 set the gain of the gain control amplifier. In the timing chart of FIG.
H typically has hundreds of SCK cycles, so it can handle much more data.

As described above, by extending the period of the chip select CS and increasing the data amount of the serial data DI, it is possible to make the system of FIG. 1 more multifunctional.

FIG. 3 is a system diagram for explaining a third embodiment of the present invention. In this embodiment, the horizontal reference pulse HP among the minimum clocks and pulses necessary for the operation of reading a signal from the solid-state imaging device 51 is used.
And the vertical reference pulse VP are multiplexed and supplied as a composite pulse HVP from the TG / SG generator 5242 of the digital signal processing IC 52 to the timing signal generator 5122 of the solid-state imaging device 51.

In the case of this embodiment, the horizontal reference pulse H
Since P and the vertical reference pulse VP are taken into the solid-state imaging device 51 as a composite signal, the number of pins can be further reduced by one pin as compared with the embodiment of FIG. 1, and the power consumption can be further reduced.

FIG. 4 is a timing chart for explaining a fourth embodiment of the present invention. This embodiment is obtained by adding one dummy bit indicating update / non-update to the head of serial data DI in the configuration of FIG. 1 or FIG.

Only when the dummy bit is at the H ("1") level, assuming that subsequent serial data D7 to D0 are received and the set value of register 517 is updated, serial data D7 to D0 are repeatedly supplied every V. Nothing. In other words, when the signal is at the L (“0”) level, the supply of serial data is not received, and power consumption can be suppressed accordingly.

In this embodiment, the serial data D7
~ D0 is not repeatedly supplied every V,
It is possible to suppress power consumption for transmitting the serial data D7 to D0.

[0032]

As described above, according to the driving apparatus for a solid-state imaging device of the present invention, it is possible to reduce power consumption by reducing the number of pins while achieving multi-function and multi-function on the same chip. Becomes

[Brief description of the drawings]

FIG. 1 is a system diagram for explaining a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a second embodiment of the present invention;

FIG. 3 is a system diagram for explaining a third embodiment of the present invention.

FIG. 4 is a timing chart for explaining a fourth embodiment of the present invention;

FIG. 5 is a system diagram for explaining driving of a conventional solid-state imaging device.

FIG. 6 is a system diagram for explaining driving of another conventional solid-state imaging device.

[Explanation of symbols]

51: solid-state imaging device, 511: light receiving section, 5121, 51
22 timing signal generator, 513 noise canceling circuit, 514 output amplifier, 515 CDS circuit, 5
16: serial / parallel converter, 517: register,
518: gain control amplifier, 52: digital signal processing I
C, 522: A / D converter, 523: Digital signal processing circuit, 5241, 5242: TG / SG generator.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA04 AA10 AB01 BA14 FA06 FA50 5C024 AA01 CA00 FA01 FA11 FA16 HA07 HA15

Claims (6)

[Claims] 1. A solid-state imaging device that externally supplies a minimum clock and pulse required for a signal reading operation, wherein the minimum clock and pulse are used to set various parameters on the image sensor. A driving apparatus for a solid-state image sensor, wherein only serial data synchronized with the above is supplied at the same time. 2. A solid-state imaging device for supplying a minimum necessary clock and pulse for signal readout operation from an external device, wherein a group of pulses necessary for receiving serial data by the clock and pulse is provided on the imaging device. A driving device for a solid-state imaging device, wherein the driving signal is generated by a timing signal generator, serial / parallel converted on the imaging device, and stored as various parameters in a register on the imaging device. 3. The setting value in a register is updated by supplying the serial data to the solid-state imaging device by synchronizing the driving pulse horizontally or vertically, and updating the set value in a register. Driving device for solid-state imaging device. 4. The driving device for a solid-state imaging device according to claim 1, wherein the serial data is a blanking period in a signal reading period of the solid-state imaging device. 5. The method according to claim 1, wherein a dummy code indicating a register update is added to the head of the serial data, and when the dummy code is information not to be updated, a set value in the register is held. 5. The driving device for a solid-state imaging device according to any one of 4. 6. The driving device for a solid-state imaging device according to claim 1, wherein a set value in a register is held when said serial data has a specific value.