JP2000187994A - Latch circuit, shift register circuit, and picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a low voltage interface and low power consumption compatible by reducing burden on a clock signal line as well as power consumption. SOLUTION: When a clock signal ck is 'H', and an input pulse signal in (first control signal) is 'H', (n) type transistors M15, M16 are turned on and an output node /OUT is made a GND level. Then, a (p) type transistor M12 is turned on, an output node OUT is made Vcc (16 V). Then, when first, second control signals and a clock signal ck are in a 'H' level, a latch circuit LAT are operated as a level shifter. Otherwise, they are operated as a level holding circuit. Therefore, a shift register circuit constituted of latch circuits LAT functions as low voltage interface, when the latch circuit LAT is non-active, input of a clock signal ck is stopped, so that burden of a clock signal line and power consumption are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a latch circuit for transmitting a pulse signal, a shift register circuit having the latch circuit, and an image display device using the shift register circuit.

[0002]

2. Description of the Related Art Here, as an example of a shift register circuit having a conventional latch circuit and an image display device, a liquid crystal display device and a shift register circuit constituting a data signal line driving circuit and a scanning signal line driving circuit thereof are described. A description is given below. However, the shift register and the image display device according to the present invention are not limited to the above-described liquid crystal display device and the shift register for the liquid crystal display device, but may be applied to other image display devices and the shift register for the image display device. Applicable.

Conventionally, an active matrix driving type liquid crystal display device has been known as the liquid crystal display device. As shown in FIG. 37, the liquid crystal display device includes a pixel array ARY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD. In the pixel array ARY, a pixel PIX is arranged near each intersection between a number of scanning signal lines GL and a number of data signal lines SL that intersect with each other and is connected to the adjacent scanning signal line GL and data signal line SL. And are arranged in a matrix.

The data signal line driving circuit SD samples the input video signal dat in synchronization with a timing signal such as a clock signal cks, amplifies the video signal dat as necessary, and writes the amplified signal to each data signal line SL. The scanning signal line drive circuit GD is
In synchronization with a timing signal such as a clock signal ckg or the like, the scanning signal lines GL are sequentially selected, and the opening and closing of the switching elements in the pixel PIX are controlled, whereby each data signal line SL is controlled.
The pixel PIX corresponding to the video signal (data) dat written to
And the data written to each pixel PIX is held.

As shown in FIG. 38, the pixel PIX includes a field effect transistor SW as the switching element.
And a pixel capacitance composed of a liquid crystal capacitance CL and an auxiliary capacitance (added as necessary) CS. Then, the data signal line is connected through the drain and the source of the transistor SW.
SL is connected to one electrode of the pixel capacitance, while the gate of the transistor SW is connected to the scanning signal line GL. Further, the other electrode of the pixel capacitor is connected to a common electrode (not shown) common to all pixels. In the above configuration, the transmittance or reflectance of the liquid crystal is modulated by the voltage applied to each liquid crystal capacitor CL, and the pixel is displayed.

Next, the video signal dat is connected to the data signal line SL.
The method of writing to the file will be described. There are a dot-sequential driving method and a line-sequential driving method as a driving method of the data signal line SL. Here, the dot-sequential driving method will be described. FIG. 39 shows a detailed circuit configuration of the data signal line drive circuit SD. The video signal dat input to the video signal line DAT is written to the data signal line SL by opening and closing the sampling circuit AS with output pulses of each stage of the shift register circuit 1 synchronized with the video signal dat.

More specifically, the output signal n of the adjacent latch circuit SR constituting the shift register circuit 1
Are amplified by a buffer circuit composed of a plurality of inverter circuits, an inverted signal is generated as necessary, and the sampling signal s and the inverted signal / s are output to a sampling circuit (analog switch) AS. Then, the sampling circuit AS opens and closes based on the sampling signals s and / s, and supplies the video data from the video signal line DAT to the data signal line SL. FIG. 40 shows clock signals cks and / cks to the latch circuit SR, output signals n1 to n3 of the latch circuit SR, and sampling signals s1 and s2 in that case.

FIG. 41 shows a detailed circuit configuration of the scanning signal line driving circuit GD. In this scanning signal line driving circuit GD,
Adjacent latch circuit SR constituting shift register circuit 2
The output signal n is taken by a NAND circuit,
Further, a desired pulse width is obtained by overlapping with an external pulse width control signal gps. In that case, the clock signals ckg, / ckg to the latch circuit SR, the output signals n1 to n3 of the latch circuit SR, the pulse width control signal gps,
FIG. 42 shows the scanning signals gl1 and gl2 to the scanning signal line GL.

Here, in the data signal line driving circuit SD and the scanning signal line driving circuit GD, each latch circuit SR constituting the shift register circuits 1 and 2 has a configuration as shown in FIG. FIG. 43 shows an example of a latch circuit SR for configuring the shift register circuits 1 and 2 that can scan in only one direction. Here, a specific configuration example of the clocked inverter circuit 3 used in the latch circuit SR is shown in FIG. On the other hand, when configuring a shift register circuit capable of bidirectional scanning, a latch circuit SR having a configuration as shown in FIG. 45 is used. These latch circuits
SR is a half-latch circuit, which latches an input signal at one of the rising and falling edges of the clocks ck and / ck, and outputs an output signal n having a pulse width of one cycle of the clocks ck and / ck.

In recent years, in order to reduce the size, increase the resolution, and reduce the mounting cost of a liquid crystal display device, a pixel array ARY for controlling display and signal line drive circuits SD and GD are integrally formed on the same substrate. Technology is attracting attention. In such a liquid crystal display device integrated with a drive circuit, a transparent substrate needs to be used as a substrate when a transmission type liquid crystal display device that is widely used at present is configured. In such a case, a polycrystalline silicon thin film transistor that can be formed on a quartz substrate or a glass substrate is often used as an active element such as the transistor SW of the pixel PIX or the transistor forming the clocked inverter circuit 3.

[0011]

However, the above-mentioned conventional liquid crystal display device has the following problems.
That is, as shown in FIG. 39, the data signal line drive circuit SD obtains the sampling signals s and / s based on a continuous signal of the output signals n of the two adjacent latch circuits SR. Therefore, as shown in FIG. 40, the timing of the falling edge of the sampling signal s1 corresponding to the data signal line SL1 and the timing of the rising edge of the sampling signal s2 corresponding to the next-stage data signal line SL2 substantially coincide with each other. is there.

Therefore, for example, the waveforms of the sampling signals s and / s become dull due to changes in the characteristics of the transistors constituting the data signal line drive circuit SD, or the output signals n from the two adjacent latch circuits SR are changed. If the timing slightly shifts, the sampling signals s1 and s2 corresponding to the adjacent data signal lines SL1 and SL2 may overlap. In that case, the data signal line SL
, Noise may be superimposed on the displayed image, and a defect such as bleeding, ghost, crosstalk, or the like may occur in the displayed image.

In the above-mentioned conventional liquid crystal display device, the clock signals cks, ckg and the start signals sps, spg input to the shift register circuits 1, 2 are the same as the clock signals cks, spg shown in FIGS. Like ckg, it is directly input from the outside as a signal having the same amplitude as the power supply voltage of the drive circuits SD and GD. On the other hand, a liquid crystal display device integrated with a driving circuit using the polycrystalline silicon thin film transistor has inferior transistor characteristics as compared with a single crystal silicon transistor, and particularly has an absolute value of a threshold voltage as high as 1V to 6V. Therefore, the driving power supply voltage is also 15
It has to be high up to 20V. Therefore, in the case of the liquid crystal display device integrated with the driving circuit, it is necessary to increase the amplitude of the clock signals cks, ckg and the start signals sps, spg, etc., which are directly input from the outside.

However, when the amplitude of the clock signal cks, ckg or the like is increased, there is a problem that power consumption in an external circuit such as a control circuit (not shown) for generating a clock signal or the like is increased. Unnecessary radiation due to signal lines also poses a major problem.

In order to solve the problem caused by increasing the amplitude of the clock signals cks, ckg and the like as described above,
It has been proposed to mount a level shifter circuit (signal booster circuit) on the signal line drive circuits SD and GD side of the liquid crystal display device to reduce the voltage of the input / output interface.

FIG. 46 shows a data signal line drive circuit SD equipped with the above-mentioned level shifter circuit. In the data signal line drive circuit SD shown in FIG. 46, a level shifter circuit LS is arranged immediately before the shift register circuit 5. And the amplitude of the input clock signal cks and the start signal sps
(5V) is boosted to 15V and supplied to the shift register circuit 5. Thus, an operating voltage of 15 V is obtained with an input signal of 5 V
You get However, when a polycrystalline silicon thin film transistor is used in this configuration, the duty ratio of the boosted signal greatly changes due to variations in its characteristics, and the timing and width of the output pulse n of the data signal line drive circuit SD vary. , Noise may be superimposed on the data signal line SL to cause a deterioration in image quality. Further, since the level shifter circuit LS itself has a low driving ability, a buffer is required to drive the subsequent signal lines, and there is a problem that power consumption increases.

FIG. 47 shows a scanning signal line drive circuit GD equipped with the above-mentioned level shifter circuit. In the scanning signal line driving circuit GD shown in FIG. 47, a level shifter circuit LS is arranged immediately before the shift register circuit 6 and on the pulse width control signal line GPS. Then, the amplitude (5 V) of the input clock signal ckg, start signal spg, and pulse width control signal gps is boosted to 15 V and supplied to the shift register circuit 6 or the NOR circuit. Also in this case, the level shifter circuit
As with the data signal line drive circuit SD equipped with LS,
There is a problem that the image quality may be reduced and power consumption may be increased.

FIG. 48 and FIG. 49 are specific circuit configuration diagrams of the level shifter circuit LS. In the figure, M1, M2
Is a p-type transistor, and M3 to M6 are n-type transistors. FIG. 50 shows waveforms of input signals in and / in and output signals out and / out with respect to the level shifter circuit LS shown in FIG. 48 or FIG.

As a method for avoiding the above-mentioned problems of a decrease in image quality and an increase in power consumption, there is a method in which each of the shift register circuits constituting each of the signal line driving circuits SD and GD has a boosting function. According to this method, since the latch circuits at each stage of the shift register circuit have a boosting function, a signal line driving buffer for driving signal lines between the individual latch circuits is not required. In addition, since the output of each latch circuit is directly boosted instead of a control signal such as a clock signal or a start signal input to each latch circuit, sampling signals s, / s, etc., which are stable with respect to variations in transistor characteristics, are provided. Can be obtained.

However, the level shifter circuit LS has the configuration shown in FIG.
8 and the structure shown in FIG.
A high driving force is required for a transistor that inputs n and / in. Therefore, the gate area of the transistor is increased, which causes another problem of an increase in load on the clock signal line and an increase in power consumption.

It is an object of the present invention to reduce the load on a clock signal line and reduce power consumption by incorporating a boosting function in a latch circuit, and to achieve a shift register that achieves both low voltage interface and low power consumption. It is an object of the present invention to provide a circuit and an image display device having low power consumption and high display quality using the shift register circuit.

[0022]

According to a first aspect of the present invention, there is provided a latch circuit for receiving a pulse signal and a clock signal and transmitting the pulse signal in synchronization with the clock signal. The amplitude of the clock signal or the pulse signal is smaller than the amplitude of the pulse signal output from the latch circuit.

According to the above configuration, when it is necessary to increase the output amplitude of the latch circuit or the shift register circuit using a plurality of latch circuits, or when the driving voltage is not increased to a certain degree or more, the latch circuit and the shift register circuit operate normally. Even when the clock signal does not operate, the amplitude of the clock signal can be reduced, so that the load on the external circuit that generates the clock signal is reduced and the power consumption can be reduced.

According to a second aspect of the present invention, in the latch circuit according to the first aspect, a first circuit having a voltage holding function and a second circuit having a level shift function are further provided. The second circuit is characterized in that some elements are shared with each other.

According to the above configuration, since the number of elements is small and the circuit size is further reduced, power consumption can be reduced, the operating frequency can be improved, and manufacturing costs can be reduced.

According to a third aspect of the present invention, in the latch circuit according to the second aspect, a power supply potential is supplied to the latch circuit, and the voltage holding is provided between the power supply potential and the second circuit. An element for controlling a function or a level shift function of an input signal is provided.

According to the above configuration, the circuit operation can be controlled by controlling the power supply to the second circuit by the element, so that the circuit configuration for control becomes extremely simple and the operation is improved. It is possible to suppress power consumption in a circuit that is not used.

According to a fourth aspect of the present invention, in the latch circuit according to the first aspect, each of the source electrodes is connected to the power supply potential while each of the gate electrodes is connected to the respective drain electrodes. The first p-type transistor and the second p-type transistor, and the source electrode
a first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor, and a source electrode connected to the second p-type transistor. A second n-type transistor having a drain electrode connected to the ground potential, a gate electrode connected to the drain electrode of the first p-type transistor, and a source electrode connected to the first p-type transistor. A third n-type transistor connected to the drain electrode of the transistor and having the gate signal input with the pulse signal, a source electrode connected to the drain electrode of the third n-type transistor, and a drain electrode connected to the ground potential 4n-th type that is connected and receives the clock signal to the gate electrode A transistor, a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, and a gate electrode to which an inverted signal of the pulse signal is input, and a source electrode connected to the drain electrode of the fifth n-type transistor. A sixth n-type transistor whose drain electrode is connected to the ground potential and whose gate electrode receives the clock signal, wherein the pulse signal is output from the drain electrode of the second p-type transistor. The inverted signal of the pulse signal is output from the drain electrode of the first p-type transistor.

According to the above configuration, even in the latch circuit having such a configuration, when the clock signal is in the active state, it functions as a normal level shifter circuit having a function of boosting and outputting the input signal. When is in the inactive state, it functions as a holding circuit that maintains the internal state. Therefore, since this latch circuit operates as a latch circuit having a level shift function,
When a shift register circuit is formed by combining these, the amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, that is, the power supply voltage of the shift register circuit.

Further, since the inverted signal of the clock signal is not input to this latch circuit, the circuit scale is reduced. In addition, since the load on the clock signal line is reduced, the load on the external circuit can be reduced.

Also in this latch circuit, current does not always flow when the level of the clock signal is switched, but flows only when the output signal is inverted.
There is a merit that power consumption hardly increases.

Further, since the number of transistors constituting the latch circuit is only eight, the level shift function and the latch function can be made compatible with an extremely small number of elements.

In addition, the latch circuit operates at a timing corresponding to one stage of the logic gate at any timing during operation, so that it can be operated at extremely high speed.

According to a fifth aspect of the present invention, in the latch circuit of the first aspect, each of the source electrodes is connected to the power supply potential while each of the gate electrodes is connected to the respective drain electrodes. The first p-type transistor and the second p-type transistor, and the source electrode
a first n-type transistor connected to the drain electrode of the p-type transistor, a gate electrode connected to the drain electrode of the second p-type transistor, and a source electrode connected to the first n-type transistor
A seventh n-type transistor having a drain electrode connected to the drain electrode, a drain electrode connected to the ground potential, and a gate electrode receiving an inverted signal of the clock signal, and a source electrode connected to the drain of the second p-type transistor. A second n-type transistor connected to an electrode and a gate electrode connected to the drain electrode of the first p-type transistor; a source electrode connected to the drain electrode of the second n-type transistor; and a drain electrode connected to the ground potential. In addition, an eighth n-type transistor having a gate electrode to which an inverted signal of the clock signal is input, a source electrode connected to a drain electrode of the first p-type transistor, and a pulse signal being input to a gate electrode. A 3n-type transistor, wherein the source electrode is a drain of the third n-type transistor; While connected to the electrode, and the 4n-type transistor having a drain electrode is connected to the ground potential, the clock signal is inputted to the gate electrode,
A fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a gate electrode receiving an inverted signal of the pulse signal, and a source electrode connected to the drain electrode of the fifth n-type transistor. On the other hand, the drain electrode is connected to the ground potential, and the clock signal is input to the gate electrode.
An n-type transistor is provided, wherein the pulse signal is output from a drain electrode of the second p-type transistor, and an inverted signal of the pulse signal is output from a drain electrode of the first p-type transistor.

According to the above configuration, when the clock signal is in the active state, it functions as a normal level shifter circuit having the function of boosting and outputting the input signal.
When the clock signal is in the inactive state, it functions as a holding circuit that maintains the internal state. Therefore, since this latch circuit operates as a latch circuit having a level shift function, when a shift register circuit is configured by combining these, the amplitude of the clock signal is changed to the amplitude of the pulse signal to be scanned. That is, the power supply voltage can be made lower than the power supply voltage of the shift register circuit.

A clock signal and its inverted signal are input to this latch circuit. When the latch circuit operates as a level shifter circuit, the signal path of the holding circuit is completely cut off. Is completely shut off, so that stable operation is guaranteed. That is, the operation margin is increased, and it is possible to cope with a reduction in the voltage of the input signal and an increase in the operation speed.

Also, in this latch circuit, current does not always flow when the level of the clock signal changes, but flows only when the output signal is inverted.
There is a merit that power consumption hardly increases.

Further, since the number of transistors constituting the latch circuit is only 10, the level shift function and the latch function can be compatible with an extremely small number of elements.

Also, in this latch circuit, there is only one current path at any timing during operation, and the internal delay operates with a delay corresponding to one stage of the logic gate. Can work.

According to a sixth aspect of the present invention, in the latch circuit according to the first aspect, each of the source electrodes is connected to the power supply potential while each of the gate electrodes is connected to the respective drain electrodes. The first p-type transistor and the second p-type transistor, and the source electrode
a first n-type transistor having a gate electrode connected to the drain electrode of the p-type transistor, a gate electrode connected to the drain electrode of the second p-type transistor, and a source electrode connected to the second p-type transistor;
A second n-type transistor having a gate electrode connected to the drain electrode of the first p-type transistor; a source electrode connected to the drain electrode of the first p-type transistor; A third n-type transistor to which the pulse signal is input, a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, and a gate electrode to which an inverted signal of the pulse signal is input;
A ninth n-type transistor having a source electrode connected to the drain electrodes of the third and fifth n-type transistors, a drain electrode connected to the ground potential, and a gate electrode to which the clock signal is input; Is connected to the drain electrodes of the first and second n-type transistors, while the drain electrode is connected to the ground potential, and the gate electrode receives an inverted signal of the clock signal. The pulse signal is output from the drain electrode of the second p-type transistor, and an inverted signal of the pulse signal is output from the drain electrode of the first p-type transistor.

According to the above configuration, in the latch circuit, in addition to the above-described effects, the number of transistors to be configured is eight.
Since the number of the shift registers is smaller than that of the fifth aspect, a shift register circuit having an extremely small circuit scale can be formed.

Further, since the number of inputs of the clock signal and its inverted signal is reduced by half, there is an advantage that the capacity of the clock signal line is reduced and the load on the external circuit can be reduced.

According to a seventh aspect of the present invention, in the latch circuit according to the first aspect, each of the source electrodes is connected to the power supply potential while each of the gate electrodes is connected to the respective drain electrodes. The first p-type transistor and the second p-type transistor, and the source electrode
a first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor, and a source electrode connected to the second p-type transistor. A second n-type transistor having a drain electrode connected to the ground potential, a gate electrode connected to the drain electrode of the first p-type transistor, and a source electrode connected to the first p-type transistor. A third n-type transistor connected to the drain electrode of the transistor and having the gate signal input with the pulse signal; a source electrode connected to the drain electrode of the second p-type transistor; The fifth n-type transistor to which the inverted signal is input and the source electrode are connected to the third n-type transistor. While connected to the drain electrode of the preliminary second 5n-type transistor, with a drain electrode connected to the ground potential, and a second 9n-type transistor in which the clock signal is inputted to the gate electrode, the second
The pulse signal is output from a drain electrode of a p-type transistor, and an inverted signal of the pulse signal is output from a drain electrode of the first p-type transistor.

In the latch circuit having the above configuration, in addition to the above-described functions and effects, the number of transistors to be configured is seven,
Since it is smaller than the configuration of the sixth aspect of the present invention, a shift register circuit having an extremely small circuit scale can be configured.

Further, since the number of inputs of the clock signal and its inverted signal is reduced by half, there is an advantage that the capacity of the clock signal line is reduced and the load on the external circuit can be reduced.

According to an eighth aspect of the present invention, in the latch circuit according to the first aspect, the latch circuit includes first and second logical product-negative OR circuits, and the first logical product-negation circuit is provided. The inputs of the AND circuit of the OR circuit are the clock signal and the pulse signal, and the inputs of the NOR circuit of the first AND-NOR circuit are the outputs of the AND circuit. Signal and the output signal of the second AND-NOR circuit. The input of the AND circuit part of the second AND-NOR circuit is an inverted signal of the clock signal and the pulse signal. The input of the NOR circuit of the second AND-NOR circuit is the output signal of the AND circuit and the output signal of the first AND-NOR circuit. Features.

In the above configuration, the input signal is taken in only when the clock signal is in the active state, and the internal state is held when the clock signal is in the inactive state. Therefore, since this latch circuit operates as a latch circuit having a level shift function, when a shift register circuit is formed by combining these, the amplitude of the clock signal is changed to the amplitude of the pulse signal to be scanned, that is, the shift It is possible to make the voltage lower than the power supply voltage of the register circuit.

Further, since the logical product-negative logical sum can be configured as one logical gate, the circuit scale can be reduced.

According to a ninth aspect of the present invention, in the latch circuit according to the eighth aspect, the logical product-negative OR circuit comprises:
A first p-type transistor and a second p-type transistor whose respective gate electrodes are connected to the respective drain electrodes while respective source electrodes are connected to the power supply potential, and the source electrodes are connected to the drain electrodes of the first p-type transistors. On the other hand, a drain electrode is connected to the ground potential, a gate electrode receives the output signal of the other AND-NOR circuit, a first n-type transistor, and a source electrode corresponds to the second p-type transistor. An eleventh n-type transistor connected to a drain electrode and having a gate electrode to which an inverted signal of the clock signal is input; a source electrode connected to a drain electrode of the first p-type transistor; and the pulse signal input to a gate electrode And the source electrode is connected to the drain electrode of the third n-type transistor. On the other hand, a fourth n-type transistor having a drain electrode connected to the ground potential and the clock signal input to the gate electrode, a source electrode connected to the drain electrode of the second p-type transistor, and a gate A fifth n-type transistor whose electrode receives an inverted signal of the pulse signal, a source electrode connected to the drain electrodes of the eleventh and fifth n-type transistors, and a drain electrode connected to the ground potential; A twelfth n-type transistor to which a gate electrode is supplied with an inverted signal of the output signal of the other AND-NOR circuit, wherein the pulse signal is output from a drain electrode of the first p-type transistor; 2p
An inverted signal of the pulse signal is output from a drain electrode of the type transistor.

In the above configuration, when such an AND-NOR circuit is applied to, for example, a logic circuit having a shift register function (AND-NOR circuit), the input signal becomes the power supply voltage. When the shift register circuit is configured by combining these, the amplitude of the clock signal is smaller than the amplitude of the pulse signal to be scanned, that is, the power supply voltage of the shift register circuit. It is possible to do.

In addition, in the AND-NOR circuit, since the current flows only when the output signal is inverted without depending on the switching of the level of the input signal, there is an advantage that the power consumption is hardly increased. .

According to a tenth aspect of the present invention, in the latch circuit according to the first aspect, the latch circuit includes a first NAND circuit to which the clock signal and the pulse signal are inputted, A second NAND circuit to which an inverted signal of the pulse signal is input, and a third NAND circuit to which an output signal of the first AND circuit and an output signal of the fourth AND circuit are input And a fourth NAND circuit to which an output signal of the second NAND circuit and an output signal of the third NAND circuit are input.

In the above configuration, the input signal is taken into the NAND circuit only when the clock signal is in the active state, and not taken when the clock signal is in the inactive state, and the internal state is maintained. Therefore, since this latch circuit operates as a latch circuit having a level shift function, when a shift register circuit is formed by combining these, the amplitude of the clock signal is changed to the amplitude of the pulse signal to be scanned, that is, the shift It is possible to make the voltage lower than the power supply voltage of the register circuit.

According to an eleventh aspect of the present invention, in the latch circuit according to the tenth aspect, the first and second NAND circuits each have a source electrode connected to a power supply potential and a gate connected to a source gate. A first p-type transistor and a second p-type transistor whose electrodes are connected to each other's drain electrode, and a 3nth source whose source electrode is connected to the drain electrode of the first p-type transistor and whose gate electrode receives the pulse signal. A transistor and a source electrode connected to the drain electrode of the third n-type transistor, while a drain electrode is connected to the ground potential,
A fourth n-type transistor whose gate electrode receives the clock signal; a source electrode connected to the drain electrode of the second p-type transistor; a drain electrode connected to the ground potential; A 13th n-type transistor to which an inverted signal of the signal is input, a source electrode is connected to a drain electrode of the second p-type transistor, a drain electrode is connected to the ground potential, and a gate electrode is connected to the gate electrode. A 14th n-type transistor to which an inverted signal is input,
From the drain electrode of the first p-type transistor to the first
And the inverted signal of the output signal is output from the drain electrode of the second p-type transistor.

In the above configuration, such a NAND circuit is replaced with, for example, a logic circuit having a level shift function.
When applied to (NAND logic circuit), it operates normally even when the input signal is smaller than the power supply voltage.Therefore, when a shift register circuit is configured by combining this with a normal NAND logic circuit The amplitude of the clock signal can be made smaller than the amplitude of the pulse signal to be scanned, that is, the power supply voltage of the shift register circuit.

According to a twelfth aspect of the present invention, in the latch circuit according to the first aspect, the latch circuit includes first and second p-type transistors whose source electrodes are connected to a power supply potential, a transistor, and a source electrode. Third and fourth p-type transistors each having a gate electrode connected to a clock signal and a source electrode connected to the drain electrodes of the first and second p-type transistors, respectively, and a source electrode having the third and fourth p-type transistors Third and fifth n-type transistors each having a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal, and a source electrode connected to the drain electrode of the transistor; Fourth and sixth n-type transistors connected to the drain electrode of the transistor, the gate electrode is connected to the clock signal, and the drain electrode is connected to the ground potential. And Njisuta, the source electrode of the third
And a drain electrode of the fourth p-type transistor, a gate electrode connected to the drain electrode of the fourth and third p-type transistors, and a drain electrode connected to the ground potential. An output pulse is output from the drain electrode of the fourth p-type transistor, and an inverted signal of the output pulse is output from the drain electrode of the third p-type transistor. I do.

According to the above configuration, since the third and fourth p-type transistors for inputting the clock signal to the gate electrode are added, the output node for outputting the output pulse or its inverted signal is at low level. At the time of the operation at (ground potential), the p-type transistor works to limit the current from the power supply potential side, and the operation margin is expanded.

According to a thirteenth aspect of the present invention, in the latch circuit according to the first aspect, the latch circuit includes first and second p-type transistors whose source electrodes are connected to a power supply potential, a transistor, and a source electrode. Third and fourth p-type transistors each having a gate electrode connected to a clock signal and a source electrode connected to the drain electrodes of the first and second p-type transistors, respectively, and a source electrode having the third and fourth p-type transistors Third and fifth n-type transistors each having a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal, and a source electrode connected to the drain electrode of the transistor; Fourth and sixth n-type transistors connected to the drain electrode of the transistor, the gate electrode is connected to the clock signal, and the drain electrode is connected to the ground potential. And Njisuta, the source electrode of the third
And the first and second p-type transistors connected to the drain electrodes of the fourth and third p-type transistors, respectively, and the gate electrode is connected to the drain electrodes of the fourth and third p-type transistors, respectively.
And the source electrode is connected to the drain electrodes of the first and second n-type transistors, respectively.
Seventh and eighth n-type transistors each having a gate electrode connected to the inverted signal of the clock signal and a drain electrode connected to the ground potential, wherein an output pulse is output from the drain electrode of the fourth p-type transistor. The inverted pulse of the output pulse is output from the drain electrode of the third p-type transistor.

According to the above structure, since the third and fourth p-type transistors for inputting the clock signal to the gate electrode are added, the output node for outputting the output pulse or its inverted signal is at low level. At the time of the operation at (ground potential), the p-type transistor works to limit the current from the power supply potential side, and the operation margin is expanded.

According to a fourteenth aspect, in the latch circuit according to the first aspect, the latch circuit includes first and second p-type transistors each having a source electrode connected to a power supply potential, a transistor, and a source electrode. Third and fourth p-type transistors, each having a gate electrode connected to a clock signal, and a source electrode connected to the drain electrodes of the first and second p-type transistors, respectively, and a source electrode having the first and second p-type transistors. A fifth electrode connected to the drain electrode of the transistor, a gate electrode connected to the input pulse signal and an inverted signal of the input pulse signal, and a drain electrode connected to the drain electrode of the third and fourth p-type transistors, respectively. And the sixth p-type transistor, and the source electrode is connected to the drain electrode of the third and fourth p-type transistors, respectively, and the gate electrode is Third and fifth n-type transistors respectively connected to the force pulse signal and the inverted signal of the input pulse signal, a source electrode connected to the drain electrode of the third and fifth n-type transistors, and a gate electrode connected to the third and fifth n-type transistors. Fourth and sixth n-type transistors connected to a clock signal and having a drain electrode connected to the ground potential; source electrodes connected to the drain electrodes of the third and fourth p-type transistors; and a gate electrode connected to the third and fourth p-type transistors. First and second n-type transistors connected to the drain electrodes of the fourth and third p-type transistors, respectively, and having the drain electrodes connected to the ground potential; An output pulse is output from the electrode, and an inverted signal of the output pulse is output from the drain electrode of the third p-type transistor. To.

According to the above configuration, the third and fourth p-type transistors whose clock signals are input to the gate electrode, and the fifth and sixth p-type transistors whose input pulse signal and its inverted signal are input to the gate electrode are provided. The p-type transistor limits the current from the power supply potential side when the output node from which the output pulse or its inverted signal is output goes low (ground potential) because of the addition of the p-type transistor. Work, the operating margin is expanded.

According to a fifteenth aspect of the present invention, in the latch circuit according to the first aspect, the latch circuit includes first and second p-type transistors whose source electrodes are connected to a power supply potential, a transistor, and a source electrode. Third and fourth p-type transistors, each having a gate electrode connected to a clock signal, and a source electrode connected to the drain electrodes of the first and second p-type transistors, respectively, and a source electrode having the first and second p-type transistors. A fifth electrode connected to the drain electrode of the transistor, a gate electrode connected to the input pulse signal and an inverted signal of the input pulse signal, and a drain electrode connected to the drain electrode of the third and fourth p-type transistors, respectively. And the sixth p-type transistor, and the source electrode is connected to the drain electrode of the third and fourth p-type transistors, respectively, and the gate electrode is Third and fifth n-type transistors respectively connected to the force pulse signal and the inverted signal of the input pulse signal, a source electrode connected to the drain electrode of the third and fifth n-type transistors, and a gate electrode connected to the third and fifth n-type transistors. Fourth and sixth n-type transistors connected to a clock signal and having a drain electrode connected to the ground potential; source electrodes connected to the drain electrodes of the third and fourth p-type transistors; and a gate electrode connected to the third and fourth p-type transistors. First and second n-type transistors respectively connected to the drain electrodes of the fourth and third p-type transistors, and source electrodes connected to the drain electrodes of the first and second n-type transistors, respectively; A seventh electrode having a gate electrode connected to the inverted signal of the clock signal and a drain electrode connected to the ground potential;
And an eighth n-type transistor, wherein an output pulse is output from the drain electrode of the fourth p-type transistor, and an inverted signal of the output pulse is output from the drain electrode of the third p-type transistor. It is characterized by.

According to the above configuration, the third and fourth p-type transistors having the gate electrode supplied with the clock signal, and the fifth and sixth p-type transistors having the gate electrode supplied with the input pulse signal and its inverted signal. The p-type transistor limits the current from the power supply potential side when the output node from which the output pulse or its inverted signal is output goes low (ground potential) because of the addition of the p-type transistor. Work, the operating margin is expanded.

According to a sixteenth aspect of the present invention, in the latch circuit according to the ninth aspect, the first, second, third, and fifth n-type transistors have a dual gate structure, and the fourth, sixth, seventh, and fourth transistors have the same structure.
The 8n-type transistor has a single-gate structure.

In the above configuration, when a transistor is directly connected between the output terminal of the latch circuit and the ground terminal, the transistor on the ground potential side has a single gate structure and the transistor on the output terminal side has a dual gate structure. At this time, it is possible to achieve both reduction of the number of elements and securing of the withstand voltage of the elements. Generally, in a plurality of transistors connected in series, a drain side (a high potential side for an n-channel transistor, a high potential side for an n-channel transistor, Since a stronger voltage is applied to the lower side (in the case of the type transistor), it is effective to make the drain side transistor a dual gate configuration and increase the element breakdown voltage. Also, since only a relatively small voltage is applied to the source side, the load can be reduced by employing a single gate configuration, and high-speed operation of the shift register circuit and reduction in the number of elements can be realized. Become.

According to a seventeenth aspect, in the latch circuit according to the ninth aspect, the channel length of the first, second, third, and fifth n-type transistors is larger than the channel length of the fourth, sixth, seventh, and eighth n-type transistors. It is characterized in that the channel length is longer.

In the latch circuit having the above configuration, when a plurality of transistors are directly connected between the output terminal and the ground terminal of the latch circuit as described above, the transistor on the output terminal side is more than the channel length of the transistor on the ground potential side. By increasing the channel length, it is possible to achieve both reduction in the number of elements and securing of the withstand voltage of the elements. As described above, in the plurality of transistors connected in series, the drain side (the high potential side in the n-channel transistor) is higher than the source side (the lower potential side in the n-channel transistor and the higher potential side in the p-channel transistor). , P
Since a stronger voltage is applied to the lower potential side of a channel transistor, it is effective to increase the channel length of the transistor on the drain side and increase the withstand voltage of the element. Further, since only a relatively small voltage is applied to the source side, the load can be reduced by shortening the channel length, and high-speed operation of the shift register circuit can be achieved.
It is possible to reduce the number of elements.

According to an eighteenth aspect of the present invention, in a shift register circuit having a plurality of latch circuits for transmitting a pulse signal in synchronization with a clock signal, inputting and stopping of a clock signal supplied to each of the latch circuits is performed. It has a clock signal input control unit for controlling, and the amplitude of the clock signal is smaller than the amplitude of the pulse signal.

According to the above configuration, the amplitude of the clock signal is smaller than the amplitude of the pulse signal, that is, smaller than the power supply voltage for transmitting the pulse signal. Therefore, the pulse signal having a large amplitude can be transmitted without increasing power consumption by an external circuit that generates the clock signal. In that case, the input of the clock signal supplied to each of the latch circuits constituted by active elements required to have a high driving force is stopped by the clock signal input control unit when the latch circuit is inactive,
The load on the clock signal line and the power consumption are reduced.

According to a nineteenth aspect of the present invention, in the shift register circuit according to the eighteenth aspect, the clock signal inputted to each of the latch circuits is only one of a clock signal having a predetermined cycle or a signal having an inverted phase thereof. There is a feature.

According to the above configuration, the latch circuit operates in synchronization with only one of the certain clock signal and the opposite phase signal. Therefore, the load on the clock signal line is reduced by half and power consumption is reduced as compared with the case where both the clock signal ck and the inverted clock signal / ck are used as in the conventional latch circuit SR shown in FIG. Can be

According to a twentieth aspect of the present invention, in the shift register circuit according to the eighteenth aspect, the output signal of each of the latch circuits is input to the subsequent latch circuit via the first transfer gate, and 2 is input to the preceding latch circuit via the second transfer gate,
Alternatively, the scanning direction is controlled by selectively conducting the second transfer gate by an external signal.

According to the shift register circuit having the above configuration,
Each output signal of the latch circuit is input to the preceding and subsequent latch circuits via the first and second transfer gates, respectively, and one of the first and second transfer gates is turned on by an external signal. Thus, the scanning direction of the shift register is controlled.

In the shift register circuit having such a configuration, the propagation direction of the pulse signal can be set in any direction by the input signal to the transfer gate. Can be configured.

According to a twenty-first aspect of the present invention, in the shift register circuit of the eighteenth aspect, the output signal of each of the latch circuits is input to a subsequent latch circuit via a buffer circuit. .

In the shift register circuit having the above configuration,
For example, if the configuration is such that the latch circuit output pulse signal is input to the next-stage latch circuit via the buffer circuit,
Even in a latch circuit with a level shift function having a relatively small driving force, by adding a buffer circuit,
Since the driving force for the next stage can be increased, the stable operation and high-speed operation of the shift register circuit can be achieved.

According to a twenty-second aspect of the present invention, in the shift register circuit according to the eighteenth aspect, the clock signal input control section comprises a first clock signal input control section and a second clock signal input control section. The latch circuit includes a first p-type transistor and a second p-type transistor each of which has a source electrode connected to a power supply potential and a gate electrode connected to a drain electrode of the other, and a source electrode of the first p-type transistor. A first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor; and a source electrode connected to the drain of the second p-type transistor. While the drain electrode is connected to the ground potential and the gate electrode is connected to the first p-type electrode. A second n-type transistor connected to the drain electrode of the transistor, a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, and a gate electrode connected to the pulse signal input node; Is connected to the drain electrode of the third n-type transistor, the drain electrode is connected to the ground potential, and the gate electrode is connected to the first clock signal input control unit. Are connected to the drain electrode of the second p-type transistor, the fifth n-type transistor has a gate electrode connected to the inverted pulse signal input node, and the source electrode is connected to the drain electrode of the fifth n-type transistor. The drain electrode is connected to the ground potential and the gate electrode is A second n-type transistor connected to a two-clock signal input control unit, wherein the drain electrode of the second p-type transistor is a pulse signal output node, and the drain electrode of the first p-type transistor is an inverted pulse signal output node; It is characterized by doing.

According to the above configuration, when the clock signal input from the first clock signal input control unit becomes active, the fourth n-type transistor is turned on, and when the level of the input pulse signal becomes "H", the third n-type transistor is turned on. Is turned on, and the inverted pulse signal output node becomes the ground potential. Then, the second p-type transistor is turned on, and the pulse signal output node becomes the power supply potential later than the fall of the output signal of the inverted pulse signal output node. Therefore, the first p-type transistor is turned off, and the potential of the inverted pulse signal output node is determined to the ground potential. Further, since the input inverted pulse signal is "L", the fifth n-type transistor is turned off, and since the inverted pulse signal output node is at the ground potential, the second n-type transistor is turned off. Thus, the potential of the pulse signal output node is determined as the power supply potential. That is,
When the level of the input pulse signal and the output pulse signal is “H” and the clock signal is active, the latch circuit outputs a pulse signal having the amplitude of the power supply voltage even if the amplitude of the clock signal is small. While operating as a level shifter circuit, the others operate as level holding circuits. Therefore, according to the shift register circuit configured by connecting the plurality of latch circuits, a pulse signal having a larger amplitude is transmitted in synchronization with a clock signal having a small amplitude.

Further, the latch circuit requires the clock signal only when the latch circuit is in an active state. Therefore, when the latch circuit is in an inactive state, the input of the clock signal is stopped by the first and second clock signal input control units, thereby reducing the load on the clock signal line and the power consumption. It is.

Further, the pulse signal from the pulse signal output node rises after the fall of the pulse signal from the inverted pulse signal output node. Therefore, the pulse width of the output pulse signal of the pulse signal output node is always smaller than the pulse width of the output pulse signal of the inverted pulse signal output node, and the output pulse signal of the pulse signal output node in each latch circuit , There is no temporal overlap in output signals from adjacent latch circuits.

According to a twenty-third aspect of the present invention, in the shift register circuit according to the twenty-second aspect, the latch circuit comprises:
A first inverter having an input terminal connected to the inverted pulse signal output node; and a second inverter having an input terminal connected to the pulse signal output node, and having the output terminal of the first inverter output a new pulse signal. The output terminal of the second inverter may be a new inverted pulse signal output node while the node is a node.

According to the above configuration, the pulse signal from the inverted pulse signal output node falls with a delay from the rise of the pulse signal from the pulse signal output node.
Therefore, the pulse width of the output pulse signal of the inverted pulse signal output node is always smaller than the pulse width of the output pulse signal of the pulse signal output node, and the output pulse of the inverted pulse signal output node in each latch circuit is By using signals, there is no temporal overlap in output signals from adjacent latch circuits.

Further, the dullness of the output pulse signal and the output inversion pulse signal due to the operation delay of the transistor constituting the latch circuit is corrected by the buffer function (amplifying function) of the inverter. In particular, in the present shift register circuit including a multi-stage latch circuit, since the signal is corrected immediately before or immediately before the latch circuit of each stage, the superposition of the signal delay of each latch circuit is prevented. Therefore, stable operation is possible even in a series of multi-stage latch circuits.

According to a twenty-fourth aspect of the present invention, in the shift register circuit according to the twenty-second aspect, the first clock signal input control section includes a gate electrode of the fourth n-type transistor when the latch circuit becomes inactive. Switching means for electrically disconnecting from the clock signal input node; and potential fixing means for fixing the potential of the gate electrode of the fourth n-type transistor electrically disconnected from the clock signal input node to a predetermined potential. On the other hand, the second clock signal input control unit comprises: switching means for electrically disconnecting the gate electrode of the sixth n-type transistor from the clock signal input node when the latch circuit is in an inactive state; The potential of the gate electrode of the sixth n-type transistor electrically separated from the signal input node Characterized in that it is composed of a potential fixing means for fixing the potential.

According to the above configuration, when the gates of the fourth and sixth n-type transistors are electrically disconnected from the clock signal input node by the switching means of the first and second clock signal input control units. The potentials of the gate electrodes of the fourth and sixth n-type transistors are fixed at a predetermined value by potential fixing means. Thus, malfunction of the latch circuit during the transition from the active state to the inactive state is prevented.

According to a twenty-fifth aspect of the present invention, in the shift register circuit according to the twenty-fourth aspect, the switching means of the first clock signal input control unit includes a source electrode connected to the clock signal input node and a drain connected to the clock signal input node. An electrode is connected to the gate electrode of the fourth n-type transistor, and a gate electrode is formed of a 15-th n-type transistor connected to the pulse signal input node;
The switching means of the clock signal input control unit has a source electrode connected to the clock signal input node,
A drain electrode is connected to a gate electrode of the sixth n-type transistor, and a gate electrode is formed of a 16n-type transistor connected to the pulse signal output node.

According to the above configuration, when the pulse signal input to the gate electrodes of the fifteenth and sixteenth n-type transistors is “L”, that is, when the latch circuit is in an inactive state, the fifteenth and sixteenth transistors are not activated. The 16n-type transistor is turned off, and the input of the clock signal to the gate electrodes of the fourth and sixth n-type transistors is stopped. Thus, the latch circuit shifts to an operation as a level holding circuit.

According to a twenty-sixth aspect of the present invention, in the shift register circuit according to the twenty-fourth aspect, the potential fixing means of the first clock signal input control section has a source electrode connected to the fourth clock signal input control section.
A 17th n-type transistor is connected to the gate electrode of the n-type transistor, the drain electrode is connected to the ground potential, and the gate electrode is connected to the power supply potential. The fixing means includes an eighteenth transistor in which the source electrode is connected to the gate electrode of the sixth n-type transistor, the drain electrode is connected to the ground potential, and the gate electrode is connected to the power supply potential.
It is characterized by comprising an n-type transistor.

According to the above arrangement, when the switching means electrically disconnects the gate electrodes of the fourth and sixth n-type transistors from the clock signal input node, the fourth and sixth n-type transistors are electrically connected to each other. The gate electrode of the transistor is fixed at the ground potential. In this manner, a malfunction that occurs when the latch circuit transitions from the inactive state to the active state is prevented. Furthermore, when the potential fixing means is constituted by a transistor, the element area becomes smaller than that when the potential fixing means is constituted by a resistor.

According to a twenty-seventh aspect of the present invention, in the shift register circuit according to the twenty-fourth aspect, the potential fixing means of the first clock signal input control section has a source electrode connected to the fourth clock signal input control section.
a second clock signal input control unit connected to the gate electrode of the n-type transistor, comprising a nineteenth n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to its own source electrode; The potential fixing means is a 20th n-type transistor having a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential, and a gate electrode connected to its own source electrode. It is characterized by comprising.

According to the above configuration, when the switching means electrically disconnects the gate electrodes of the fourth and sixth n-type transistors from the clock signal input node, the fourth and sixth n-type transistors are electrically connected to each other. The gate electrode of the transistor is fixed to the threshold voltage of the 19th and 20th n-type transistors. In this manner, a malfunction that occurs when the latch circuit transitions from the inactive state to the active state is prevented. Furthermore, as compared with the case where the gate electrodes of the nineteenth and twentieth n-type transistors are connected to the power supply potential as in the case of the invention according to claim 7, the wiring layout on the circuit is simplified and the circuit area is reduced. Is done.

According to a twenty-eighth aspect of the present invention, in the shift register circuit according to the twenty-fourth aspect, the potential fixing means of the first clock signal input control unit is provided between the gate electrode of the fourth n-type transistor and a ground potential. And the potential fixing means of the second clock signal input control unit comprises a second resistor interposed between the gate electrode of the sixth n-type transistor and a ground potential. It is characterized by comprising.

According to the above configuration, when the switching means electrically disconnects the gate electrodes of the fourth and sixth n-type transistors from the clock signal input node, the fourth and sixth n-type transistors are electrically connected to each other. The gate electrode of the transistor is fixed at the ground potential. In this manner, a malfunction that occurs when the latch circuit transitions from the inactive state to the active state is prevented. Further, since the structure of the potential fixing means is simplified, the manufacturing process is simplified. Furthermore, the circuit area is reduced by forming the resistor under the wiring and arranging the resistor in a multilayer manner.

According to a twenty-ninth aspect of the present invention, in the shift register circuit according to the twenty-fifth aspect, the potential fixing means of the first clock signal input control section includes a source electrode connected to the fourth clock signal input control section.
a second n-type transistor connected to a gate electrode of the n-type transistor, a drain electrode connected to the ground potential, and a gate electrode connected to the inverted pulse signal input node; The potential fixing means of the control unit may include a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential, and a gate electrode connected to the inverted pulse signal output node. It is characterized by comprising a 22n-type transistor.

According to the above configuration, when the switching means electrically disconnects the gate electrodes of the fourth and sixth n-type transistors and the clock signal input node, the fourth and sixth n-type transistors are electrically disconnected. The gate electrode of the transistor is fixed at the ground potential. In this manner, a malfunction that occurs when the latch circuit transitions from the inactive state to the active state is prevented. On the other hand, when the switching means electrically connects the gate electrodes of the fourth and sixth n-type transistors to the clock signal input node, the twenty-first and twenty-second n-type transistors are turned off, and the 4. The conduction current from the gate electrode of the sixth n-type transistor to the ground potential is prevented.

According to a thirtieth aspect of the present invention, a plurality of data signal lines are arranged in the column direction, a plurality of scanning signal lines are arranged in the row direction, and a plurality of data signal lines are arranged at positions surrounded by the data signal lines and the scanning signal lines. A plurality of pixels arranged one by one and arranged in a matrix, a data signal line driving circuit for supplying a video signal to the data signal line, and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal line In the matrix type image display device, at least one of the data signal line driving circuit and the scanning signal line driving circuit includes:
A shift register circuit according to any one of claims 18 to 29 is used.

According to the above configuration, at least one of the data signal line driving circuit and the scanning signal line driving circuit is configured using the shift register circuit according to any one of claims 18 to 29. ing. Therefore,
The one signal line drive circuit described above has an amplitude of the transfer pulse signal.
(That is, the power supply voltage). For this reason, the power consumption of a clock wiring having a large wiring load capacity due to a long wiring length and the power consumption of an external circuit for generating a clock are significantly reduced. Further, when the latch circuit constituting the shift register circuit of the signal line driving circuit is in an inactive state, the input of the clock signal to the shift register circuit is stopped by the clock signal input control unit, and the clock signal Wire loading is reduced.

According to a thirty-first aspect of the present invention, in the image display device of the thirtieth aspect, the one signal line driving circuit is configured using the shift register circuit of the twenty-second aspect. A drive signal for driving a corresponding signal line is generated using an output signal having a smaller pulse width among two output signals of a pulse signal and an inverted pulse signal from each latch circuit included in a shift register circuit. It is characterized by having become.

According to the above configuration, the drive signal is generated by using the output signal having the smaller pulse width of the output pulse signal or the output inversion pulse signal, so that the time in the output signal from the adjacent latch circuit is reduced. No overlap. Therefore, when the one signal line driving circuit is a data signal line driving circuit, the sampling signals generated by the adjacent latch circuits do not overlap in time. Therefore, the writing of the video signal to another data signal line does not start while the video signal is being written to one data signal line. In the case of a scanning signal line driver circuit, scanning signals generated by adjacent latch circuits do not overlap with each other in time. Therefore, writing of video data to pixels in another row does not start while video data is being written to pixels in a certain row. That is, in any of the signal drive circuits, noise is not superimposed on the video signal, and a good image can be obtained without adding a circuit for narrowing the pulse width of the drive signal.

In such a case, generally, a large through current flows in the level shift circuit when the signal is switched.
In the configuration of this latch circuit, a through current flows only at the time of switching of the output signal (that is, at the time of propagation of the pulse signal), not at the time of switching of the clock signal, so that power consumption is extremely reduced.

According to a thirty-second aspect of the present invention, in the image display device of the thirtieth aspect, the shift register circuit of the one signal line driving circuit amplifies the amplitude of the start signal having the same amplitude as the clock signal. Wherein a level shifter circuit for supplying the pulse signal to the first-stage latch circuit is provided.

According to the above configuration, in the one signal line driving circuit, the start signal is boosted in advance and then input to the first-stage latch circuit of the shift register circuit. Therefore, even if the first-stage latch circuit has the same configuration as the other-stage latch circuits, a stable operation is realized. Further, as in the case of the clock signal, the amplitude of the start signal can be made smaller than the drive voltage, and the power consumption of the external circuit for generating the start signal can be reduced.

According to a thirty-third aspect of the present invention, in the image display device according to the thirtieth aspect, the level shifter amplifies the amplitude of the control signal having the same amplitude as the clock signal and supplies the amplified control signal to the one signal line driving circuit. A circuit is provided.

According to the above configuration, a control signal to a buffer circuit or the like other than the shift register circuit is boosted in advance and then input. Therefore, the amplitude of all the control signals input to the one signal drive circuit can be made smaller than the drive voltage, and the power consumption of the control signal generation external circuit can be reduced.

According to a thirty-fourth aspect of the present invention, in the image display device according to the thirtieth aspect, the one signal line driving circuit is formed on the same substrate as the pixels.

According to the above configuration, the pixel for displaying and the one signal line driving circuit for driving the pixel are manufactured on the same substrate in the same step. Thus, the manufacturing cost and the mounting cost can be reduced, and the non-defective product rate can be increased.

According to a thirty-fifth aspect of the present invention, in the image display device according to the thirty-fourth aspect, the one of the signal line driving circuits and the active elements forming the pixels are polycrystalline silicon thin film transistors. .

According to the above structure, the use of the polycrystalline silicon thin-film transistor having a characteristic of extremely high driving force as compared with the amorphous silicon thin-film transistor used in the conventional active matrix type liquid crystal display device allows the pixel and the pixel to be formed. The signal line driver circuit is easily formed over the same substrate.

Further, although the polycrystalline silicon thin film transistor has extremely high driving power as compared with the amorphous silicon thin film transistor, its driving power is smaller by one to two digits than the single crystal silicon transistor. Therefore, when a level shifter circuit is formed by using the above-mentioned polycrystalline silicon thin film transistor, there is a possibility that the duty of a signal is largely changed. However, according to the configuration of the shift register circuit in the one signal line driving circuit, it is possible to obtain an output signal having substantially the same pulse width from any one of the latch circuits in the shift register circuit, and to achieve a good image display. Is realized. At that time, the polycrystalline silicon thin film transistor has a large load on the clock signal line because the driving width is low and the channel width needs to be large. However, according to the configuration of the shift register circuit in the one signal line driving circuit, the first and second clock signal input control units connect the clock signal line only to the driving transistor of the latch circuit in the operating state. Thus, the load on the clock signal line and the power consumption of the drive circuit can be reduced.

According to a thirty-sixth aspect, in the image display device according to the thirty-fifth aspect, the polycrystalline silicon thin film transistor is formed on a glass substrate by a process at 600 ° C. or lower.

According to the above configuration, the polycrystalline silicon thin film transistor is formed on a glass substrate by a process at a temperature of 600 ° C. or less. Therefore, although the strain point temperature is low,
Glass, which is inexpensive and easy to increase in size, can be used as a substrate, and a large-sized image display device is manufactured at low cost.

[0112]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram showing an example of the shift register circuit according to claim 14. The shift register circuit 11 is configured by connecting a plurality of latch circuits (half latch circuits) LAT in series. That is, the start signal (pulse signal) st is input to the input node of the first-stage latch circuit LAT, while the input node of the second-stage latch circuit LAT is connected to the output node. Similarly, the input node of each latch circuit LAT is connected to the output node of the preceding latch circuit LAT, while the output node is connected to the input node of the subsequent latch circuit LAT. The clock signal ck is input to the control node of the odd-numbered latch circuit LAT. On the contrary,
A clock signal / ck, which is an inverted signal of the clock signal ck, is input to the control node of the even-numbered latch circuit LAT.

As described above, each latch circuit LAT in the present embodiment is controlled by one of the clock signal ck and the clock signal / ck. Here, it is assumed that the drive voltage of the shift register circuit 11 is 16 V, while the amplitude of the clock signals ck and / ck is 5 V. As described above, by inputting the clock signals ck and / ck of a voltage lower than the drive voltage of the shift register circuit 11,
Power consumption by the clock signals ck and / ck can be suppressed. Some of the signals require an inverted signal thereof, but are omitted here (detailed later).

FIG. 2 shows an example of a circuit configuration of the latch circuit according to claim 4 which constitutes the shift register circuit 11 in FIG. The power supply potential Vcc (= 16 V) is connected to the source electrodes of the two p-type transistors M11 and M12 as the first and second p-type transistors. The gate electrode of the p-type transistor M11 is connected to the drain electrode of the p-type transistor M12, while the gate electrode of the p-type transistor M12 is connected to the drain electrode of the p-type transistor M11.

The source electrode of the n-type transistor M13 as the first n-type transistor is connected to the drain electrode of the p-type transistor M11 to form an output node / OUT. The drain electrode of the n-type transistor M13 is connected to the ground potential GND, while the gate electrode is connected to the drain electrode of the p-type transistor M12. Similarly, the drain electrode of the p-type transistor M12
The source electrode of an n-type transistor M14 as a type transistor is connected to form an output node OUT. The drain electrode of the n-type transistor M14 is connected to the ground potential GND, while the gate electrode is connected to the drain electrode of the p-type transistor M11.

Further, between the drain electrode (output node / OUT) of the p-type transistor M11 and the ground potential GND,
Two n-type transistors M15 and M16 connected in series as third and fourth n-type transistors are provided. The input terminal is connected to the gate electrode of the n-type transistor M15.
While a pulse signal is input from IN, a clock signal is input from the input terminal CK to the gate electrode of the n-type transistor M16. Similarly, two n-type transistors M17 and M18 connected in series as fifth and sixth n-type transistors are connected between the drain electrode (output node OUT) of the p-type transistor M12 and the ground potential GND. Has been established. The input terminal / I is connected to the gate electrode of the n-type transistor M17.
While the inverted signal of the above pulse signal is input from N, n
A clock signal is input to the gate electrode of the type transistor M18 from the input terminal CK.

FIG. 3 shows a configuration in which first and second clock signal input sections 12 and 13 are added to the latch circuit of FIG.
Latch circuit as an example of the shift register circuit described in 1.
Shows LAT. The first clock signal input control unit 1
2 is an input node connected to the input terminal IN of the n-type transistor M15 to receive the pulse signal as a first control signal and a clock input node CK to which a clock signal ck (clock signal / ck) is input. And an output node CKIA connected to the gate of the n-type transistor M16. Then, the logic level of the first control signal is "H".
And when the clock signal ck (/ ck) is active, the potential level of the output node CKIA becomes “H”. The second clock signal input control unit 13 is connected to the output node OU.
Output pulse signal out as a second control signal connected to T
, An input node to which the clock signal ck (/ ck) is input, and an output node CKIB connected to the gate of the n-type transistor M18. Then, the logic level of the second control signal is "H".
And when the clock signal ck (/ ck) is active, the potential level of the output node CKIB becomes “H”.

The above-structured latch circuit LAT operates as follows. FIG. 4 shows a clock signal ck (/ ck) input to a clock input node CK, pulse signals in and / in input to input nodes IN and / IN, an output signal ckia from an output node CKIA, and an output signal ckia. FIG. 7 is a waveform diagram of an output signal ckib from a node CKIB and pulse signals out and / out output from output nodes OUT and / OUT. Hereinafter, the operation of the latch circuit LAT will be described with reference to FIGS. In this embodiment, the input pulse signal in is used as the first control signal, while the output pulse signal out is used as the second control signal.

[0119] First, at time t ₁ in FIG. 4, the clock signal ck (/ ck) becomes "H (active)". Then, the input pulse signal in (first control signal) becomes “H”.
Therefore, the output signal ckia from the output node CKIA of the first clock signal input control unit 12 becomes “H”. As a result, the n-type transistors M15 and M16 turn on, and the output node / OUT goes to the GND level. Then, the gate potential becomes "L" of the p-type transistor M12, a p-type transistor M12 is turned on, at time t _2, the output node OUT becomes Vcc (16V) level. Therefore, the p-type transistor M11 is turned off, and the potential of the output node / OUT is fixed to GND.

Since the output pulse signal out (second control signal) from the output node OUT is Vcc and the clock signal ck (/ ck) is also "H", the second clock signal input control unit 13 Is high, and the n-type transistor M18 is turned on. However, since the input pulse signal / in is "L", the n-type transistor M17 is turned off. Further, since the output node / OUT is at the GND level, the p-type transistor M14 is off. Therefore, the potential of the output node OUT is determined to Vcc.

That is, in the latch circuit LAT of the present embodiment, when the logic levels of the first and second control signals are “H” and the clock signal ck (/ ck) is active, the latch circuit LAT shown in FIG. It operates as a normal level shifter circuit as shown.

[0122] Then, at time t ₃ in FIG. 4, the clock signal ck (/ ck) becomes "L". Then, the output signals ckia and ckib from the first and second clock signal input control units 12 and 13 become “L”. Therefore, the n-type transistors M16 and M18 are turned off, the latch circuit LAT simply operates as a level holding circuit, the level of the output node / OUT is held at GND, and the level of the output node OUT is held at Vcc (16V). Because

That is, the latch circuit LAT according to the present embodiment operates as a level holding circuit except that it operates as the level shifter circuit between the time points t ₁ and t ₃ .

[0124] Then, at time t _4, the clock signal
ck (/ ck) becomes "H". Then, the output pulse signal o
Since ut (second control signal) is “H”, the output signal ckib from the output node CKIB of the second clock signal input control unit 13
Becomes "H". Further, the input inversion pulse signal / in is “H”. As a result, the n-type transistors M17, M18
There turned on, the output node OUT at time t ₅ the output signal ckib becomes GND level becomes "L". Then, p
P-type transistor M11 gate potential becomes "L" type transistor M11 is turned on, at time t _6, the output node / OUT becomes Vcc (16V) level.

As described above, the latch circuit LAT according to the present embodiment operates when the logic levels of the first and second control signals are “H” and the clock signal ck (/ ck) is active. It operates as a level shifter circuit, and otherwise operates as a level holding circuit. That is,
This latch circuit LAT functions as a latch circuit having a level shifter function. Therefore, as shown in FIG. 1, by connecting a plurality of the present latch circuits LAT in series to form the shift register circuit 11, the driving voltage
It can be operated with a clock signal having an amplitude lower than (Vcc), and the power consumption of an external circuit for generating a clock signal can be reduced.

Further, as shown in FIG.
Rises later than the fall of the output signal / out. Therefore, when the shift register circuit 11 is configured by connecting a plurality of the latch circuits LAT in series, a predetermined time interval can be provided at the rising timing of the output signal out from the two adjacent latch circuits LAT. Therefore, if the present shift register circuit 11 is used as a data signal line drive circuit in an image display device, even if the characteristics of the transistors M11 to M18 change, the timing of the output signals from the two adjacent latch circuits LAT slightly shifts. Even if it occurs, it is possible to prevent the sampling signals corresponding to the adjacent data signal lines from overlapping. Therefore, noise is not superimposed on the data signal line, and there is no risk of causing bleeding, ghosts, crosstalk, and the like in the display image.

At this time, as shown in FIG. 4, the pulse width of the output signal is different from the pulse width of the clock signal, but the level changes in the latch circuit LAT in any stage. The pulse width of the output signal does not change alternately in each stage of the latch circuit LAT. Therefore, in the data signal line driving circuit, there is no deviation in the timing at which the image data is taken into the data signal line, and good display quality can be obtained.

Further, as described above, when the latch circuit LAT in the present embodiment is in an inactive state, it operates as a level holding circuit to operate the clock signal ck (/ c
The clock signal ck (/ ck) is not required because it only keeps a constant state regardless of the state of k). Therefore, in the case of the above-mentioned inactive state, the first and second clock signal input control units 12 and 13 control the clock input node C
By electrically disconnecting K from the output nodes CKIA and CKIB, the load on the clock signal line and the power consumption can be reduced.

FIG. 5 shows an example of the latch circuit according to the fifth aspect. This latch circuit is connected to the ground potential GND of the first and second n-type transistors M13 and M14 of the latch circuit of FIG.
In the seventh, the inverted clock signal / CK is input to the gate,
Transistors M19 and M20 as eighth n-type transistors
Is different from the latch circuit of FIG. That is,
The source electrode and the drain electrode of the transistor M19 are connected to the drain electrode of the transistor M13 and the ground potential GND, respectively. The source electrode and the drain electrode of the transistor M20 are
The drain electrode of the transistor M14 is connected to the ground potential GND.

The latch circuit of FIG. 5 operates similarly to the level shifter circuit described with reference to FIG. That is, the clock signal
When CK is active, transistors M11, M12, M
13, M15 constitute a level shifter circuit, and when the inverted clock signal / CK is active, the transistors M11,
M12, M17 and M18 form a latch circuit (two mutually connected inverter circuits). The waveforms of the clock signal (CK, / CK), input pulse signal (IN, / IN), and output pulse signal (OUT, / OUT) of this latch circuit are described with reference to FIG. 4 except that there are no signals ckia and ckib. Signal waveform. The latch circuit operates as a circuit having a level shift function and a latch (hold) function at the same time, and some of the transistors (M11 and M12) of the respective circuit configurations that control the level shift function and the latch function are shared. Therefore, the circuit size is not significantly increased as compared with the case where the respective circuits are separately configured.

As a result, a relatively large drive voltage Vcc can be output by inputting the clock signals CK, / CK or the input signals IN, / IN having a small amplitude to the latch circuit. Note that, here, the positions of the transistors connected in series may be interchanged (this also applies to other embodiments).

FIG. 6 shows an example of the latch circuit according to the sixth aspect. The latch circuit of FIG. 6 includes ninth and tenth transistors instead of the n-type transistors M16 and M18 of the latch circuit of FIG.
The n-type transistors M21 and M22 are used as the n-type transistors. The source electrode of the n-type transistor M21 is connected to the drain electrodes of the n-type transistors M15 and M17, and the drain electrode is connected to the ground potential GND. The only difference from the latch circuit of FIG. 2 is that the electrodes are connected to the drain electrodes of the n-type transistors M13 and M14, and the drain electrode is connected to the ground potential GND. That is, in this latch circuit, the transistors M16 and M18 to which the clock signal (CK) of FIG.
Since the common transistor M22 to which the inverted clock signal (/ CK) is input is provided on the ground terminal side of the transistors M13 and M14 of FIG. The number is small and the circuit size can be reduced.

The present invention can be realized even if the polarities of all the transistors are reversed from those of the present embodiment and the polarities of the power supply and the signal are all reversed, and the same effects as described above can be expected. This applies not only to the present embodiment but also to other embodiments (however, when an AND circuit and an OR circuit are used, it is necessary to replace them with an OR circuit and an AND circuit, respectively). There is).

FIG. 7 shows an example of the latch circuit according to the seventh aspect. This latch circuit uses an n-type transistor M21 as a ninth n-type transistor in place of the n-type transistors M16 and M18 of the latch circuit in FIG. 2, and connects the source electrodes of the n-type transistor M21 to n-type transistors M15 and M1.
The only difference from the latch circuit of FIG. 2 is that the drain electrode of FIG. 7 is connected to the ground potential GND. That is,
This latch circuit is provided with a clock signal (C
Since the transistors M16 and M18 to which (K) is input are one transistor M21, the number of elements can be further reduced.

FIG. 8 shows an example of the latch circuit according to the eighth aspect. This latch circuit includes first and second AND-NOR circuits AND-NOR1 and AND-NOR2,
The inputs of the AND circuit portion of the first AND-NOR circuit AND-NOR1 are the clock signal (CK) and the pulse signal (IN), and the input of the first AND-NOR circuit AND-NOR1 is The input of the NOR circuit is connected to the output signal of the AND circuit and the second signal.
AND-NOR2 AND-NOR2 output signal B (/ OUT)
It is. Further, a second AND-NOR circuit AND-NOR2
Are the clock signal (CK) and the inverted signal (/ IN) of the pulse signal, and the input of the NOR circuit of the second AND-NOR circuit AND-NOR2 is An output signal of the AND circuit unit and a first AND-AND circuit AND-
This is the output signal A (OUT) of NOR1. Where one of the input signals
The amplitude of (one of IN and CK) is smaller than the drive voltage Vcc. Each signal (CK and IN, or / CK and / I
N) each require an inverted signal, which is not shown.

FIG. 9 shows an example of the latch circuit according to claim 9, which constitutes the AND-NOR1 and AND-NOR2 circuits shown in FIG. This latch circuit is shown in FIG.
2. Instead of the n-type transistor M14 of the latch circuit, a transistor M23 as an eleventh n-type transistor to which an inverted clock signal (/ CK) is input to the gate electrode is used, and instead of the n-type transistor M18 of FIG. 2 is different from the latch circuit of FIG. 2 only in that the inverted signal (/ B) of the output signal is input to the transistor M24, and the transistor M24 is used as a twelfth n-type transistor whose source electrode is also connected to the transistor M23. Even with such a configuration, it is possible to input a clock signal (CK, / CK) having an amplitude smaller than the power supply voltage and obtain a logical result of a desired amplitude (power supply amplitude).

As described above, the positions of the transistors M17 and M23 and the transistor M24 in FIG. 9 may be interchanged.

FIG. 10 shows an example of the latch circuit according to the tenth aspect. This latch circuit includes first to fourth NAND circuits NAND1, NAND2, NAND3, and NAND4, and an input of the first NAND circuit NAND1 receives a clock signal (CK).
And a pulse signal (IN), and a second NAND circuit NA
ND2 input is clock signal (CK) and inverted pulse signal
(/ IN), the inputs of the third NAND circuit NAND3 are the output signal X of the first NAND circuit NAND1 and the output signal (/ OUT) of the fourth NAND circuit NAND4, The inputs of the fourth NAND circuit NAND4 are the output signal Y of the second NAND circuit NAND2 and the output signal (OUT) of the third NAND circuit NAND3.
It is. Also in this latch circuit, the amplitude of one (IN or / IN) of the signals input to the first and second NAND circuits NAND1 and NAND2 can be made smaller than the drive voltage Vcc. Note that each signal (CK and IN or / CK and
/ IN) each require an inverted signal, which is not shown.

FIG. 11 shows an example of the latch circuit according to claim 11, which constitutes the first and second NAND circuits NAND1 and NAND2 shown in FIG. This latch circuit
The transistors M13 and M24 of the latch circuit of FIG. 9 are omitted, and the transistors M17 and M23 of FIG. 9 are replaced by a first transistor having a drain electrode connected to the ground potential GND.
3. a transistor M25 as a fourteenth n-type transistor;
The only difference from the latch circuit of FIG. According to this configuration as well, a clock signal (CK, / CK) having an amplitude smaller than the power supply voltage Vcc is input, and a desired amplitude (power supply amplitude) is obtained.
Can be obtained.

FIG. 12 shows an example of the latch circuit according to the twelfth aspect. In this latch circuit, the transistors M13, M14, M15, and M17 on the output terminals OUT and / OUT of the n-type transistors shown in FIG.
b, M17a, M17b, and the transistor M1 on the ground potential GND side
6, M18, M19 and M20 have a single gate structure. Thus, it is possible to improve the reliability of the circuit while minimizing the increase in the input capacitance.

FIG. 13 shows an example of the latch circuit according to the thirteenth aspect. In this latch circuit, the transistor M1 on the ground potential GND side among the n-type transistors in FIG.
6, the channel length of M18, M19 and M20 is 6 μm, and the output terminal O
The channel length of the transistors M13, M14, M15, M17 on the UT, / OUT side is increased to 8 μm. Thus, it is possible to improve the reliability of the circuit while minimizing the increase in the input capacitance.

FIG. 14 shows a modification of the latch circuit shown in FIG. This latch circuit is connected to the output terminal OU of FIG.
The transistors M13 and M14 on the T and / OUT sides are replaced with n-type transistors M27 and M28, and the transistors M19 and M20 on the ground potential GND side in FIG. 5 are replaced with n-type transistors M29 and M30. 5 is different from the latch circuit in FIG. 5 in that the series connection of the transistors M15 and M16 and the transistors M17 and M18 in FIG. 5 is reversed. The signals IN and CK and / IN and CK input to the gate electrodes of the transistors M15 and M16 and the transistors M17 and M18 in FIG. 14 can be reversed. In this way, the smaller amplitude signals (CK, / CK) are input to the transistors M15 and M17 on the ground potential GND side in FIG. 14, so that the operation is stabilized and the operation speed is improved. That is, the configuration shown in FIG. 5 is more preferable than the configuration shown in FIG.

FIG. 15 shows an example of the latch circuit according to the twelfth aspect. This latch circuit is a modified example in which transistors M41 and M42 as third and fourth p-type transistors are added to the latch circuit described in FIG. The third p-type transistor M41 has a source electrode connected to the drain electrode of the first p-type transistor M11 and a drain electrode connected to the first p-type transistor M11.
The gate of the n-type transistor M13 is connected to the fourth n-type transistor M16 to which the clock signal (CK) is input.
The fourth p-type transistor M42 has a source electrode connected to the drain electrode of the second p-type transistor M12 and a drain electrode connected to the second n-type transistor M1.
The fourth source electrode and the gate electrode are connected to the gate electrode of the sixth n-type transistor M18 to which the clock signal (CK) is input. In this latch circuit, between the power supply potential Vcc of the latch circuit of FIG. 2 and both output nodes OUT and / OUT, the third and fourth p-type transistors M41 and M42 whose clock signals (CK) are input to the gate electrodes are connected. Both output nodes O
When UT, / OUT becomes low level (ground potential),
The type transistors M41 and M42 act to limit the current from the power supply potential Vcc side, and the operation margin is expanded.

FIG. 16 shows an example of the latch circuit according to the thirteenth aspect. This latch circuit is a modification example in which the same transistors M41 and M42 as the third and fourth p-type transistors described in FIG. 15 are connected and added to the latch circuit described in FIG. Therefore, in this latch circuit, between the power supply potential Vcc of the latch circuit of FIG. 5 and the two output nodes OUT and / OUT, the third and fourth p-type transistors M41 and M41 in which the clock signal (CK) is input to the gate electrode are provided. The addition of M42 allows the p-type transistors M41, M42 to operate when both output nodes OUT and / OUT are at a low level (ground potential).
However, this works to limit the current from the power supply potential Vcc side, and the operation margin is expanded.

FIG. 17 shows an example of the latch circuit according to the fourteenth aspect. This latch circuit is a modification example in which transistors M41, M42, M43, and M44 as third to sixth p-type transistors are added to the latch circuit described in FIG. The third and fourth p-type transistors M41 and M42 are the same as those described with reference to FIG.
While connected between M12 and the first and second n-type transistors M13 and M14, the fifth p-type transistor M43 is connected to the third p-type transistor M41, and the sixth p-type transistor M44 is connected to the fourth p-type transistor M44.
5p are connected in parallel with the
The input pulse signal (I
N), the inverted signal (/ IN) of the input pulse signal is input to the gate electrode of the sixth p-type transistor M44. In this latch circuit, a clock signal is applied to a gate electrode between the power supply potential Vcc of the latch circuit of FIG. 2 and both output nodes OUT and / OUT.
(CK) and the input pulse signal (IN) are input respectively, and the third and fifth p-type transistors M41 and M43 connected in parallel to each other, and the clock signal (CK) and the inverted signal of the input pulse signal (/ IN) are input, and the fourth and sixth p-type transistors M42 and M44 connected in parallel to each other are added. Therefore, when both output nodes OUT and / OUT become low level (ground potential), Each p-type transistor M41, M42, M43, M4
4 acts to limit the current from the power supply potential Vcc side, further expanding the operation margin.

FIG. 18 shows an example of the latch circuit according to the fifteenth aspect. This latch circuit is a modification example in which transistors M41 to M44 as third to sixth p-type transistors, which are the same as those described in FIG. 17, are connected to the latch circuit described in FIG. Therefore, in this latch circuit, the clock signal (CK) and the clock signal are applied to the gate electrode between the power supply potential Vcc of the latch circuit of FIG. 5 and both output nodes OUT and / OUT.
The input pulse signal (IN) is input, and the third and fifth p-type transistors M41 and M43 connected in parallel with each other, and the clock signal (CK) and the inverted signal (/ IN) of the input pulse signal are respectively input to the gate electrodes. Input and connected in parallel with each other,
Since the sixth p-type transistors M42 and M44 are added,
During the operation in which both output nodes OUT and / OUT become low level (ground potential), each of the p-type transistors M41, M42, M43, M44
However, it works to limit the current from the power supply potential Vcc side, and the operation margin is further expanded.

Now, the first and second clock signal input control units 12 and 13 described in FIG. 3 will be specifically described below. Since the first clock signal input control unit 12 and the second clock signal input control unit 13 have the same circuit configuration,
The following description is made on behalf of the first clock signal input control unit 12. FIG. 19 shows an example of the first clock signal input control unit 12 of the shift register according to claims 24 to 26.

The first clock signal input control section 12
It is roughly composed of two n-type transistors TG and TD as switching means and potential fixing means. The drain electrode of the transistor TG serving as the 15th n-type transistor serving as the switching means is connected to the gate of the n-type transistor M16 forming the latch circuit LAT to form the output node CKIA. The clock input node CK is connected to the source electrode of the transistor TG,
The first control signal (input pulse signal in) is input to the gate electrode. The output node CKIA is connected to the source electrode of a transistor TD as a 17n-th transistor serving as a potential fixing means, while the drain electrode is connected to the ground potential GND. Further, the gate electrode is connected to the power supply potential Vcc (= 16 V). The second clock signal input control unit 13 includes a sixteenth n-type transistor as a switching means and an eighteenth transistor as a potential fixing means.
An n-type transistor is provided as well.

First clock signal input control unit 1 having the above configuration
2, when the logic level of the first control signal (input pulse signal in) becomes "H", the n-type transistor TG is turned on, the clock input node CK and the output node CKIA are connected, and the n-type transistor M16 The clock signal ck is input. Further, the input pulse signal in is supplied to the n-type transistor M15
Is also input to the gate. As a result, as described above, when the input pulse signal in and the output pulse signal out are “H” and the clock signal ck (/ ck) is active, the n-type transistors M15 and M16 connected in series
Turns on, and the latch circuit LAT operates as a level shifter circuit.

On the other hand, when the logic level of the first control signal in is "L", the n-type transistor TG is turned off, and the output node CKIA enters a floating state. Therefore, while the gate electrode is connected to the power supply potential Vcc, the drain electrode is connected to the ground potential GND, the n
The on-resistance of the type transistor TD is used as a pull-down resistor to fix the potential of the output node CKIA. As a result, as described above, the n-type transistor M16 turns off regardless of the state of the clock signal ck (/ ck), and the latch circuit
The LAT operates as a level holding circuit.

That is, in the first clock signal input control section 12, the switching means is constituted by the n-type transistor TG, and the potential fixing means is constituted by the n-type transistor TD, the power supply potential Vcc and the ground potential GND. It is.

FIG. 20 shows an example of the first clock signal input control section 12 of the shift register according to claim 27. As in the case of FIG. 19, a transistor TG to which the first control signal (input pulse signal in) is input is provided between the gate electrode of the n-type transistor M16 and the clock input node CK. The output node CKIA is formed. Further, the output node CKIA is used as a pull-down resistor of the output node CKIA, and is used as a potential fixing means.
The source electrode of a transistor TD as a 9 n-type transistor is connected, the ground electrode GND is connected to the drain electrode of the n-type transistor TD, and the gate electrode is connected to its own source electrode. Therefore, the pull-down voltage becomes the threshold voltage of the n-type transistor TD. That is, FIG.
0 in the first clock signal input control unit 12a shown in FIG.
9, there is an advantage that the routing of the wiring is simplified as compared with the configuration of the first clock signal input control unit 12 shown in FIG. The second clock signal input control unit 13 is similarly provided with a 20n-th transistor as a potential fixing means.

FIG. 21 shows an example of the first clock signal input control section 12 of the shift register circuit according to claim 29. 19 and 20, between the gate electrode of the n-type transistor M16 and the clock input node CK, the first control signal (input pulse signal in) is input to the gate electrode of the n-type transistor TG. To form an output node CKIA. Furthermore, this output node CK
IA is connected to a source electrode of a transistor TD as a 21st n-type transistor which is used as a pull-down resistor of an output node CKIA and is a potential fixing means, and a ground potential GND is connected to a drain electrode of the n-type transistor TD.
The gate electrode of the n-type transistor TD has an inverted signal of the first control signal (the inverted signal of the second control signal in the case of the second clock signal input control unit 13) inputted to the gate electrode of the n-type transistor TG. ) Is entered. Therefore, when the n-type transistor TG is on, the n-type transistor TD is off, and the n-type transistor M16 generated when the clock input node CK and the output node CKIA are electrically connected is connected It is possible to prevent a through current from the gate electrode to the ground potential GND. The second
The clock signal input control unit 13 is similarly provided with a 22nd n-type transistor which is a potential fixing means.

FIG. 22 shows an example of the first clock signal input control section 12 of the shift register circuit according to claim 28. 19 to 21, between the gate electrode of the n-type transistor M16 and the clock input node CK, the first control signal (input pulse signal in) is applied to the gate electrode.
Output node through an n-type transistor TG
Forming the CKIA. Furthermore, to this output node CKIA,
The first used as the pull-down resistor of the output node CKIA
One end of a resistor R as a resistor is connected, and the other end is connected to a ground potential GND. Here, when the element areas of the resistor and the transistor having the same resistance value are simply compared, the area of the resistor is larger than that of the transistor. However,
The resistor has an advantage that the real area occupied can be reduced by performing multilayer wiring (forming the resistor below the wiring) by utilizing its simple structure. The second
The clock signal input control unit 13 is similarly provided with a resistor as a second resistor.

As described above, in the present embodiment,
Each of the latch circuits LAT constituting the shift register circuit 11 receives the clock signal ck or the inverted clock signal / ck.
The operation is performed in synchronization with only one of them. Therefore, the load on the clock signal line can be reduced by half as compared with the case where both the clock signal ck and the inverted clock signal / ck are used as in the latch circuit SR shown in FIG.
Power consumption can be reduced.

Each of the latch circuits LAT constituting the shift register circuit 11 has two p-type transistors M11 and M12 and two n-type transistors M15 and M17 (FIG. 4).
The n-type transistors M16 and M18 are interposed between the ground potential GND and the n-type transistors M3 and M4 connected to the ground potential GND of the level shifter circuit shown in FIG. The output signals ck of the first and second clock signal input control units 12 and 13 are connected to the gate electrodes of the n-type transistors M16 and M18.
ia and ckib are entered. In addition, the output node / OUT, OUT
Transistors N13 and M
14 is interposed. The output nodes OUT and / OUT are connected to the gate electrodes of the n-type transistors M13 and M14.

Therefore, the input pulse signal in to the first clock signal input control section 12 and the output pulse signal out to the second clock signal input control section 13 are "H" (that is, the latch circuit LAT is active). Clock signal
When ck is active, the latch circuit LAT functions as a level shifter like the level shifter circuit LS shown in FIG. On the other hand, the others can function as a level holding circuit.

As a result, the shift register circuit 11 can be operated with a clock signal having an amplitude lower than the drive voltage (Vcc), and the power consumption of an external circuit for generating a clock signal can be reduced. Further, the pulse width of the output signal out is smaller than the pulse width of the output signal / out. Therefore, by using the output signal out as the drive signal, a time interval can be provided between the output signals from the two adjacent latch circuits LAT. No noise is superimposed on the signal. When the latch circuit LAT is inactive, the first and second clock signal input control units 12 and 13
Clock input node CK and output nodes CKIA, CKIB
By electrically disconnecting the clock signal from the clock signal line, the load on the clock signal line and the power consumption can be reduced.

FIG. 23 shows an example of the latch circuit LAT constituting the shift register circuit according to claim 23. In FIG. 23, p-type transistors M11, M12, n
The type transistors M13 to M18 and the first and second clock signal input control units 15 and 16 correspond to the p-type transistors M11 and M12, the n-type transistors M13 to M18, and the first and second clock signal inputs in FIG. It has the same configuration as the control units 12 and 13 and functions similarly. The specific circuit configuration of the first and second clock signal input control units 15 and 16 is as shown in FIGS.

In the present embodiment, the input terminal of the first inverter INV is connected to the drain of the p-type transistor M11 (output node / OUT in the latch circuit LAT shown in FIG. 3). Similarly, the second terminal is connected to the drain of p-type transistor M12 (output node OUT in latch circuit LAT shown in FIG. 3).
Connect the inverter circuit INV. The output terminal of the first inverter INV is set to the output node OUT, while the output terminal of the second inverter INV is set to the output node / OUT. Generally, the level shifter circuit has a smaller driving force than other logic operation circuits. Therefore, by adding a circuit having a buffer function (amplifying function) such as an inverter circuit INV, the signal propagation to the subsequent stage can be ensured and the shift register operation can be performed stably. Clock signal ck (/ ck) input to node CK, pulse signals in and / in input to input nodes IN and / IN, output signal ckia output from output node CKIA, and output from output node CKIB Output signal ck
ib and the pulse signal ou output from the output nodes OUT and / OUT
The waveform of t, / out is shown. Compared with the waveform diagram shown in FIG. 4, the phase of the output signals out and / out is inverted due to the addition of the inverter circuit INV to the output nodes OUT and / OUT in FIG. It is earlier than the fall of the output signal / out.

Therefore, similar to the case of the latch circuit LAT shown in FIG. 3, when the shift register circuit 11 formed by the present latch circuit LAT is used for the data signal line drive circuit and the output signal / out is used, the adjacent one is used. Latch circuit LAT
Even if there is a slight deviation in the timing of the output signal / out from, overlapping of the sampling signals corresponding to the adjacent data signal lines can be prevented.

Note that the first and second clock signal input control units 15 and 16 of the latch circuit of FIG. 23 are removed, and the clock signal (CK) is input to the gate electrodes of the transistors M16 and M18, as described in FIG. The first and second inverters INV may be provided at the output terminals OUT and / OUT of the latch circuit. Also in this configuration, the buffer operation of the inverter INV ensures the signal propagation to the subsequent stage, and can perform the shift register operation stably.

FIG. 25 is a block diagram showing an example of the shift register circuit according to the twentieth aspect. The shift register circuit 21 is configured such that the output node and the input node of the latch circuit LAT adjacent to each other are connected via an analog switch ASW. That is, the input node of the first-stage latch circuit LAT is supplied with an external control signal lr.
A start signal (pulse signal) st is input via an analog switch ASW1 whose on / off control is performed. On the other hand, the output node is connected to the input node of the second-stage latch circuit LAT via the analog switch ASW1. Next, in addition to the output node of the first-stage latch circuit LAT, the input node of the second-stage latch circuit LAT is connected via an analog switch ASW2 that is turned on / off by an external control signal / lr. It is connected to the output node of the latch circuit LAT of the stage. On the other hand, the output node is connected to the input node of the first-stage latch circuit LAT via the analog switch ASW2,
Third stage latch circuit LAT via analog switch ASW1
Connected to the input node. Next, the input node of the third-stage latch circuit LAT is connected to the output node of the fourth-stage latch circuit LAT via the analog switch ASW2 in addition to the output node of the second-stage latch circuit LAT. . on the other hand,
The output node is connected to the input node of the fourth-stage latch circuit LAT via the analog switch ASW1 in addition to the input node of the second-stage latch circuit LAT. The input node of the fourth stage latch circuit LAT, which is the last stage,
In addition to the output signal from the third-stage latch circuit LAT, a start signal st is input via an analog switch ASW2.

The shift register circuit 21 having the above configuration can switch the scanning direction as follows. That is, when the control signal lr becomes active, the analog switch ASW1 that is turned on / off by the control signal lr is turned on, while the analog switch ASW2 that is turned on / off by the control signal / lr is turned off. Therefore, the start signal
The st is input to the first-stage latch circuit LAT, and the output pulse signal from the preceding-stage latch circuit LAT is sequentially input to the subsequent-stage latch circuit LAT. That is, the shift register circuit 2
1 scans from the first latch circuit LAT toward the last latch circuit LAT. On the other hand, the control signal
When lr becomes inactive, the analog switch ASW2 turns off while the analog switch ASW2 turns on. Therefore, the start signal st is the fourth stage (final stage) of the latch circuit LA.
Then, the output pulse signal from the subsequent latch circuit LAT is sequentially input to the preceding latch circuit LAT. That is, the shift register circuit 21 is connected to the last latch circuit LAT.
From the first to the first latch circuit LAT.

FIG. 26 is a circuit diagram of the latch circuit LAT and the analog switch ASW forming the shift register circuit 21 in FIG. Analog switch ASW1
Is configured such that the source electrode and the drain of an n-type transistor M31 whose gate electrode receives a control signal lr and a p-type transistor M32 whose control electrode / lr receives a gate electrode are connected. The output node / OUT of the latch circuit LAT or the output node OUT is connected to the source electrode side.
While the drain side is the output node / O
UT1 and OUT1. The analog switch ASW2 is
The source electrode and the drain of an n-type transistor M33 whose control signal / lr is input to its gate electrode and a p-type transistor M34 whose control signal lr is input to its gate electrode are connected to each other. Then, while the output node / OUT or the output node OUT of the latch circuit LAT is connected to the source electrode side, the drain side is connected to the output node / OUT2, OUT2 to the preceding stage.
And The latch circuit LAT in FIG. 26 is configured based on the latch circuit section shown in FIG. 3 and the clock signal input control section shown in FIG. 19, but the latch circuit section shown in FIG. It may be configured based on the clock signal input control unit.

FIG. 27 is a block diagram showing an example of the shift register according to claim 21 and a modification of the shift register circuit described in FIG. In this shift register circuit, a buffer circuit BUF is added between the output of each latch circuit LAT and the analog switches ASW1 and ASW2 as the first and second transfer gates for the preceding and subsequent latch circuits. In this shift register circuit as well, the scanning direction of the shift register circuit can be switched similarly to the shift register circuit of FIG. 25, and even when the driving force (signal propagation performance) of the latch circuit LAT is reduced through the analog switch ASW, Since the buffer circuit BUF is added, a large driving force can be obtained, and stable operation of the shift register circuit can be achieved. Note that each latch circuit and the like constituting the shift register circuit are shown in FIG.
Analog switches ASW1 on both sides of the latch circuit LAT described in
It can be configured by interposing the inverter INV described with reference to FIG. 23 at the output terminal toward ASW2.

FIG. 28 shows the shift register circuit 11 shown in FIG. 2 or the shift register circuit 21 shown in FIG. 25 (however, in this case, the control signal lr is activated to scan in the forward direction). FIG. 4 is a circuit configuration diagram of a data signal line drive circuit SD using the circuit diagram. The basic configuration of the present data signal line drive circuit SD is substantially the same as the conventional data signal line drive circuit SD shown in FIG. That is, the adjacent latch circuit LS forming the shift register circuit 25 The serial signal of the SR output signal / n is amplified by a buffer circuit composed of a plurality of inverter circuits, and an inverted signal is generated as necessary, and the sampling signal s and its inverted signal / s are generated.
Is output to the sampling circuit (analog switch) AS.
Then, the sampling circuit AS outputs the sampling signal s, /
It opens and closes based on s, and supplies video data dat from the video signal line DAT to the data signal line SL. Latch circuit LS in that case Clock signal cks, / cks to SR and latch circuit LS
SR output signals n1, / n1 to n3, / n3 and sampling signals s1, s
2 is shown in FIG.

In this case, the latch circuit LS constituting the shift register circuit 25 SR has the same configuration as the latch circuit LAT shown in FIG. 3 or FIG. 23, and is a latch circuit having a level shifter function. Therefore, an output signal n having an amplitude of 16 V and a clock signal cks, / cks having an amplitude of 5 V
1, / n1 to n3, / n3 can be output. Therefore,
Such a latch circuit LS In the case where the data signal line drive circuit SD including the shift register circuit 25 having the SR is used, a high drive voltage can be obtained with the clock signal cks, / cks having a low amplitude, and the absolute value of the threshold voltage is high. The clock signal cks, in the case of configuring the drive circuit integrated type liquid crystal display device using a polycrystalline silicon thin film transistor,
This prevents the increase in power consumption due to / cks.

Here, the latch circuit LS SR is shown in FIG.
It is assumed that the latch circuit LAT has the circuit configuration shown in FIG. The sampling signals s and / s for capturing the video data dat are supplied to the latch circuits LS of each stage in the shift register circuit 25. It is generated based on the row active output signal / n among the output signals n and / n from the SR. In this case, as for the output signals out and / out of the latch circuit LAT having the circuit configuration shown in FIG. 23, the pulse width of the output signal / out is smaller than the pulse width of the output signal out as shown in FIG. Therefore, in the sampling signals s, / s generated by the data signal line driving circuit SD, as shown in FIG. 29, there is no temporal overlap between the adjacent sampling signals s1, s2. That is, immediately before the writing of the video data to one data signal line SL is completed, the video data is not started to be written to another data signal line SL, and the noise is prevented from being superimposed on the data signal line SL. Good image display can be obtained.

In the above description, the latch circuit LS constituting the shift register circuit 25 has been described. SR is the latch circuit LAT having the circuit configuration shown in FIG. 23, and the sampling signals s, / s based on the row active output signal / n.
Has been generated. However, the latch circuit LS SR is
The latch circuit LAT having the circuit configuration shown in FIG. 3 may be used. In that case, the high active output signal n
If the sampling signals s, / s are generated based on, the adjacent sampling signals s1, s2 can be prevented from having a temporal overlap.

Further, as described above, the latch circuit LS constituting the shift register circuit 25 is used. SR (that is, the latch circuit LAT shown in FIG. 3 or FIG. 23)
It has the same first and second clock signal input control units as the clock signal input control units 12 and 13. Then, in the inactive state, the clock signal cks, / cks is not necessary since it simply operates as a level holding circuit. Therefore, in the case of the inactive state, the clock signal c is controlled by the first and second clock signal input control units.
By stopping the input of ks and / cks, the load on the clock signal line and the power consumption can be reduced. Note that each latch circuit LS in FIG. Of the clock signal and start signal input to SR, the inverted signal / c
Input of ks and / sps can be omitted.

FIG. 30 is a circuit diagram showing another configuration example of the data signal line drive circuit SD using the shift register circuit 11 or the shift register circuit 21. In the present data signal line drive circuit SD, the shift register circuit 26
First stage latch circuit LS On the start signal line SPS to SR,
A normal level shifter circuit LS having a circuit configuration as shown in FIG. 48 or FIG. 49 is provided. Then, the level shifter circuit LS boosts the start signals sps and / sps having the same amplitude of 5 V as the clock signals cks and / cks to an amplitude of 16 V, and the first-stage latch circuit LS. Supplies to SR.

As described above, by setting the amplitude of the start signal sps to 5 V, the data signal line driving circuit SD
The amplitude of all digital input signals can be 5V. That is, according to the present embodiment, the output level of the external signal generation circuit can be unified to 5 V, so that power consumption can be reduced and the system can be simplified.

FIG. 31 shows the shift register circuit 11 shown in FIG. 2 or the shift register circuit 21 shown in FIG. 25 (however, in this case, the control signal lr is activated to scan in the forward direction). FIG. 3 is a circuit configuration diagram of a scanning signal line driving circuit GD using the same. Main scanning signal line drive circuit
The basic configuration of the GD has a buffer circuit in which the pulse width control signal line GPS and the NOR circuit are removed from the buffer circuit of the conventional scanning signal line drive circuit GD shown in FIG. That is, the adjacent latch circuit LS forming the shift register circuit 27 A continuous signal of the SR output signal / n is taken by a NAND circuit, amplified by a buffer circuit composed of a plurality of inverter circuits, and supplied to the scanning signal line GL. Latch circuit LS in that case Clock signal ckg, / ckg to SR and latch circuit LS
FIG. 32 shows SR output signals n1, / n1 to n3, / n3 and scanning signals gl1, gl2 to the scanning signal line GL.

In this case, the latch circuit LS forming the shift register circuit 27 SR is a latch circuit having the same configuration as the latch circuit LAT shown in FIG. 3 or 23 and having a level shifter function. Therefore, as in the case of the data signal line drive circuit SD shown in FIG. 28 or FIG. 30, a high drive voltage can be obtained with the low amplitude clock signals ckg and / ckg, and the drive circuit It is possible to prevent an increase in power consumption due to the clock signals ckg and / ckg when configuring a liquid crystal display device having a body shape.

Also, the latch circuit LS It is assumed that SR is a latch circuit LAT having a configuration shown in FIG. 23, and a scanning signal gl for writing video data dat to pixels is supplied to the latch circuit LS of each stage. S
It is generated based on the row active output signal / n from R. Therefore, as in the case of the data signal line driving circuit SD shown in FIG. 28 or FIG. 30, there is no overlap between the adjacent scanning signals gl1 and gl2 as shown in FIG. In other words, immediately before the writing of the video data to the pixels in a certain row is completed, the video data is not started to be written to the pixels in another row, so that noise is prevented from being superimposed on the image signal, and a good image is obtained. You can get the display. Thus, according to the main scanning signal line driving circuit GD,
Latch circuit LS Generates scan signal gl based on row active output signal / n from SR and scans adjacent scan signals
Since overlap between gls can be eliminated, a supply circuit of the pulse width control signal gps for controlling the pulse width of the scanning signal gl as in the case of the scanning signal line driving circuit GD shown in FIG. is there.

In the case of the main scanning signal line driving circuit GD, the latch circuit LS SR is a latch circuit LAT having the circuit configuration shown in FIG.
When the scanning signal gl is generated based on the high active output signal n, the adjacent scanning signals gl1 and gl2 can be prevented from overlapping each other.

Further, as in the case of the data signal line drive circuit SD shown in FIG. 28 or 30, when the latch circuit LS is in the inactive state, By stopping the input of the clock signals ckg and / ckg in the first and second clock signal input control units constituting the SR, it is possible to reduce the load on the clock signal line and the power consumption.

FIG. 33 is a circuit diagram showing another example of the configuration of the scanning signal line drive circuit GD using the shift register circuit 11 or the shift register circuit 21. In FIG. In the main scanning signal line driving circuit GD, one of the shift register circuits 28
Stage latch circuit LS Start signal line SPG // SPG to SR
A normal level shifter circuit LS1 having a circuit configuration as shown in FIG. Further, a pulse width control signal line 29 similar to that of FIG. 41 is provided, and the above-described level shifter circuit LS2 is connected to the pulse width control signal line 29. Then, the same amplitude 5 as the clock signals ckg and / ckg is generated by the level shifter circuit LS1.
V start signal spg, / spg is boosted to 16V amplitude and the first stage latch circuit LS Supplies to SR. Further, the level shifter circuit LS2 boosts the pulse width control signals gps, / gps having the same amplitude of 5 V as the clock signals ckg, / ckg to 16 V and supplies the same to the NOR circuits 30 to 33 of the respective stages.

Therefore, by setting the amplitudes of the start signals spg and / spg and the pulse width control signals gps and / gps to 5 V, the amplitudes of all the digital input signals to the main scanning signal line driving circuit GD are set to 5 V. can do. That is, according to the present embodiment, the output level of the external signal generation circuit can be unified to 5 V, so that power consumption can be reduced and the system can be simplified.

The adjacent latch circuit LS The pulse width of the scanning signal gl can be set more optimally by generating the scanning signal gl by overlapping the series of SR output signals / n with the pulse width control signals gps and / gps.

In the present embodiment, the latch circuit LS constituting each data signal line drive circuit SD and each scan signal line drive circuit GD is used. The case has been described as an example where the control signal is generated using the output signal having the smaller pulse width among the output signals out and / out from the SR. However, in the present invention, an output signal having a wider pulse width may be used. However, in that case, the adjacent latch circuit LS as described above Although the time overlap that occurs in the control signal based on the output signal from the SR cannot be positively eliminated,
The effect of reducing the amplitude of the clock signal can be obtained.

As described above, the data signal line driving circuit SD and the scanning signal line driving circuit GD in the present embodiment
At least one of the data signal line driving circuit SD or the scanning signal line driving circuit of the liquid crystal display device as shown in FIG.
By using it as a GD, an image display device having both low power consumption and high display quality can be configured.

In particular, in the circuit configuration of the liquid crystal display device as shown in FIG. 37, the data signal line driving circuit SD and the scanning signal line driving circuit GD have the same length as the side of the screen (that is, the display area). Since the wirings are widely distributed over the range, the wiring length of the clock signals cks, ckg and the like is extremely long. Therefore, the wiring load capacity such as the clock wiring is large, and the effect of reducing the power consumption by reducing the amplitude of each signal is extremely large. Note that each latch circuit LS in FIG. It is also possible to omit the input of the inverted signals / cks, / sps among the clock signal and the start signal input to SR. Further, the inverted signal / gps among the pulse width control signals input to the respective NOR circuits 30 to 33 in FIG. 33 can be omitted.

FIG. 34 is a configuration diagram showing a liquid crystal display device which is an example of the image display device according to claim 30. This liquid crystal display device 41 includes a data signal line driving circuit SD shown in FIG. 28 or FIG. 30, and a scanning signal line driving circuit GD shown in FIG. 31 or FIG. Data signal line drive circuit
SD is the data signal line drive circuit shown in FIG. 28 or FIG.
It has the same circuit configuration as SD. Further, the scanning signal line driving circuit GD has the same circuit configuration as the scanning signal line driving circuit GD shown in FIG. 31 or FIG. Also, pixel array AR
Y is a pixel array ARY in the liquid crystal display device shown in FIG.
It has the same configuration as.

In the present liquid crystal display device 41, the pixel PIX
, A data signal line driving circuit SD, and a scanning signal line driving circuit GD
Are formed on the same substrate SUB and have a so-called driver monolithic structure. And the external control circuit
Video signal dat, clock signal cks, start signal s from CTL
It is driven according to ps, a clock signal ckg, a start signal spg, a pulse width control signal gps, and various driving power supplies from an external power supply circuit VGEN.

In such a circuit configuration, as in the case of the liquid crystal display device shown in FIG. 37, the wiring load capacitance is extremely large. By making the amplitude of each input signal to the circuits SD and GD smaller than the amplitude of the drive voltage of both signal line drive circuits SD and GD, it is possible to obtain a large effect of reducing power consumption.

By forming the data signal line drive circuit SD and the scan signal line drive circuit GD on the same substrate SUB as the pixel array ARY (monolithically), it is possible to form the data signal line drive circuit SD and the scan signal line drive circuit GD on a separate substrate. , Signal line drive circuit SD, GD
It is possible to reduce the manufacturing cost and the mounting cost, and also obtain the effect of improving the reliability.

In a monolithic liquid crystal display device as shown in FIG. 34, since a transparent substrate such as a quartz substrate or a glass substrate is used as the substrate SUB, a conventional active matrix type liquid crystal display device is used as an active element. A polycrystalline silicon thin film transistor having a characteristic that is much higher in driving force than an amorphous silicon thin film transistor used is used. FIG. 35 shows a structural example of the polycrystalline silicon thin film transistor. 49 is an insulating substrate such as a glass substrate, 50 is a silicon oxide film, 5
4 is a polycrystalline silicon film, 59a is a source region, and 59b is a drain region. Further, 55 is a silicon oxide film as a gate insulating film, 56 is a gate electrode, 63 is a silicon oxide film as an interlayer insulating film, and 65 is a metal wiring. FIG. 36 is a sectional view showing an example of a procedure for manufacturing the polycrystalline silicon thin film transistor. Hereinafter, a manufacturing process for forming a polycrystalline silicon thin film transistor at 600 ° C. or lower will be briefly described.

First, an amorphous silicon thin film 52 is deposited on a glass substrate 51 as shown in FIG. Then, as shown in FIG. 36C, an excimer laser 53 is irradiated to form a polycrystalline silicon thin film 54. Next, FIG.
After patterning the polycrystalline silicon thin film 54 into the shape of the active region as shown in FIG. 6D, a gate insulating film 55 made of silicon dioxide is formed on the upper surface as shown in FIG. Next, as shown in FIG.
The gate electrode 56 of the thin film transistor is formed on the substrate 5 from aluminum or the like.

After that, as shown in FIG.
The region of the n-type thin film transistor is covered with a resist 57, and an impurity “phosphorus 58” is implanted into the source and drain regions of the n-type thin film transistor using the gate electrode 56 as an irradiation mask. Thus, n ⁺ regions 59a and 59b are formed on both sides of gate electrode 56 in polycrystalline silicon thin film 54. Similarly, as shown in FIG. 36H, the region of the n-type thin film transistor is covered with a resist 60, and the impurity “shelf element 61” is implanted into the source and drain regions of the p-type thin film transistor using the gate electrode 56 as an irradiation mask. I do. Thus,
On both sides of the gate electrode 56 in the polycrystalline silicon thin film 54, p ⁺ regions 62a and 62b are formed. After that, FIG.
As shown in FIG. 7, an interlayer insulating film 63 made of silicon dioxide or silicon nitride is deposited. Then, FIG. 36 (j)
As shown in FIG. 36 (k), after opening contact holes 64 reaching n ⁺ regions 59a, 59b and p ⁺ regions 62a, 62b (that is, source and drain regions) in interlayer insulating film 63, Then, a metal wiring 65 such as aluminum is formed via the contact hole 64.

In the above-described manufacturing procedure, since the maximum temperature of the process is 600 ° C. when the gate insulating film 55 is formed, highly heat-resistant glass such as Corning 1737 glass can be used. Further, since the glass substrate can be formed at a temperature of 600 ° C. or lower, a glass substrate having a large area can be used at a low cost, so that the cost and the area of the liquid crystal display device can be reduced.

When the liquid crystal display device is formed, a transparent electrode (in the case of a transmissive liquid crystal display device) or a reflective electrode (in the case of a reflective liquid crystal display device) is further interposed via another interlayer insulating film. Is formed).

In the above description, a complementary type polycrystalline thin film transistor has been described as an example. However, the type is not limited to the complementary type. Furthermore, a forward stagger (top gate) using the polycrystalline silicon thin film 54 on the insulating substrate 49 (51) as the active layers 59a and 59b is taken as an example, but is not limited thereto. It may have another structure.

By using the above-described polycrystalline silicon thin film transistor as an active element, a scanning signal line driving circuit GD and a data signal line driving circuit SD having practical driving capabilities can be mounted on the same substrate as the pixel array ARY in FIG. It can be configured on the SUB with substantially the same manufacturing process.

Furthermore, since the polycrystalline silicon thin film transistor has a driving capability one or two digits smaller than that of a single crystal silicon transistor (MOS (metal oxide semiconductor) transistor), it operates at high speed like the data signal line driving circuit SD. In this case, it is necessary to increase the gate width in order to obtain the driving force. As a result, the gate capacitance also increases, and the clock signal lines and the like connected to the gates of hundreds of transistors become large loads, resulting in an increase in power consumption. However, according to the present embodiment, since the shift registers 11 and 21 using the low-amplitude clock signals ck and / ck as shown in FIG. 1 or FIG. 25 are used in the data signal line driving circuit SD, the clock signal line CL
It is possible to reduce the load on K and / CLK, thereby reducing power consumption.

The level shifter circuit shown in FIGS. 30 and 33 is provided by the polycrystalline silicon thin film transistor.
In the case where the LS is configured, compared with the case where the LS is configured by a single crystal transistor, the pulse duty change is large because the driving capability is small. However, according to the present embodiment, since the shift registers 11 and 21 as shown in FIG. 1 or FIG. 10 are used, the pulse widths of the sampling signals can be made uniform, and the time between adjacent sampling signals can be reduced. Can have no overlap. Therefore, deterioration of display quality can be suppressed.

The embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments.
Other configurations (image display devices other than liquid crystal display devices and the like) such as the combination of the above embodiments can be similarly applied.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a shift register circuit of the present invention.

FIG. 2 is a circuit configuration diagram illustrating an example of a latch circuit in FIG. 1;

FIG. 3 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 4 shows a clock signal, an input pulse signal,
FIG. 4 is a waveform diagram of an output signal and an output pulse signal of a clock signal input control unit.

FIG. 5 is a circuit configuration diagram illustrating an example of a latch circuit included in the shift register illustrated in FIG. 8;

FIG. 6 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 7 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 8 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 9 is a diagram illustrating an example of an AND-NOR circuit constituting the latch circuit of FIG. 8;

FIG. 10 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 11 is a diagram showing an example of an AND-NOR circuit constituting the latch circuit of FIG. 10;

FIG. 12 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 13 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 14 is a circuit configuration diagram showing another example of the latch circuit in FIG. 1;

FIG. 15 is a circuit diagram showing a modification of the latch circuit in FIG. 2;

FIG. 16 is a circuit diagram showing a modification of the latch circuit in FIG. 5;

FIG. 17 is a circuit diagram showing another modification of the latch circuit in FIG. 2;

FIG. 18 is a circuit diagram showing another modification of the latch circuit in FIG. 5;

19 is a diagram illustrating a circuit configuration example of a clock signal input control unit in FIG. 3;

20 is a diagram illustrating a circuit configuration example different from that of FIG. 19;

FIG. 21 is a diagram illustrating an example of a circuit configuration different from FIGS. 19 and 20;

FIG. 22 is a diagram illustrating an example of a circuit configuration different from FIGS. 19 to 21;

FIG. 23 is a circuit configuration diagram of a latch circuit different from that of FIG. 3;

24 is a waveform diagram of the clock signal, the input pulse signal, the output signal of the clock signal input control unit, and the output pulse signal in FIG.

FIG. 25 is a block diagram of a shift register circuit different from FIG. 1;

26 is a circuit configuration diagram of a latch circuit and an analog switch in FIG. 25.

FIG. 27 is a block diagram showing another example of the shift register circuit according to the present invention.

28 is a circuit configuration diagram of a data signal line driver circuit using the shift register circuit shown in FIG. 1 or FIG.

29 is a waveform diagram of a clock signal to the latch circuit, an output signal of the latch circuit, and a sampling signal in FIG. 26.

30 is a circuit configuration diagram of a data signal line driving circuit different from FIG. 28;

31 is a circuit configuration diagram of a scanning signal line driving circuit using the shift register circuit shown in FIG. 1 or FIG.

32 is a waveform diagram of a clock signal to the latch circuit, an output signal of the latch circuit, and a scanning signal in FIG.

FIG. 33 is a circuit configuration diagram of a scanning signal line driving circuit different from FIG. 31;

FIG. 34 is a schematic configuration diagram of a monolithic liquid crystal display device as an image display device of the present invention.

35 is a sectional view of a polycrystalline silicon thin film transistor used in the liquid crystal display device of FIG.

FIG. 36 is a view showing a procedure of manufacturing the polycrystalline silicon thin film transistor shown in FIG. 35.

FIG. 37 is a schematic configuration diagram of a liquid crystal display device of an active matrix drive system.

FIG. 38 is a detailed configuration diagram of a pixel in FIG. 37.

39 is a diagram showing a detailed circuit configuration of a data signal line driving circuit in FIG. 37.

40 is a waveform diagram of a clock signal to the latch circuit, an output signal of the latch circuit, and a sampling signal in FIG. 39.

FIG. 41 is a diagram showing a detailed circuit configuration of a scanning signal line driving circuit in FIG. 37;

42 is a waveform diagram of the clock signal to the latch circuit, the output signal of the latch circuit, the pulse width control signal, and the scanning signal in FIG. 41.

FIG. 43 is a circuit configuration diagram of the latch circuit in FIGS. 39 and 41.

FIG. 44 is a diagram showing a specific configuration example of the clocked inverter circuit in FIG. 43.

FIG. 45 is a circuit configuration diagram of a latch circuit capable of bidirectional scanning.

FIG. 46 is a circuit configuration diagram of a data signal line driving circuit equipped with a level shifter circuit.

FIG. 47 is a circuit configuration diagram of a scanning signal line driving circuit equipped with a level shifter circuit.

FIG. 48 is a specific circuit configuration diagram of the level shifter circuit in FIGS. 46 and 47.

FIG. 49 is a circuit configuration diagram of a level shifter circuit different from FIG. 48;

FIG. 50 is a waveform diagram of an input signal and an output signal in FIG. 48 or 49.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G09G 3/36 H03K 3/356 H03K 3/356 E 19/0185 19/00 101E (72) Inventor Ichiro Shiraki 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka, Japan (72) Inventor Kazuhiro Maeda 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka, Japan

Claims (36)

[Claims] 1. A latch circuit to which a pulse signal and a clock signal are input and which transmits the pulse signal in synchronization with the clock signal, wherein the amplitude of the clock signal or the pulse signal is a pulse output from the latch circuit. A latch circuit having a smaller amplitude than a signal. 2. The latch circuit according to claim 1, wherein
It further includes a first circuit having a voltage holding function and a second circuit having a level shift function, wherein the first and second circuits share some elements with each other. Latch circuit. 3. The latch circuit according to claim 2, wherein
A power supply potential is supplied to the latch circuit, and an element for controlling the voltage holding function or the level shift function of the input signal is provided between the power supply potential and the second circuit. A latch circuit characterized by the following. 4. The latch circuit according to claim 1, wherein
The latch circuit includes a first p-type transistor and a second p-type transistor each having a source electrode connected to a power supply potential and a gate electrode connected to each drain electrode, and a source electrode connected to the first p-type transistor. A first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor; and a source electrode connected to the second p-type transistor. A second n-type transistor having a drain electrode connected to a ground potential, a gate electrode connected to the drain electrode of the first p-type transistor, and a source electrode connected to the drain of the first p-type transistor. A third electrode connected to the electrode and receiving the pulse signal at the gate electrode; an n-type transistor, a fourth n-type transistor having a source electrode connected to the drain electrode of the third n-type transistor, a drain electrode connected to the ground potential, and a gate electrode to which the clock signal is input; A fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, a gate electrode receiving an inverted signal of the pulse signal, and a source electrode connected to the drain electrode of the fifth n-type transistor On the other hand, a drain electrode is connected to the ground potential, and a gate electrode is provided with a sixth n-type transistor to which the clock signal is input. The pulse signal is output from a drain electrode of the second p-type transistor, An inverted signal of the pulse signal is output from the drain electrode of the first p-type transistor A latch circuit. 5. The latch circuit according to claim 1, wherein
The latch circuit includes a first p-type transistor and a second p-type transistor each having a source electrode connected to a power supply potential and a gate electrode connected to each drain electrode, and a source electrode connected to the first p-type transistor. A first n-type transistor having a gate electrode connected to the drain electrode of the second p-type transistor, a source electrode connected to the drain electrode of the first n-type transistor, and a drain electrode connected to the ground potential. A seventh n-type transistor connected to the gate electrode and receiving an inverted signal of the clock signal; a source electrode connected to the drain electrode of the second p-type transistor; and a gate electrode connected to the drain electrode of the first p-type transistor. And a source electrode connected to the second n-type transistor. An eighth n-type transistor connected to the drain electrode of the transistor, the drain electrode being connected to the ground potential, and an inverted signal of the clock signal being input to the gate electrode; and a source electrode connected to the drain electrode of the first p-type transistor. And a third n-type transistor having the gate electrode receiving the pulse signal, a source electrode connected to the drain electrode of the third n-type transistor, and a drain electrode connected to the ground potential. A fourth n-type transistor whose gate electrode receives the clock signal; a fifth n-type transistor whose source electrode is connected to the drain electrode of the second p-type transistor and whose gate electrode receives an inverted signal of the pulse signal; A transistor and a source electrode connected to the drain electrode of the fifth n-type transistor. On the other hand, a drain electrode is connected to the ground potential, a gate electrode is provided with a sixth n-type transistor to which the clock signal is input, and the pulse signal is output from a drain electrode of the second p-type transistor; A latch circuit, wherein an inverted signal of the pulse signal is output from a drain electrode of the first p-type transistor. 6. The latch circuit according to claim 1, wherein
The latch circuit includes a first p-type transistor and a second p-type transistor each having a source electrode connected to a power supply potential and a gate electrode connected to each drain electrode, and a source electrode connected to the first p-type transistor. A first n-type transistor having a gate electrode connected to the drain electrode of the second p-type transistor, a source electrode connected to the drain electrode of the second p-type transistor, and a gate electrode connected to the first p-type transistor. A second n-type transistor connected to a drain electrode of the transistor, a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, and a gate electrode receiving the pulse signal; Connected to the drain electrode of the second p-type transistor, A fifth n-type transistor whose electrode receives an inverted signal of the pulse signal; a source electrode connected to the drain electrodes of the third and fifth n-type transistors; a drain electrode connected to the ground potential; A ninth n-type transistor whose gate electrode receives the clock signal; a source electrode connected to the drain electrodes of the first and second n-type transistors; a drain electrode connected to the ground potential; A 10 n-type transistor to which an inverted signal of the clock signal is input, wherein the pulse signal is output from the drain electrode of the second p-type transistor, and the pulse signal is inverted from the drain electrode of the first p-type transistor. A latch circuit, which outputs a signal. 7. The latch circuit according to claim 1, wherein
The latch circuit includes a first p-type transistor and a second p-type transistor each having a source electrode connected to a power supply potential and a gate electrode connected to each drain electrode, and a source electrode connected to the first p-type transistor. A first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor; and a source electrode connected to the second p-type transistor. A second n-type transistor having a drain electrode connected to a ground potential, a gate electrode connected to the drain electrode of the first p-type transistor, and a source electrode connected to the drain of the first p-type transistor. A third electrode connected to the electrode and receiving the pulse signal at the gate electrode; an n-type transistor, a fifth n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor, and a gate electrode receiving an inverted signal of the pulse signal; and a source electrode having the third and fifth n-type transistors. A ninth n-type transistor connected to the ground potential while the drain electrode is connected to the ground potential, and the gate electrode receiving the clock signal. Wherein the pulse signal is output from the first latch circuit, and an inverted signal of the pulse signal is output from the drain electrode of the first p-type transistor. 8. The latch circuit according to claim 1, wherein
The latch circuit includes first and second AND-NOR circuits. The inputs of the AND circuit portion of the first AND-NOR circuit are the clock signal and the pulse signal. ,
The inputs of the NOR circuit of the first AND-AND circuit are an output signal of the AND circuit and an output signal of the second AND-AND circuit, The input of the AND circuit of the AND-NOR circuit is the inverted signal of the clock signal and the pulse signal, and the input of the NOR circuit of the second AND-NOR circuit is A latch circuit comprising an output signal of the AND circuit and an output signal of the first AND-NOR circuit. 9. The latch circuit according to claim 8, wherein
In the above-described AND-NOR circuit, a first p-type transistor and a second p-type transistor each having a source electrode connected to a power supply potential and a gate electrode connected to each drain electrode, A first n-type transistor connected to the drain electrode of the first p-type transistor, the drain electrode of which is connected to the ground potential, and the output signal of the other AND-NOR circuit is input to the gate electrode; An eleventh n-type transistor having a source electrode connected to the drain electrode of the second p-type transistor and a gate electrode receiving an inverted signal of the clock signal; and a source electrode connected to the drain electrode of the first p-type transistor A third n-type transistor in which the pulse signal is input to the gate electrode; A fourth n-type transistor whose drain electrode is connected to the ground potential and whose gate electrode receives the clock signal, and a source electrode is connected to the drain electrode of the second p-type transistor. And a source connected to the drain electrodes of the eleventh and fifth n-type transistors while the drain electrode is connected to the ground. A twelfth n-type transistor connected to a potential and having a gate electrode to which an inverted signal of the output signal of the other logical product-negative-OR circuit is input; and a pulse from the drain electrode of the first p-type transistor. A signal is output and the pulse signal is inverted from the drain electrode of the second p-type transistor. A latch circuit, which outputs a signal. 10. The latch circuit according to claim 1, wherein said latch circuit comprises: a first NAND circuit to which said clock signal and said pulse signal are inputted; and an inverted signal of said clock signal and said pulse signal. A third NAND circuit to which an output signal of the first NAND circuit and an output signal of the fourth NAND circuit are input; A latch circuit comprising: an output signal of a second NAND circuit; and a fourth NAND circuit to which an output signal of the third NAND circuit is input. 11. The latch circuit according to claim 10, wherein said first and second NAND circuits each have a source electrode connected to a power supply potential and a gate electrode connected to a drain electrode. A first n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, a gate electrode receiving the pulse signal, and a source electrode connected to the source electrode. Is connected to the drain electrode of the third n-type transistor, while the drain electrode is connected to the ground potential and the gate electrode is supplied with the clock signal. The source electrode is connected to the second p-type transistor. The drain electrode of the transistor is connected to the ground potential while the drain electrode is connected to the ground potential. A 13th n-type transistor whose pole is supplied with an inverted signal of the pulse signal, a source electrode connected to the drain electrode of the second p-type transistor, a drain electrode connected to the ground potential, and a gate electrode A 14th n-type transistor to which an inverted signal of the clock signal is input;
A latch circuit, wherein an inverted signal of said output signal is output from a drain electrode of said second p-type transistor, respectively, as an output signal of said NAND circuit. 12. The latch circuit according to claim 1, wherein said latch circuit comprises a first and a second p-type transistors having a source electrode connected to a power supply potential.
A third and a fourth p-type transistor whose source electrode is connected to a drain electrode of the first and second p-type transistors, respectively, and whose gate electrode is connected to a clock signal; A third and a fifth n-type transistors connected to the drain electrodes of the third and fourth p-type transistors, respectively, and a gate electrode connected to the input pulse signal and the inverted signal of the input pulse signal; Fourth and sixth n-type transistors connected to the drain electrode of the third and fifth n-type transistors, the gate electrode is connected to the clock signal, and the drain electrode is connected to the ground potential; The gate electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors, and the gate electrodes are connected to the fourth and third p-type transistors. First and second n-type transistors each connected to the drain electrode of the transistor, and the drain electrode is connected to the ground potential. An output pulse is output from the drain electrode of the fourth p-type transistor. A latch circuit wherein an inverted signal of an output pulse is output from a drain electrode of a third p-type transistor. 13. The latch circuit according to claim 1, wherein said latch circuit comprises a first and a second p-type transistors having a source electrode connected to a power supply potential.
A third and a fourth p-type transistor whose source electrode is connected to a drain electrode of the first and second p-type transistors, respectively, and whose gate electrode is connected to a clock signal; A third and a fifth n-type transistors connected to the drain electrodes of the third and fourth p-type transistors, respectively, and a gate electrode connected to the input pulse signal and the inverted signal of the input pulse signal; Fourth and sixth n-type transistors connected to the drain electrode of the third and fifth n-type transistors, the gate electrode is connected to the clock signal, and the drain electrode is connected to the ground potential; The gate electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors, and the gate electrodes are connected to the fourth and third p-type transistors. First and second n-type transistors respectively connected to the drain electrode of the transistor, source electrodes are respectively connected to the drain electrodes of the first and second n-type transistors, and the gate electrode is used for an inverted signal of the clock signal. And a drain electrode of the fourth p-type transistor, wherein an output pulse is output from the drain electrode of the fourth p-type transistor, and the third p-type transistor is connected to the third p-type transistor. Wherein an inverted signal of the output pulse is output from the drain electrode of the latch circuit. 14. The latch circuit according to claim 1, wherein said latch circuit includes a first and a second p-type transistors having a source electrode connected to a power supply potential.
A third and a fourth p-type transistor whose source electrode is connected to a drain electrode of the first and second p-type transistors, respectively, and whose gate electrode is connected to a clock signal; A drain electrode of each of the first and second p-type transistors; a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal;
Fifth and sixth p-type transistors whose drain electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors, and source electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors. Third and fifth n-type transistors connected to each other and having a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal, respectively, and a source electrode connected to a drain electrode of the third and fifth n-type transistors, respectively. Fourth and sixth n-type transistors connected to each other, a gate electrode connected to a clock signal, and a drain electrode connected to the ground potential; and a source electrode connected to the drain electrodes of the third and fourth p-type transistors, respectively. And the gate electrode is connected to the drain electrode of each of the fourth and third p-type transistors, and the drain electrode is connected to the ground potential First and second n-type transistors connected to each other, an output pulse is output from the drain electrode of the fourth p-type transistor, and an inverted signal of the output pulse is output from the drain electrode of the third p-type transistor. Is output. 15. The latch circuit according to claim 1, wherein the first and second p-type transistors have their source electrodes connected to a power supply potential.
A third and a fourth p-type transistor whose source electrode is connected to a drain electrode of the first and second p-type transistors, respectively, and whose gate electrode is connected to a clock signal; A drain electrode of each of the first and second p-type transistors; a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal;
Fifth and sixth p-type transistors whose drain electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors, and source electrodes are respectively connected to the drain electrodes of the third and fourth p-type transistors. Third and fifth n-type transistors connected to each other and having a gate electrode connected to an input pulse signal and an inverted signal of the input pulse signal, respectively, and a source electrode connected to a drain electrode of the third and fifth n-type transistors, respectively. Fourth and sixth n-type transistors connected to each other, a gate electrode connected to a clock signal, and a drain electrode connected to the ground potential; and a source electrode connected to the drain electrodes of the third and fourth p-type transistors, respectively. And the first and second n-type transistors whose gate electrodes are connected to the drain electrodes of the fourth and third p-type transistors, respectively. A transistor and a source electrode are respectively connected to the drain electrodes of the first and second n-type transistors, a gate electrode is connected to an inverted signal of the clock signal, and a drain electrode is connected to the ground potential. Wherein an output pulse is output from the drain electrode of the fourth p-type transistor, and an inverted signal of the output pulse is output from the drain electrode of the third p-type transistor. Latch circuit. 16. The latch circuit according to claim 9, wherein said first, second, third, and fifth n-type transistors have a dual gate structure, and said fourth, sixth, seventh, and eighth n-type transistors have a single gate structure. A latch circuit characterized by the above-mentioned. 17. The latch circuit according to claim 9, wherein a channel length of said first, second, third and fifth n-type transistors is longer than a channel length of said fourth, sixth, seventh and eighth n-type transistors. A latch circuit characterized by the above-mentioned. 18. A shift register circuit having a plurality of latch circuits for transmitting a pulse signal in synchronization with a clock signal, wherein a clock signal input control for controlling input and stop of a clock signal supplied to each of the latch circuits. A shift register circuit, wherein the amplitude of the clock signal is smaller than the amplitude of the pulse signal. 19. The shift register circuit according to claim 18, wherein a clock signal input to each of said latch circuits is only one of a clock signal having a predetermined cycle and a signal having a phase opposite thereto. Shift register circuit. 20. The shift register circuit according to claim 18, wherein an output signal of each of the latch circuits is input to a subsequent latch circuit via a first transfer gate, and is also input to a second transfer gate via a second transfer gate. A shift register circuit, which is inputted to a preceding latch circuit and selectively conducts the first or second transfer gate by an external signal to control a scanning direction thereof. 21. The shift register circuit according to claim 18, wherein an output signal of each of the latch circuits is input to a subsequent latch circuit via a buffer circuit. 22. The shift register circuit according to claim 18, wherein the clock signal input control section comprises a first clock signal input control section and a second clock signal input control section, and the latch circuit comprises: A first p-type transistor and a second p-type transistor whose respective gate electrodes are connected to the respective drain electrodes while the source electrodes are connected to the power supply potential, and the source electrodes are connected to the drain electrodes of the first p-type transistors. On the other hand, a first n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the drain electrode of the second p-type transistor; and a source electrode connected to the drain electrode of the second p-type transistor. , The drain electrode is connected to the ground potential, and the gate electrode is connected to the gate of the first p-type transistor. A second n-type transistor connected to the in-electrode, a third n-type transistor having a source electrode connected to the drain electrode of the first p-type transistor, and a gate electrode connected to the pulse signal input node; A fourth n-type transistor having a drain electrode connected to the ground potential and a gate electrode connected to the first clock signal input control section, and a source electrode connected to the drain electrode of the third n-type transistor; A fifth n-type transistor connected to the drain electrode of the second p-type transistor and having a gate electrode connected to the inversion pulse signal input node; a source electrode connected to the drain electrode of the fifth n-type transistor; Is connected to the ground potential, and the gate electrode is connected to the second clock signal. A sixth n-type transistor connected to the force control unit, wherein the drain electrode of the second p-type transistor is a pulse signal output node, and the drain electrode of the first p-type transistor is an inverted pulse signal output node. Characteristic shift register circuit. 23. The shift register circuit according to claim 22, wherein the latch circuit has a first inverter having an input terminal connected to the inverted pulse signal output node, and an input terminal connected to the pulse signal output node. The second
A shift register circuit comprising an inverter, wherein the output terminal of the first inverter is a new pulse signal output node, and the output terminal of the second inverter is a new inverted pulse signal output node. 24. The shift register circuit according to claim 22, wherein the first clock signal input control unit is configured to connect a gate electrode of the fourth n-type transistor to a clock signal input node when the latch circuit is in an inactive state. The fourth n-type transistor electrically isolated from the clock signal input node; and a potential fixing means for fixing the potential of the gate electrode of the fourth n-type transistor to a predetermined potential. (2) a switching unit for electrically disconnecting the gate electrode of the sixth n-type transistor from the clock signal input node when the latch circuit is in an inactive state, and an electrical connection between the clock signal input node and the clock signal input node. A potential for fixing the potential of the gate electrode of the sixth n-type transistor cut off to a predetermined potential. Shift register circuit, characterized in that it is composed of a constant section. 25. The shift register circuit according to claim 24, wherein the switching means of the first clock signal input control unit has a source electrode connected to the clock signal input node and a drain electrode connected to the fourth n-type. The 15th n-type transistor connected to the gate electrode of the transistor and having the gate electrode connected to the pulse signal input node, wherein the switching means of the second clock signal input control unit includes a source electrode having the clock signal input node. While connected to the node, the drain electrode is connected to the gate electrode of the sixth n-type transistor, and the gate electrode is formed by a 16n-type transistor connected to the pulse signal output node. Shift register circuit. 26. The shift register circuit according to claim 24, wherein the potential fixing means of the first clock signal input control section has a source electrode connected to the gate electrode of the fourth n-type transistor and a drain electrode connected to the gate electrode of the fourth n-type transistor. The 17th n-type transistor connected to the ground potential and having a gate electrode connected to the power supply potential, wherein the potential fixing means of the second clock signal input control unit has a source electrode connected to the gate electrode of the sixth n-type transistor. Wherein the drain electrode is connected to the ground potential, and the gate electrode is formed of an 18th n-type transistor connected to the power supply potential. 27. The shift register circuit according to claim 24, wherein the potential fixing means of the first clock signal input control unit has a source electrode connected to a gate electrode of the fourth n-type transistor and a drain electrode connected to a gate electrode of the fourth n-type transistor. A first electrode connected to the ground potential and having a gate electrode connected to its own source electrode;
The second clock signal input control unit includes a source electrode connected to the gate electrode of the sixth n-type transistor, a drain electrode connected to the ground potential, and a gate electrode. A second electrode whose electrode is connected to its own source electrode
A shift register circuit including a 0n-type transistor. 28. The shift register circuit according to claim 24, wherein the potential fixing means of the first clock signal input control unit is provided between a gate electrode of the fourth n-type transistor and a ground potential. The second clock signal input control unit is configured with a second resistor interposed between a gate electrode of the sixth n-type transistor and a ground potential. A shift register circuit. 29. The shift register circuit according to claim 25, wherein the potential fixing means of the first clock signal input control unit has a source electrode connected to the gate electrode of the fourth n-type transistor and a drain electrode connected to the fourth n-type transistor. The potential fixing means of the second clock signal input control unit is connected to the ground potential and has a gate electrode connected to the inverted pulse signal input node. A shift register connected to the gate electrode of the transistor, the drain electrode being connected to the ground potential, and the gate electrode being constituted by a 22n-th transistor connected to the inverted pulse signal output node. circuit. 30. A matrix in which a plurality of data signal lines are arranged in a column direction, a plurality of scanning signal lines are arranged in a row direction, and one at a position surrounded by the data signal lines and the scanning signal lines. Active matrix image display having a plurality of pixels arranged in a matrix, a data signal line driving circuit for supplying a video signal to the data signal line, and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal line In the device, at least one of the data signal line driving circuit and the scanning signal line driving circuit is configured using the shift register circuit according to any one of claims 18 to 29. Image display device. 31. The image display device according to claim 30, wherein the one signal line drive circuit is configured using the shift register circuit according to claim 22, and configures the shift register circuit. A drive signal for driving a corresponding signal line is generated by using an output signal having a smaller pulse width among two output signals of a pulse signal and an inverted pulse signal from each latch circuit. Characteristic image display device. 32. The image display device according to claim 30, wherein the amplitude of a start signal having the same amplitude as that of the clock signal is amplified to be applied to a first-stage latch circuit in the shift register circuit of the one signal line driving circuit. An image display device comprising a level shifter circuit for supplying the pulse signal. 33. The image display device according to claim 30, further comprising: a level shifter circuit that amplifies an amplitude of a control signal having the same amplitude as the clock signal and supplies the amplified control signal to the one signal line driving circuit. Characteristic image display device. 34. The image display device according to claim 30, wherein said one signal line drive circuit is formed on the same substrate as said pixels. 35. The image display device according to claim 34, wherein the one of the signal line driving circuits and the active elements forming the pixels are polycrystalline silicon thin film transistors. 36. The image display device according to claim 35, wherein said polycrystalline silicon thin film transistor is formed on a glass substrate by a process at 600 ° C. or lower.