JP2000184385A - Solid-state image pickup element, its drive method and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup element where an electric signal is optionally compressed in a vertical direction and a horizontal output data rate can be compressed and that has provision for a moving picture, a still picture with balanced resolution and for a progressive operation, to provide its drive method and a camera system. SOLUTION: In a plurality of sensor sections 11 that are placed in a matrix, signal charges of the sensor section group placed at an interval of one row, e.g. on an odd row are read by a vertical CCD 12o placed at an interval of one column, e.g. on an odd number column and signal charges of the sensor section group placed at an interval of one row, e.g. on an even row are read by ea vertical CCD 12e placed at an interval of one column, e.g. on an even number column, and signal charges of two pixels adjacent in a column direction are summed by the same vertical CCD 12o, 12e and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor, a method of driving the same, and a camera system, and more particularly to a color solid-state image sensor which can be used for both still images and moving images, a method of driving the same, and imaging of the solid-state image sensor. It relates to a camera system used as a device.

[0002]

2. Description of the Related Art In recent years, with the expectation of mounting a still function on a video camera, development of a solid-state imaging device that can be used for both still images and moving images has been advanced. Generally, it is considered that a still image is based on a square lattice and a moving image is based on 13.5 MHz. Therefore, in order to use both of them, interpolation / compression is required by either method. Here, while the still image is in the high-pixel non-format, the moving image is NTSC /
Because the broadcasting method such as PAL is required, down conversion from a high-resolution still image solid-state imaging device
Producing television signals such as NTSC / PAL is considered most efficient.

When a method of cutting out the central area of an effective pixel area such as camera shake correction is used as a method of down conversion, if the broadcast method is cut out at a high number of pixels, the angle of view between a still image and a moving image changes. Becomes large, and a lot of pixel information is discarded, resulting in poor efficiency.
For this reason, as a method of down-conversion, a method of performing a vertical compression process of a still image / moving image by mixing (vertical addition) in a transfer process of signal charges has conventionally been adopted.

In order to execute the vertical compression process in the process of transferring the signal charges, color coding of a color filter is the biggest problem. That is, the primary colors R (red), G
In the case of (green) and B (blue), it is safe to perform vertical addition as vertical stripes, whereas complementary colors are C (cyan) and
Y (yellow), G (green), M (magenta) 4
The use of vertical stripes is disadvantageous in terms of color resolution in the horizontal direction. Therefore, a technique of shift addition by the horizontal transfer unit (hereinafter, referred to as horizontal shift addition) is employed to keep the horizontal drive frequency constant.

However, C, Y, G, and M are, for example, those shown in FIG.
In the complementary color checker color coding arranged as shown in FIG. 2, in order to cope with the interlace operation, the color difference signal Cr obtained by mixing signal charges of two pixels in the vertical direction (hereinafter, referred to as vertical two-pixel mixing). (G
+ C, M + Y) and Cb (M + C, G + Y) are line sequential obtained alternately in the vertical direction.
Vertical mixing while maintaining b was not possible. In addition,
In FIG. 17, an odd number (ODD) field is on the left side,
The right side shows the even (EVEN) fields.

On the other hand, complementary color coding as shown in FIG. 18 has been proposed for realizing vertical mixing and horizontal shift addition (literature; 1997 Annual Meeting of the Institute of Image Information and Television Engineers (ITE). '97: 1997 ITE Ann
ual Convention) "Study on Single-Chip Color Imaging with Hi-Vision / NTSC Output" pp. 37-38). According to the complementary color coding, as is apparent from FIG. 18, the color difference signals Cr (G + C, M + Y) and Cb (M + C,
G + Y) in a quincunx shape.

As described above, in the conventional complementary color coding in which the color difference signals Cr and Cb are arranged in a quincunx pattern, as shown in FIG. Charge during horizontal blanking period
After shifting the bit (for two pixels), the signal charges of the next one line are line-shifted, whereby signals of the same color component can be vertically mixed. That is, the color difference signal C
Vertical mixing can be realized while maintaining r and Cb.

[0008]

However, the color difference signals Cr and Cb are arranged in a quincunx pattern, that is, the color difference signals Cr and Cb.
In the case of complementary color coding in which b is alternately obtained in the horizontal direction and the vertical direction, as described above, vertical mixing with a horizontal 2-bit shift, that is, addition of signals of the same color component separated by two pixels, Since the vertical compression processing is realized, there is a problem that the color resolution in the horizontal direction is reduced to the same degree (ie, 水平) as the horizontal four repetition coding compared to the normal horizontal two repetition coding.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a moving picture, which can perform arbitrary vertical compression and horizontal output data rate compression and has a balanced resolution. An object of the present invention is to provide a solid-state imaging device capable of coping with a still image and a progressive operation, a driving method thereof, and a camera system.

[0010]

According to the present invention, there is provided a solid-state image pickup device comprising a plurality of sensor units arranged in a matrix and a first transfer unit arranged every other row for the plurality of sensor units. A vertical transfer unit including a second transfer unit group arranged every other unit and every other column; and a plurality of sensor units.
A first drive system for reading each signal charge of the sensor unit group located in every other row to a first transfer unit group and reading each signal charge of the sensor unit group located in another every other row to a second transfer unit group; And a second drive system for adding the signal charges of two pixels adjacent in the column direction read from the plurality of sensor units in each of the first and second transfer unit groups. .

In the solid-state imaging device and the method of driving the same, each signal charge of a group of sensor units located in every other row (for example, odd-numbered row) among the plurality of sensor units is arranged in every other row (for example, odd-numbered row). Each signal charge of the sensor unit group located in every other row (for example, even-numbered row) is placed in the first transfer unit group arranged for every other row (for example, even-numbered row). 2 is read out to each of the transfer units. As a result, signal charges of two pixels adjacent in the column direction are read out to the same transfer unit. Then, the signal charges of the two pixels are added in the transfer section.

Another solid-state image pickup device according to the present invention has a plurality of sensor units arranged in a matrix, and is arranged corresponding to each of the plurality of sensor units. From a color filter of color coding repeated for each pixel, a first transfer unit group arranged every other row for a plurality of sensor units, and a second transfer unit group arranged every other row for the plurality of sensor units Vertical transfer unit, and among the plurality of sensor units, each signal charge of a sensor unit group located on every other row is assigned to a first transfer unit group, and each signal charge of a sensor unit group located on every other row is assigned to a first transfer unit group. The second transfer unit group has a drive system for reading.

In another solid-state image pickup device having the above-described structure and a method of driving the same, each signal charge of a group of sensor units located in every other row (for example, an odd-numbered row) among the plurality of sensor units is arranged in every other row (for example, an odd-numbered row). Each signal charge of the sensor unit group located in every other row (for example, even-numbered row) is arranged in every other row (for example, even-numbered row) in the first transfer unit group arranged for every other row. And read them out to the second transfer unit group. At this time, since the color filter has a color coding in which the same color is repeated every two pixels in the row direction, signal charges of the same color are read out to the same transfer unit.

In the camera system according to the present invention, among the plurality of sensor units arranged in a matrix, each signal charge of the sensor unit group located in every other row is arranged in every other column.
Each of the first and second transfer unit groups reads out the signal charges of the sensor unit groups located in every other row into the second transfer unit group arranged in every other column. In the above, a solid-state imaging device capable of adding and outputting signal charges of two pixels adjacent in a column direction read from a plurality of sensor units and using the added signal is used as an imaging device. Then, an imaging mode setting unit that can selectively set a still image mode and a moving image mode with respect to the solid-state imaging device, and the solid-state imaging device is driven according to the imaging mode set by the imaging mode setting unit. A driving unit and a signal processing unit for processing an output signal of the solid-state imaging device are provided.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, a CCD image sensor (hereinafter, referred to as a CCD image sensor)
However, the present invention is not limited to this, and can be applied to all solid-state imaging devices having a structure in which signal charges read from pixels are vertically transferred in a horizontal direction.

FIG. 1 shows a CC according to a first embodiment of the present invention.
FIG. 1 is a schematic configuration diagram illustrating a D imaging device, and illustrates an example in which the invention is applied to a single-chip color CCD imaging device of an IS (interlace scan)-(interline transfer) system, for example.

In FIG. 1, a CCD imaging device 10 according to this embodiment includes a plurality of sensor units (pixels) 11 arranged in a matrix, and a plurality of vertical units arranged for each vertical column of the sensor units 11. CCD (vertical transfer unit) 12, sensor unit 11
Read gate unit 1 interposed between the vertical CCD 12
3. Horizontal CC arranged on one end side of vertical CCD 12
D (horizontal transfer unit) 14, a charge detection unit 16 and an output circuit 17 arranged at an end on the transfer destination side of the horizontal CCD 14.

On the imaging area (pixel area) 18 of the CCD imaging device 10, for example, a color filter 19 of complementary color checkerboard color coding is arranged. In this color filter 19, as shown in FIG.
/ C / G / Y, even-numbered rows are G / Y / M / C color coding, that is, the same color is repeated every four pixels in the horizontal direction (column direction) and every two pixels in the vertical direction (column direction) The color coding is repeated four times horizontally and two times vertically.

In the CCD image pickup device 10 having such a configuration, the sensor section 11 is composed of, for example, a PN-junction photodiode, and photoelectrically converts incident light into a signal charge having a charge amount corresponding to the light amount and stores the signal charge. For a plurality of sensor units 11 arranged in a matrix, every other row, for example, an odd number (OD
D) A vertical CCD 12o is arranged for each column, and a vertical CCD 12e is arranged for each other column, for example, for each even (EVEN) column.
Is arranged.

The read gate unit 13 receives, for example, a read pulse XSG described later, and as an example,
The signal charges of the sensor units located in every other row, for example, the sensor units 11 in the odd rows are applied to the vertical CCDs 12o in the odd columns, and the signal charges of the sensor units located in the other rows, for example, the sensor units 11 in the even rows are even-numbered. The structure is such that the data is read out to the vertical CCDs 12e in the column. The specific configuration of the read gate unit 13 will be described later.

The vertical CCD 12, for example, has four phases of vertical transfer clocks Vφ1 to Vφ shown in the timing chart of FIG.
The transfer is carried out by 4, and during a part of the horizontal blanking period, the signal charges corresponding to one scanning line (one line) are vertically transferred (line-shifted) as a unit and transferred to the horizontal CCD 14.

The horizontal CCD 14, for example, has two-phase horizontal transfer clocks Hφ1 and Hφ shown in the timing chart of FIG.
2 and driven by the vertical CCD 12
The signal charges corresponding to one scanning line line-shifted from are sequentially horizontally transferred in the horizontal scanning period after the horizontal blanking period and supplied to the charge detection unit 16. This horizontal C
The operation of the CD 14 is a transfer operation in the normal mode.

The charge detecting section 16 is constituted by, for example, a floating diffusion amplifier.
In other words, the horizontal CCD 14 includes a floating diffusion FD into which signal charges are injected, a reset drain RD from which charges are discharged, and a reset gate RG disposed between the floating diffusion FD and the reset drain RD. The supplied signal charge is detected and converted to a signal voltage. A predetermined reset drain voltage VRD is applied to the reset drain RD152.

FIG. 4 is a plan pattern diagram showing an example of a specific configuration of the sensor section 11, the vertical CCD 12, and the read gate section 13. In FIG. 4, the vertical CCD 12
The transfer channels 21o and 21e extend in parallel in the vertical direction and are alternately arranged in the horizontal direction, and are sequentially arranged in the vertical direction above the transfer channels 21o and 21e and extend in parallel in the horizontal direction. Existing 4-phase vertical transfer clock V
It has a configuration having transfer electrodes 22-1 to 22-4 corresponding to φ1 to Vφ4. The transfer electrodes 22-1 to 22-4 are 2
The line (two vertical pixels) is formed as one unit.

In these transfer electrodes 22-1 to 22-4, for example, the second-phase and fourth-phase vertical transfer clocks Vφ
2, the transfer electrodes 22-2 and 22-4 to which Vφ4 is applied are formed by the first layer of polysilicon (indicated by a dashed line in the figure), and the first and third phase vertical transfer clocks Vφ1 and Vφ
The transfer electrodes 22-1 and 22-3 to which φ3 is applied are formed of a second-layer polysilicon (indicated by a two-dot chain line in the figure). The transfer electrodes 22-2 and 22-4 made of the first-layer polysilicon and the transfer electrodes 22-1 and 22-3 made of the second-layer polysilicon are connected to the transfer channels 21o and 21-2.
On e, it is formed in a sawtooth shape and overlaps with each other at a substantially central portion of the sensor unit 11.

Here, as shown by hatching in FIG. 4, a part of the sensor section 11o of every other row (odd row in this example) on the side of the transfer channel 21o of the odd column is surrounded by hatching in FIG. Except for each other row (in this example, even-numbered row) of each sensor section 11e, a channel stop section 23 for element isolation is formed except for a part on the transfer channel 21e side of an even-numbered column. On the other hand, the transfer electrodes 22-1 to 22-4 are connected to the transfer channels 21o,
By being formed wide not only on 21 e but also on the opening edge of the sensor section 11, the portion where the channel stop section 23 is not formed also serves as the gate electrode of the readout gate section 13.

On the other hand, the four-phase vertical transfer clocks Vφ1 to Vφ4 applied to the transfer electrodes 22-1 to 22-4 are set to take three values of a low level, an intermediate level and a high level. The third high-level pulse becomes the read pulse XSG. Then, this read pulse XS
When G is applied to the readout gate unit 13 through each of the transfer electrodes 22-1 to 22-4, the signal charge is read out from each of the sensor units 11.

More specifically, the first phase vertical transfer clock V
When the read pulse XSG rises at φ1, the signal charges of the sensor units 11e in every other column of the even rows are read to the vertical CCDs 12e of the even columns as indicated by the arrow in the left direction. When the read pulse XSG rises in the second-phase vertical transfer clock Vφ2, the signal charge of each sensor unit 11o in every other column of the odd-numbered row is read out to the vertical CCD 12o of the odd-numbered column as indicated by the rightward arrow.

When the read pulse XSG rises in the third-phase vertical transfer clock Vφ3, the signal charges of the sensor units 11o in every other column of the odd-numbered row are changed to the vertical position of the odd-numbered column as indicated by the leftward arrow. It is read by the CCD 12o.
Read pulse XS is applied to the fourth phase vertical transfer clock Vφ4.
When G rises, the signal charges of the other sensor units 11e in the other rows of the even rows are read out to the vertical CCDs 12e of the even columns as indicated by the rightward arrow.

As described above, according to the pixel structure shown in FIG. 4, the signal charges of the four types of pixels of the odd-row / odd-column, even-row / even-column, odd-row / even-column, and even-row / odd-column are independent of each other. And can be read. In addition, this independent read is
One of the features is that it can be realized by the phase vertical transfer clocks Vφ1 to Vφ4-4 terminals, and in this respect, it is the same as the conventional pixel structure.

Further, since the right reading of the signal charge is performed by the first-layer polysilicon (Vφ2, Vφ4) and the left reading is performed by the second-layer polysilicon (Vφ1, Vφ3), for example, If there is a difference between the voltages of the read pulse XSG and the read pulse XSG due to some problem of the manufacturing apparatus, for example, the gate length of the read gate is changed only on the read side of the second-layer polysilicon, or the potential of the sensor section is changed. By changing the voltage, the voltage of the read pulse XSG can be balanced.

The above-mentioned sensor unit 11 and the vertical CCD
The configuration of the read gate 12 and the read gate unit 13 is merely an example, and is not limited thereto.
For example, the configuration disclosed in Japanese Patent Application Laid-Open No. 59012, the first vertical CCD group arranged in every other column with the signal charges of the sensor groups arranged in every other row, and the sensor sections arranged in every other row. Any configuration is possible as long as each signal charge of the group is read out to the second vertical CCD group arranged every other column.

As described above, in the CCD image pickup device 10 having the color filter 19 of two vertical repetition color codings, the first vertical CCD group (in this example, odd-numbered columns in the present example) in which the vertical CCDs 12 are arranged every other column. Vertical C
A set of CDs 12o) and a second group of vertical CCDs (an even number of vertical CCDs 12 in this example) arranged every other row.
e), the signal charges of the sensor unit group (in this example, the set of the sensor units 11o in the odd rows) located in every other row are read out to the vertical CCDs 12o in the odd columns, and are located in every other row. The signal charges of the sensor unit group (in this example, the set of the even-numbered sensor units 11e) are transferred to the even-column vertical CCDs 12e.
The signal charges for two horizontal pixels can be mixed and output in the vertical CCDs 12o and 12e.

This horizontal two-pixel mixing forms a so-called line-sequential arrangement in which the color difference (chroma) signals Cr and Cb are sequentially arranged in the vertical direction. Here, the relationship between the complementary color coding and the color difference signals Cr and Cb will be described using the general complementary color coding shown in FIG. 5 as an example.

Normally, since the CCD image pickup device performs field reading, a1 and a2 are used in the first field.
The signal charges are mixed by a combination of two vertical pixels. Accordingly, the order of signal charges transferred by the horizontal CCD is (G + Cy), (Mg +
Ye), (G + Cy), (Mg + Ye),.
In the second field, a combination of two vertical pixels b is used.

In order to convert the signal charges output in this order into electric signals and process them in a subsequent color signal processing system to form a luminance signal Y and color difference signals Cr and Cb, the Y signals are adjacent to each other. To reduce the color difference signals Cr and Cb. That is, an approximate signal of Y signal = | (G + Cy) + (Mg + Ye) | × 1/2 = 1/2 (2B + 3G + 2R) is used as the Y signal. As the color difference signal Cr, an approximate signal of Cr = (Mg + Ye)-(G + Cy) is used.

Next, considering the line a2, the horizontal CCD
From (Mg + Cy), (G + Ye), (Mg + C
y), (G + Ye),..., so that the Y signal is composed as follows: Y signal = | (G + Ye) + (Mg + Cy) | × 1/2 = 1/2 (2B + 3G + 2R) , A1 line and balance. Similarly, the color difference signal Cb is approximated by Cb = (G + Ye)-(Mg + Cy). The same applies to the second field.

On the other hand, the CCD image pickup device 1 according to this embodiment
0, field reading is performed for the complementary color coding of two vertical repetitions shown in FIG.
By performing horizontal two-pixel mixing in D12o and 12e, the horizontal CCD 14 outputs signals from each of the lines a1, a2, a3, a4,..., M + C, Y + M , as is apparent from the operation explanatory diagram of FIG. , G + Y, C + G , M +
The signal charges are output in the order of C, Y + M , G + Y, C + G ,.

The color difference signal Cr is underlined.
Are not underlined, respectively, and represent the color difference signals Cb. Here, Mg is M, Cy is C, and Ye is Y
The same applies to the following description. In this way, by performing horizontal two-pixel mixing for complementary color coding of two vertical repetitions, the color difference signals Cr,
Cb is output in line-sequential arrangement and dot-sequential.

In a subsequent color signal processing system (not shown), the color difference signals Cr,
Cb is separated into odd bits and even bits, and the signals of the odd and even rows are independently processed to obtain a luminance signal Y and a color difference signal Cr / Cb. Since the luminance signal Y for one minute can be obtained, the same progressive (PS) operation as that in which the signal charges of all the pixels are read out independently can be performed.

Further, since the luminance signals are alternately arranged for each line, a high horizontal resolution can be obtained and the vertical / horizontal resolution is well-balanced despite the horizontal two-pixel mixture. Further, the vertical CCD 12o, 1
Since only the same color exists in each of 2e, addition compression can be easily performed in the vertical direction, and the frame rate can be increased. The addition compression in the vertical direction can be realized by performing a vertical transfer (line shift) operation for two lines or more in the horizontal CCD 14 with the horizontal transfer operation stopped.

As described above, one vertical CCD 12 (12o / 1
2e), sensor parts 11 on both sides (11o / 11e)
Of the field readout which reads out the signal charges from the vertical CCD 12 and mixes two horizontal pixels in the vertical CCD 12 as an example. Next, one vertical CCD 12 (12
o / 12e), the sensor unit 11 on one side (11o / 1
The case of reading out a frame from only 1e) will be described.

In the case of field reading, FIG.
As is clear from the description based on the above, by setting a read pulse XSG to each of the four-phase vertical transfer clocks Vφ1 to Vφ4, it is possible to read signal charges from the sensor units 11 on both sides to one vertical CCD 12. ing.

On the other hand, in the case of frame reading, a read pulse XSG is raised only for the second and fourth phase vertical transfer clocks Vφ2 and Vφ4 in FIG. The signal charges can be read out only from the sensor units 11 of the odd rows and the odd columns and the even rows and the even columns, that is, only in the right direction (→) in the figure.
The first and third phase vertical transfer clocks Vφ1 and Vφ
3, the readout pulse XSG is applied only to the vertical CCD 12, so that signal charges are supplied to the single vertical CCD 12 only from the sensor units 11 in the odd-numbered and even-numbered columns and the even-numbered and odd-numbered columns, that is, only in the leftward direction (←) in FIG. Can be read.

As described above, with respect to the complementary color coding of two vertical repetitions, in the first field, the frame read is performed by setting the read pulse XSG to the vertical transfer clocks Vφ2 and Vφ4 of the second and fourth phases. Thus, from the horizontal CCD 14, as is apparent from the operation explanatory diagram of FIG. 7, each line a1, a2, a3, a
, M, Y, G, C, M, Y, G,
The signal charges are output in the order of C, M,.

In the second field, the first phase, 3
The frame reading is performed by setting the read pulse XSG to the vertical transfer clocks Vφ1 and Vφ3 of the phase, and the horizontal CCD 14 outputs the lines b1, b2, b3,. , Signal charges are output in the order of..., G, C, M, Y, G, C, M, Y, G,.

As is apparent from the above, since the M / Y / G / C-independent signal charges can be obtained in one field by reading the frame, the luminance signal Y is obtained by the signal processing in the subsequent color signal processing system. And the color difference signals Cr and Cb can be synthesized. In addition, as in the case of field reading, since only the same color exists in each of the vertical CCDs 12, the frame rate can be increased by performing the addition compression in the vertical direction.

After adding signal charges for, for example, two vertical pixels in the horizontal CCD 14, the horizontal CCD 14
The horizontal CCD 14 is driven by performing a bit shift (transfer by one stage) and adding signal charges for two pixels.
From, 2G + 2C , 2C + 2M, 2M + 2Y , 2
Y + 2G, 2G + 2C , 2C + 2M, 2M + 2Y , 2Y
Signal charges are output in the order of + 2G,. Here, the underlined line indicates the color difference signal Cr, and the underlined line indicates the color difference signal Cb.

As described above, even in the case of frame reading, by performing addition and compression processing of signal charges for a total of four pixels, that is, two pixels each for vertical / horizontal, the color difference signal Cr is obtained in the same manner as in field reading. , Cb are output in dot sequence. Thereby, the same signal processing as that at the time of field reading can be performed.

The vertical CCD 12 and the horizontal CCD 1
In the case of performing the addition compression by 4 or the like, if the number of additions (the number of pixels to be added) increases, the signal charge amount exceeds the charge amount handled by each transfer stage of the vertical CCD 12 and the horizontal CCD 14 and overflows. Since this results in leakage to the transfer stage, there is a limit to the improvement of the compression ratio.

On the other hand, in the case of frame reading, the reading of signal charges from the sensor section 12 is halved, and the amount of information is halved, so that double addition compression is possible. There is an advantage that a higher compression ratio can be realized. In this case, it is appropriate that the vertical CCD 12 is based on a mixture of two pixels and the horizontal CCD 14 is based on a mixture of four pixels to optimize the amount of charge to be handled.

FIG. 9 shows a CC according to a second embodiment of the present invention.
FIG. 3 is a schematic configuration diagram illustrating a D image pickup device, as in the first embodiment, showing an example in which the present invention is applied to an IS-IT single-chip color CCD image pickup device.

In FIG. 9, a CCD image pickup device 30 according to the present embodiment has a plurality of sensor units 3 arranged in a matrix.
1. A plurality of vertical CCDs 32 arranged for each vertical column of the sensor units 31, a read gate unit 33 interposed between the sensor units 31 and the vertical CCDs 32, and a horizontal unit arranged on one end side of the vertical CCDs 32. CCD34, horizontal CCD3
In addition to the components of the charge detection unit 36 and the output circuit 37 disposed at the end on the transfer destination side of No. 4, a hold gate unit 35o, provided between the vertical CCD 32 and the horizontal CCD 34 (vertical output gate unit). 35e. The hold gate units 35o and 35e are used to obtain an arbitrary compression ratio.

In the CCD imaging device 30 having the above configuration,
On the imaging area (pixel area) 38, for example, four horizontal repetitions shown in FIG.
A color filter of complementary color checkerboard color coding of two vertical repetitions is provided. Also, the sensor unit 31, the vertical CCD
The specific configuration of the read gate 32 and the read gate unit 33 is also the configuration shown in the plan pattern diagram of FIG. 4, but is not limited to this configuration, which is the same as in the previous embodiment. .

FIG. 10 shows the hold gate sections 35o, 35
FIG. 14 is a plan pattern diagram illustrating an example of a specific configuration of a vertical output gate section including an e. Here, the vertical CCDs 32o, 3
As for 2e, as described in the previous embodiment with reference to FIG. 4, a plurality of transfer channels 21 extending in parallel in the vertical direction, and sequentially arranged vertically above these transfer channels 21 in the vertical direction, and Transfer electrodes 22 corresponding to four-phase vertical transfer clocks Vφ1 to Vφ4 extending in parallel in the horizontal direction
-1 to 22-4.

On the other hand, the horizontal CCD 34 extends in the horizontal direction and has a plurality of transfer channels 21o,
21e, and transfer electrodes 4 corresponding to the two-phase horizontal transfer clocks Hφ1 and Hφ2 sequentially arranged in a horizontal direction above the transfer channel 41.
2-1 to 42-4. The transfer electrodes 42-1 and 42-2 are connected to the horizontal transfer clock H of the second phase.
φ2 is applied, and the first phase horizontal transfer clock Hφ1 is applied to the transfer electrodes 42-3 and 42-4.

In these transfer electrodes 42-1 to 42-4, the transfer electrodes 42-1 and 42-3 are formed of the first layer of polysilicon to form a storage section.
-2 and 42-4 are formed by the second layer of polysilicon to form the storage section. Further, the transfer electrodes 42-3,
42-4, transfer channels 21o, 21 of the vertical CCD 32
e. And especially, the transfer electrode 42
-4 has a shape bent in an inverted L-shape.

The hold gate portions 35o and 35e are independently provided above the storage electrodes 43 extending in the horizontal direction similarly to the transfer electrodes 22-1 to 22-2 of the vertical CCDs 32o and 32e, and above the transfer channels 21o and 21e. And the hold electrodes 44o and 44e. The storage electrode 43 has a vertical C
It is formed so as to overlap with the transfer electrodes 22-4 of the CDs 32o and 32e. Hold electrodes 44o, 44
e is a storage electrode 4 made of first layer polysilicon.
3 and the transfer electrode 42-4 of the horizontal CCD 34.

In the hold gate sections 35o and 35e, a predetermined DC voltage is applied to the common storage electrode 43 as a storage voltage VStorage. On the other hand, the hold electrodes 44o and 44e have the hold voltage V
φHold1,2 are given separately. That is, a hold voltage VφHold1 is given to the hold electrode 44o by drawing out the wiring as shown by a dotted line in the figure, and a hold voltage VφHold2 is given to the hold electrode 44e by drawing out the wiring similarly.

As the hold voltages VφHold1 and VφHold1, the “H” level is applied in both the normal operation mode and the “L” level / “H” level is appropriately applied in the compression mode for obtaining an arbitrary compression ratio. FIG.
3 shows a potential distribution in a cross section taken along line XX ′ of FIG. As is clear from this potential distribution diagram, the potential below the storage electrode 43 is in a deep state.
On the other hand, when the “H” level is applied, the hold electrode 4
4o (44e) is the potential of the storage electrode 43.
It is set to be deeper than the potential below.

When the hold voltage VφHold1 is at the “H” level, the potential below the hold electrode 44o is in a deep state, so that the signal charges transferred by the vertical CCD 32o pass through the hold gate section 35o as it is. Is transferred to the horizontal CCD. On the other hand, when the hold voltage VφHold1 is at the “L” level, the potential under the hold electrode 44o is in a shallow state, so that the potential barrier causes the vertical CC.
The transfer of the signal charges from D32o to the horizontal CCD 34 is blocked, and the blocked signal charges accumulate below the storage electrode 26.

The hold gate sections 35o and 35e are not limited to those having the above-described configuration, but the point is that the transfer of signal charges from the vertical CCD 32 to the horizontal CCD 34 can be controlled for each column. Is fine.

If necessary, the hold gate unit 3
An overflow gate and an overflow drain (charge discharging portion) can be provided adjacent to 5o and 35e. According to this, when the transfer-prevented signal charge exceeds a predetermined amount, the signal charge is discharged from the overflow gate to the overflow drain, so that overflow to the adjacent transfer channel can be prevented.

Next, the vertical output gate section (VO
The operation in the compression mode for obtaining an arbitrary compression ratio in the CCD imaging device 30 according to the present embodiment having G) will be described.

First, the operation in the compression mode when vertical 2: 3 addition-1 / 1.25 compression is performed will be described with reference to the operation explanatory diagram of FIG.

Here, in each of the pixels M, C, G, and Y, the subscript x represents the row number, and the subscript y represents the column number. For example, M89 represents a magenta pixel in the 8th row and 9th column. Bo represents a portion of the odd-numbered row of the hold electrodes 44o (hereinafter, referred to as a block portion Bo) as Be.
Indicates a portion of the hold electrode 44e in an even-numbered row (hereinafter, referred to as a block portion Be). Further, St indicates a portion of the storage electrode 43 (hereinafter, referred to as a storage portion St), and D indicates an overflow drain.

The signal charges are read out from the sensor unit 31 to the vertical CCD 32, and one line transfer is performed in a state where two horizontal pixels are mixed. At the time of this one-line transfer, the hold voltages VφHold1 and VφHold2 are set to the “L” level so that the block portions Bo and Be are both in the transfer blocking state, so that + G11 , M
21 + C22, Y12 + M13 , G23 + Y24, C1
4 + G15 , M25 + C26, Y16 + M17 , G27
+ Y28, C18 + G19 , and M29 + are accumulated. Here, the color difference signal Cr is underlined,
The color difference signals Cb are not underlined.

As described above, the vertical CCD is
The signal charge is read out to block 32, and the block B
Both o and Be are in the transfer blocking state, and the first field read operation is performed from the state where the signal charges of the first line are accumulated in the storage unit St. In the first field, first, the hold voltages VφHold1 and VφHold2 are set to “H” level, and the block portions Bo and Be are both in the transfer state, so that the signal charges accumulated in the storage portion St are transferred to the horizontal CCD 24. . Hereinafter, the transfer from the storage unit St to the horizontal CCD 24 is referred to as VOG transfer.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G31 , M41 + C42, Y32 + M3 are stored in the storage unit St.
3 , G43 + Y44, C34 + G35 , M45 + C4
6, Y36 + M37 , G47 + Y48, C38 + G3
9 and M49 + signal charges are accumulated.

Further, the hold voltage VφHold1 is set to the “H” level to bring the odd-numbered column block Bo into a transfer state, while the hold voltage VφHold2 is maintained at the “L” level and the even-numbered block Be is set to a transfer blocking state. Leave as is. Then, VOG transfer is performed in this state, and signal charges of the odd-numbered columns + G31 , Y32 + M33 ,
Only C34 + G35 , Y36 + M37 and C38 + G39 are transferred to the horizontal CCD 34.

As a result, in the horizontal CCD 34, signal charges of three rows of pixels (three vertical pixels) are mixed. That is, + G11 + G31 , M21
+ C22, Y12 + M13 + Y32 + M33 , G23 +
Y24, C14 + G15 + C34 + G35 , M25 + C
26, Y16 + M17 + Y36 + M37 , G27 + Y2
8, C18 + G19 + C38 + G39 and M29 + signal charges are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Next, the hold voltage VφHold1 is set to “L” level to set the odd-numbered column block Bo to the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer is blocked by the even-numbered block block Be, and the even-numbered signal charges M41 stored in the storage unit St.
+ C42, G43 + Y44, M45 + C46, G47 +
Y48 and M49 + are transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G51 , M61 + C62, Y52 + M5
3 , G63 + Y64, C54 + G55 , M65 + C6
6, Y56 + M57 , G67 + Y68, C58 + G5
9 , and M69 + signal charges are accumulated.

Further, the hold voltage VφHold1 is set to “H” level to bring the odd-numbered column block Bo into the transfer state, while the hold voltage VφHold2 is maintained at the “L” level, and the even-numbered block block Be is set to the transfer blocking state. Leave as is. Then, by performing the VOG transfer in this state, the odd-numbered signal charges + G51 , Y52
+ M53 , C54 + G55 , Y56 + M57 , C58 +
Only G59 is transferred to the horizontal CCD 34.

As a result, in the horizontal CCD 34, signal charges of two rows of pixels (two vertical pixels) are mixed. That is, + G51 , M41 + C4
2, Y52 + M53 , G43 + Y44, C54 + G5
5 , M45 + C46, Y56 + M57 , G47 + Y4
8, the signal charges of C58 + G59 and M49 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Next, the hold voltage VφHold1 is set to “L” level to set the block portion Bo in the odd-numbered column to the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer is blocked by the block Be and the signal charges M61 + C6 of the even-numbered columns accumulated in the storage unit St.
2, G63 + Y64, M65 + C66, G67 + Y6
8, M69 + is transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G71 , M81 + C82, Y72 + M7 are stored in the storage unit St.
3 , G83 + Y84, C74 + G75 , M85 + C8
6, Y76 + M77 , G87 + Y88 , C78 + G7
9 , M89 + signal charges are accumulated.

Further, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state, and VOG transfer is performed in this state.
As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, the horizontal CCD 34 has +
G71 , M61 + C62 + M81 + C82, Y72 + M
73 , G63 + Y64 + G83 + Y84, C74 + G7
5 , M65 + C66 + M85 + C86, Y76 + M7
7 , G67 + Y68 + G87 + Y88, C78 + G7
9 , the signal charges of M69 + M89 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

The above-described vertical three-pixel mixing → vertical two-pixel mixing →
By repeating each operation of vertical three-pixel mixing →..., The compression processing in the first field in the vertical 2: 3 addition-1 / 1.25 compression mode is executed.

Next, a read operation in the second field will be described. First, the hold voltage VφHold1 is set to the “H” level to bring the odd-numbered column block Bo into the transfer state, while the hold voltage VφHold2 is set to the “L” level to set the even-numbered block Be to the transfer blocking state. Then, by performing the VOG transfer in this state,
Odd column signal charges + G11 , Y12 + M13 , C14 +
G15 , Y16 + M17 , C18 + G19 only horizontal C
Transfer to CD34.

At this time, the signal charges M21 + C2 in the even-numbered columns
2, G23 + Y24, M25 + C26, G27 + Y2
8, and each signal charge of M29 + is stored in the storage unit St. Then, the signal charges in the horizontal CCD 34
+ G11 , Y12 + M13 , C14 + G15 , Y16 +
M17 and C18 + G19 are horizontally transferred as they are. By the initial operation of the second field, a combination of pixels different from that of the first field is realized in the subsequent vertical mixing.

Subsequently, the hold voltage VφHold1 is set to “L” level to set the block portion Bo in the odd-numbered column to the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer charge is blocked in the block part Be, and the signal charges M21 + C2 in the even-numbered columns accumulated in the storage part St.
2, G23 + Y24, M25 + C26, G27 + Y2
8, M29 + is transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. By performing one-line transfer in this state, + G31 , M41 + C42, Y32 + M33 , G4 are stored in the storage unit St.
3 + Y44, C34 + G35 , M45 + C46, Y36
+ M37 , G47 + Y48, C38 + G39 , M49 +
Are accumulated.

Further, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state, and VOG transfer is performed in this state.
Thus, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, the horizontal CCD 34
+ G31 , M21 + C22 + M41 + C42, Y32 +
M33 , G23 + Y24 + G43 + Y44, C34 + G
35 , M25 + C26 + M45 + C46, Y36 + M3
7 , G27 + Y28 + G47 + Y48, C38 + G3
9 , M29 + M49 + signal charges are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

After the VOG transfer, the hold voltage VφHo
ld1 and VφHold2 are set to the “L” level, and both the blocks Bo and Be are set to the transfer blocking state. Then, by performing one-line transfer in this state, the storage unit S
t is + G51 , M61 + C62, Y52 + M53 ,
G63 + Y64, C54 + G55 , M65 + C66, Y
56 + M57 , G67 + Y68, C58 + G59 , M6
9+ signal charges are accumulated.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
VOG transfer is performed with e being in the transfer state. Thus, the horizontal CCD 34 has + G51 , M61 + C62, Y52 + M5 stored in the storage unit St.
3 , G63 + Y64, C54 + G55 , M65 + C6
6, Y56 + M57 , G67 + Y68, C58 + G5
9 , and each signal charge of M69 + is transferred as it is. Then, these signal charges are sequentially and horizontally transferred. as a result,
An output of a vertical two-pixel mixture is obtained.

After the VOG transfer, the hold voltage VφHo
ld1 and VφHold2 are set to the “L” level, and both the blocks Bo and Be are set to the transfer blocking state. Then, by performing one-line transfer in this state, the storage unit S
t is + G71 , M81 + C82, Y72 + M73 ,
G83 + Y84, C74 + G75 , M85 + C86, Y
76 + M77 , G87 + Y88 , C78 + G79 , M8
9+ signal charges are accumulated.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
VOG transfer is performed with e being in the transfer state. Thus, the horizontal CCD 34 has + G71 , M81 + C82, Y72 + M7 stored in the storage unit St.
3 , G83 + Y84, C74 + G75 , M85 + C8
6, Y76 + M77 , G87 + Y88 , C78 + G7
9 and M89 + are transferred as they are.

Subsequently, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, by performing one-line transfer in this state, the signal charges of the pixels of the next two rows are accumulated in the storage unit St.

After this one-line transfer, the hold voltage VφH
old1 is set to the “H” level, and the block portion Bo of the odd-numbered column is set.
Is held in the transfer state, and the hold voltage VφHold2 is maintained at the “L” level to keep the even-numbered block B
e is kept in the transfer blocking state. Then, in this state, V
By performing the OG transfer, the odd-numbered signal charges + G9
1 , + Y92 + M93 , + C94 + G95 , + Y96 +
Only M97 , + C98 + G99 are transferred to the horizontal CCD 34.

As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, horizontal CCD
34, + G71 + G91 , M81 + C82, Y72
+ M73 + Y92 + M93 , G83 + Y84, C74 +
G75 + C94 + G95 , M85 + C86, Y76 + M
77 + Y96 + M97 , G87 + Y88 , C78 + G7
9 + C98 + G99 and M89 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

The above vertical two pixel mixture → vertical three pixel mixture →
By repeating each operation of vertical two-pixel mixing →..., The compression processing in the second field in the vertical 2: 3 addition-1 / 1.25 compression mode is executed.

As described above, vertical 3 pixel mixture → vertical 2
By repeating each operation of pixel mixing → vertical three-pixel mixing → vertical two-pixel mixing →... And changing the combination of pixels to be mixed in the first field and the second field, information of four pixels in the vertical direction is originally used. Since information for five vertical pixels is used for obtaining information for two lines, the vertical 1 / 1.2 pixels are held while holding the color difference signals Cr and Cb.
5 (= 5/4) compression processing can be realized.

In FIG. 12, ○ indicates the center of gravity of each line in the first field, and × indicates the center of gravity of each line in the second field. As is clear from FIG.
The center of gravity of each line in the field and the second field is 1/5
It can be seen that it is shifted by the pixel pitch. However, the deviation of the center of gravity is extremely small, and is of a practically negligible level. Note that, if necessary, the center of gravity can be complemented in the subsequent signal processing system by using signals of adjacent pixels.

Next, the operation in the compression mode when vertical 3: 3 addition-1 / 1.5 compression is performed will be described with reference to the operation explanatory diagram of FIG. In the case of the vertical 1 / 1.5 compression, as in the case of the above-described vertical 1 / 1.25 compression, the signal charge is read out from the sensor unit 31 to the vertical CCD 32 and the horizontal two-pixel mixing is performed. Line transfer will be performed.

At the time of one-line transfer, the hold voltage VφH
Old1 and VφHold2 are set to the “L” level, and the block portions Bo and Be are both in the transfer blocking state.
+ G11 , M21 + C22, Y
12 + M13 , G23 + Y24, C14 + G15 , M2
5 + C26, Y16 + M17 , G27 + Y28, C18
The signal charges of + G19 and M29 + are accumulated. Here, the underlined line indicates the color difference signal Cr, and the underlined line indicates the color difference signal Cb.

As described above, the vertical CCD is
The signal charge is read out to block 32, and the block B
Both o and Be are in the transfer blocking state, and the first field read operation is performed from the state where the signal charges of the first line are accumulated in the storage unit St. In the first field, first, the hold voltages VφHold1 and VφHold2 are set to the “H” level, and both the blocks Bo and Be are in the transfer state. By performing the VOG transfer in this state, the signal charges stored in the storage unit St are transferred to the horizontal CCD.
Transfer to 24.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G31 , M41 + C42, Y32 + M3 are stored in the storage unit St.
3 , G43 + Y44, C34 + G35 , M45 + C4
6, Y36 + M37 , G47 + Y48, C38 + G3
9 and M49 + signal charges are accumulated.

Further, the hold voltage VφHold1 is set to the “H” level to bring the odd-numbered column block Bo into the transfer state, while the hold voltage VφHold2 is maintained at the “L” level and the even-numbered column block Be is set to the transfer blocking state. Leave as is. Then, VOG transfer is performed in this state, and signal charges of the odd-numbered columns + G31 , Y32 + M33 ,
Only C34 + G35 , Y36 + M37 and C38 + G39 are transferred to the horizontal CCD 34.

As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, horizontal CCD
34, + G11 + G31 , M21 + C22, Y12
+ M13 + Y32 + M33 , G23 + Y24, C14 +
G15 + C34 + G35 , M25 + C26, Y16 + M
17 + Y36 + M37 , G27 + Y28, C18 + G1
9 + C38 + G39 and M29 + signal charges are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Next, the hold voltage VφHold1 is set to “L” level to set the block portion Bo in the odd-numbered column to the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer is blocked by the even-numbered block block Be, and the even-numbered signal charges M41 stored in the storage unit St.
+ C42, G43 + Y44, M45 + C46, G47 +
Y48 and M49 + are transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G51 , M61 + C62, Y52 + M5
3 , G63 + Y64, C54 + G55 , M65 + C6
6, Y56 + M57 , G67 + Y68, C58 + G5
9 , and M69 + signal charges are accumulated.

Next, hold voltages VφHold1, Vφ
Hold2 is set to the “H” level, and the block portions Bo and Be
Are both in the transfer state. By performing the VOG transfer in this state, the data has been stored in the storage unit St until then.
+ G51 , M61 + C62, Y52 + M53 , G63 +
Y64, C54 + G55 , M65 + C66, Y56 + M
57 , G67 + Y68, C58 + G59 , and M69 + are transferred to the horizontal CCD 24.

As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, horizontal CCD
34, + G51 , M41 + C42 + M61 + C6
2, Y52 + M53 , G43 + Y44 + G63 + Y6
4, C54 + G55 , M45 + C46 + M65 + C6
6, Y56 + M57 , G47 + Y48 + G67 + Y6
8, signal charges of C58 + G59 and M69 + M69 + are sequentially arranged. Then, these signal charges are sequentially and horizontally transferred.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, + G71 , M81 + C82, Y72 + M7 are stored in the storage unit St.
3 , G83 + Y84, C74 + G75 , M85 + C8
6, Y76 + M77 , G87 + Y88 , C78 + G7
9 , M89 + signal charges are accumulated.

Subsequently, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state. By performing the VOG transfer in this state, the + G71 , M81 + C82, Y72 + M73 , and G83 previously stored in the storage unit St.
+ Y84, C74 + G75 , M85 + C86, Y76 +
The signal charges of M77 , G87 + Y88 , C78 + G79 , and M89 + are transferred to the horizontal CCD 24.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, the signal charge of each pixel of the next two rows is accumulated in the storage unit St.

Further, the hold voltage VφHold1 is set to the “H” level to bring the odd-numbered column block Bo into the transfer state, while the hold voltage VφHold2 is maintained at the “L” level, and the even-numbered block block Be is set to the transfer blocking state. Leave as is. Then, by performing the VOG transfer in this state, the odd-numbered signal charges + G91 , Y92
+ M93 , C94 + G95 , Y96 + M97 , C98 +
Only G99 is transferred to the horizontal CCD.

As a result, in the horizontal CCD 34, signal charges of two vertical pixels are mixed. That is, horizontal CCD
34, + G71 + G91 , M81 + C82, Y72
+ M73 + Y92 + M93 , G83 + Y84, C74 +
G75 + C94 + G95 , M85 + C86, Y76 + M
77 + Y96 + M97 , G87 + Y88 , C78 + G7
9 + C98 + G99 and M89 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

The above vertical three pixel mixture → vertical three pixel mixture →
By repeating the operations of vertical three pixel mixing →..., The compression processing in the first field in the vertical 3: 3 addition-1 / 1.5 compression mode is executed.

Next, a read operation in the second field will be described. First, the hold voltage VφHold1 is set to the “H” level, and the odd-numbered column block Bo is set to the transfer state, while the hold voltage VφHold2 is set to the “L” level, and the even-numbered block Be is set to the transfer blocking state. Then, by performing the VOG transfer in this state,
Odd column signal charges + G11 , Y12 + M13 , C14 +
G15 , Y16 + M17 , C18 + G19 only horizontal C
Transfer to CD34.

At this time, signal charges M21 + C2 of even-numbered columns
2, G23 + Y24, M25 + C26, G27 + Y2
8, and each signal charge of M29 + is stored in the storage unit St. Then, the signal charges in the horizontal CCD 34
+ G11 , Y12 + M13 , C14 + G15 , Y16 +
M17 and C18 + G19 are horizontally transferred as they are. By the initial operation of the second field, a combination of pixels different from that of the first field is realized in the subsequent vertical mixing.

Subsequently, the hold voltage VφHold1 is set to “L” level to put the odd-numbered column block Bo in the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer charge is blocked in the block part Be, and the signal charges M21 + C2 in the even-numbered columns accumulated in the storage part St.
2, G23 + Y24, M25 + C26, G27 + Y2
8, M29 + is transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. By performing one-line transfer in this state, + G31 , M41 + C42, Y32 + M33 , G4 are stored in the storage unit St.
3 + Y44, C34 + G35 , M45 + C46, Y36
+ M37 , G47 + Y48, C38 + G39 , M49 +
Are accumulated.

Further, hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state, and VOG transfer is performed in this state.
Thus, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, the horizontal CCD 34
+ G31 , M21 + C22 + M41 + C42, Y32 +
M33 , G23 + Y24 + G43 + Y44, C34 + G
35 , M25 + C26 + M45 + C46, Y36 + M3
7 , G27 + Y28 + G47 + Y48, C38 + G3
9 , M29 + M49 + signal charges are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one line transfer is performed in this state. Thereby, the storage unit St
+ G51 , M61 + C62, Y52 + M53 , G
63 + Y64, C54 + G55 , M65 + C66, Y5
6 + M57 , G67 + Y68, C58 + G59 , M69
Each signal charge of + is accumulated.

Next, hold voltages VφHold1, Vφ
Hold2 is set to the “H” level, and the block portions Bo and Be
Are both in the transfer state. Then, by performing VOG transfer in this state, + G51 , M61 + C62, Y52 + M53 ,
G63 + Y64, C54 + G55 , M65 + C66, Y
56 + M57 , G67 + Y68, C58 + G59 , M6
The 9+ signal charges are transferred to the horizontal CCD.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one line transfer is performed in this state. Thereby, the storage unit St
+ G71 , M81 + C82, Y72 + M73 , G
83 + Y84, C74 + G75 , M85 + C86, Y7
6 + M77 , G87 + Y88 , C78 + G79 , M89
Each signal charge of + is accumulated.

Further, the hold voltage VφHold1 is set to “H” level to bring the odd-numbered column block Bo into a transfer state, while the hold voltage VφHold2 is set to “L” level to set the even-numbered block block Be to a transfer prevention state. Then, by performing the VOG transfer in this state,
Odd column signal charges + G71 , Y72 + M73 , C74 +
G75 , Y76 + M77 , C78 + G79 only horizontal C
Transfer to CD34.

As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. That is, horizontal CCD
34, + G51 + G71 , M61 + C62, Y52
+ M53 + Y72 + M73 , G63 + Y64, C54 +
G55 + C74 + G75 , M65 + C66, Y56 + M
57 + Y76 + M77 , G67 + Y68, C58 + G5
The signal charges of 9 + C78 + G79 and M69 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Subsequently, the hold voltage VφHold1 is set to “L” level to set the block portion Bo in the odd column to the transfer blocking state, and the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, by performing the VOG transfer in this state,
Until then, the transfer is blocked by the block part Be, and the signal charges M81 + C8 in the even columns stored in the storage part St.
2, G83 + Y84, M85 + C86, G87 + Y8
8, M89 + is transferred to the horizontal CCD 34.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. Then, one-line transfer is performed in this state. By this one-line transfer, the signal charges + G91 ,
M101 + C102, Y92 + M93 , G103 + Y104, C
94 + G95 , M105 + C106 , Y96 + M97 , G10
7 + Y108, C98 + G99 and M109 + are accumulated.

Further, the hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state. Then, by performing the VOG transfer in this state, the horizontal CCD 34 mixes the signal charges of the three vertical pixels. That is, + G91 , M81 + C82 + M101 + C102, Y9
2 + M93 , G83 + Y84 + G103 + Y104, C94
+ G95 , M85 + C86 + M105 + C106 , Y96 +
M97 , G87 + Y88 + G107 + Y108, C98 + G
99 , M89 + M109 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

The above vertical three pixel mixture → vertical three pixel mixture →
By repeating each operation of vertical three-pixel mixing →..., Compression processing in the second field in the vertical 3: 3 addition-1 / 1.5 compression mode is executed.

As described above, vertical 3 pixel mixture → vertical 3
By repeating the operation of pixel mixing → vertical three-pixel mixing →... And changing the combination of pixels to be mixed in the first field and the second field, information of two lines is originally used by using information of four vertical pixels. On the other hand, since information for six vertical pixels is used, the color difference signals Cr, C
A compression process of vertical 1 / 1.5 (= 6/4) can be realized while holding b.

In FIG. 13, ○ indicates the center of gravity of each line in the first field, and x indicates the center of gravity of each line in the second field. As is clear from FIG.
The center of gravity of each line in the field and the second field is 1/3
The shift is by the pixel pitch, and the shift is larger than in the case of the compression of vertical 1 / 1.25. Therefore, if necessary, in the subsequent signal processing system, the center-of-gravity deviation can be complemented by using signals of adjacent pixels.

In addition, for only the second field, the signal charges of one pixel are not read out for every three vertical pixels.
The center of gravity can be adjusted by performing a so-called thinning operation. The operation in this case will be described below with reference to the operation explanatory diagram of FIG. When this thinning operation is applied, it is necessary to change the wiring system of the pixel portion of the CCD image sensor as described later.

First, in the second field, the vertical 3
The thinning operation of one pixel is performed for each pixel. In this example,
As is clear from FIG. 14, M21, C22,
G23, Y24, M25, C26, G27, Y29, M
29,..., G51, Y52, M53, C5 in the fifth row
4, G55, Y56, M57, C58, G59, ...,
M81, C82, G83, Y84, M85, C on the eighth line
The signal charges of pixels 86, G87, Y89, M89,... Are thinned out. This thinning operation can be easily realized by a known technique.

More specifically, as is clear from the wiring diagram of the pixel portion in FIG. 15, two vertical transfer clocks Vφ1 to Vφ1
.phi.4, V.phi.1 'to V.phi.4' are prepared, and their wiring patterns are also divided into two systems (51 to 54, 51 'to 5').
4 '), the vertical transfer clocks V.phi.1 to V.phi.
φ4, and the vertical transfer clock Vφ1 ′ is passed through the wiring patterns 51 ′ to 54 ′ for the pixels to be read out.
~ Vφ4 '.

In the first field, the signal charges of all the pixels can be read by setting the read pulse XSG to all of the two vertical transfer clocks Vφ1 to Vφ4 and Vφ1 ′ to Vφ4 ′. on the other hand,
In the second field, the vertical transfer clocks Vφ1 to Vφ4
The signal charges can be read out every other row in units of two rows by raising the read pulse XSG only on the second row and not raising the read pulse XSG on the vertical transfer clocks Vφ1 ′ to Vφ4 ′. That is, one for every three vertical pixels
A pixel thinning operation is performed.

In the second field, the signal charges read out by the thinning operation of one pixel for every three vertical pixels are output as follows. First, the hold voltage VφHold1 is set to the “H” level to bring the odd-numbered column block Bo into the transfer state, while the hold voltage VφHold2 is set to the “L” level to set the even-numbered block Be to the transfer blocking state. Then, by performing the VOG transfer in this state, the signal charges of the odd-numbered columns + G
11 , Y12 + M13 , C14 + G15 , Y16 + M1
7. Transfer only C18 + G19 to the horizontal CCD 34.

At this time, signal charges M21 and C2 in even-numbered columns
2, G23, Y24, M25, C26, G27, Y2
8 and M29 + are not read out by the thinning-out operation.
No signal charge is accumulated at t. And horizontal CC
Signal charge in D34 + G11 , Y12 + M13 , C14
+ G15 , Y16 + M17 and C18 + G19 are horizontally transferred as they are. By the initial operation of the second field, a combination of pixels different from that of the first field is realized in the subsequent vertical mixing.

Subsequently, the hold voltage VφHold1 is set to “L” level to set the block portion Bo in the odd-numbered column to the transfer blocking state, while the hold voltage VφHold2 is set to “H”.
As the level, the block portion Be of the even-numbered column is set to the transfer state. Then, VOG transfer is performed in this state.
Since no signal charges are stored in the storage unit St, the transfer of the signal charges to the horizontal CCD 34 is not performed. That is, in this VOG transfer, idle feeding is performed. Therefore, the packets (transfer stages) corresponding to the even-numbered columns of the vertical CCDs 32e in the horizontal CCD 34 are empty.

Next, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both in the transfer blocking state. By performing one-line transfer in this state, + G31 , M41 + C42, Y32 + M33 , G4 are stored in the storage unit St.
3 + Y44, C34 + G35 , M45 + C46, Y36
+ M37 , G47 + Y48, C38 + G39 , M49 +
Are accumulated.

Further, hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state, and VOG transfer is performed in this state, so that the horizontal CCD 34 mixes signal charges of three vertical pixels. However, since the packets corresponding to the vertical CCDs 32e in the even-numbered columns of the horizontal CCD 34 are empty, the horizontal CCD 34 has + G31 , M41 + C42,
Y32 + M33 , G43 + Y44, C34 + G35 , M
45 + C46, Y36 + M37 , G47 + Y48, C3
The signal charges of 8 + G39 and M49 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

Next, the hold voltages VφHold1, Vφ
Hold2 is set to the “L” level, and the block portions Bo and Be
Are both in the transfer blocking state, and one-line transfer is performed. At this time, the pixels G51, Y52, M53, C54, G
No signal charges are accumulated in the storage unit St because no reading is performed on the 55, Y56, M57, C58, and G59 by the thinning operation. Subsequently, the hold voltages VφHold1 and VφHold2 are set to the “H” level, and both the blocks Bo and Be are in the transfer state, and the VOG transfer is performed. At this time, the storage unit S
Since no signal charge is accumulated at t, the idle feeding is performed.

Thereafter, the hold voltages VφHold1, V
φHold2 is set to the “L” level and the block portions Bo and B
e are both set to the transfer blocking state, and one-line transfer is performed. Thereby, + G71 , M61 + C are stored in the storage unit St.
62, Y72 + M73 , G63 + Y64, C74 + G7
5 , M65 + C66, Y76 + M77 , G67 + Y6
8, the signal charges of C78 + G79 and M69 + are accumulated.

Further, hold voltages VφHold1, V
φHold2 is set to “H” level and the block portions Bo and B
e are both in the transfer state, and the VOG transfer is performed.
+ G71 previously stored in the storage unit St,
M61 + C62, Y72 + M73 , G63 + Y64, C
74 + G75 , M65 + C66, Y76 + M77 , G6
The signal charges of 7 + Y68, C78 + G79 and M69 + are transferred to the horizontal CCD 34.

As a result, in the horizontal CCD 34, signal charges of three vertical pixels are mixed. However, since the signal charges have not been transferred to the horizontal CCD 34 at the previous stage, the + G71 , M
61 + C62, Y72 + M73 , G63 + Y64, C7
4 + G75 , M65 + C66, Y76 + M77 , G67
The signal charges of + Y68, C78 + G79 , and M69 + are arranged in order. Then, these signal charges are sequentially and horizontally transferred.

As described above, the CC capable of performing the thinning operation
In the D image pickup device, thinning-out readout of one pixel is performed for three vertical pixels only in the second field, and the operation of mixing three vertical pixels → mixing three vertical pixels →... Is repeated to hold the color difference signals Cr and Cb. Vertical 1 / 1.5
(= 6/4) compression processing can be realized, and the displacement of the center of gravity of the second field can be eliminated.

In the above description, vertical 2: 3 addition-1 / 1.25 compression and vertical 3: 3 addition-1 / 1.5 compression have been described as examples. However, vertical 3: 4 addition-1 / 1.75 has been described. Compression and vertical 4: 4 addition-1 / 2.0 compression are also possible.
However, since the compression ratio exceeding 1 / 2.0 may exceed the amount of electric charges handled by the horizontal CCD 34 since the number of pixels added to the horizontal CCD 34 exceeds 4, in such a case, the sensor unit 31 is read out by frame reading. And 1/2.
After compression to 0, the horizontal CCD 34 may further perform vertical compression.

As a result, vertical 4: 5 addition-1 / 2.25
Compression, vertical 5: 5 addition-1 / 2.5 compression, vertical 5: 6 addition-1.2.75 compression, vertical 6: 6 addition-1 / 3.0 compression, vertical 6: 7 addition-1/3 Horizontal CCD such as .25 compression, vertical 7: 7 addition -1 / 3.5 compression, vertical 7: 8 addition -1 / 3.75 compression, vertical 8: 8 addition -1 / 4.0 compression
34 can be realized.

Further, as described above, if a charge discharging section including an overflow gate and an overflow drain is provided adjacent to the storage section St of the hold gate sections 35o and 35e, and the storage section St performs vertical addition, Without overflowing in the horizontal CCD 34, compression addition exceeding vertical 8: 8 addition-1 / 4.0 compression is also possible.

However, in the horizontal direction, compression cannot be performed basically, so that the horizontal drive frequency is determined by the initially set number of pixels. For example, when the calculation is performed using 1 / 2.0 compression as an example, NTSC vertical effective 485 lines 2
Down conversion is possible from 970 pixels, which is twice as large. Furthermore, if the camera shake correction area is set to 20%, the vertical
There are four pixels. Assuming that the aspect ratio of the pixel is 1: 1, the 4: 3 TV format has a horizontal of 1164 × 4/3.
= 1552 pixels (1.81 million pixels), 16: 9 TV
In the format, horizontal 1164 × 16/9 = 2069 pixels (2.41 million pixels).

The horizontal drive frequency is $ 1552 × 63.56.
/(63.56-10.9)｝/63.56 μs = 2
At 9.5 MHz, vertical 1 / 2.0 compression NTSC drive
Also, {1552 × 64 / (64−12)} / 64 μs
= 29.85 MHz, PAL drive with vertical 1 / 2.0 compression image stabilization area 1% or vertical 1 / 1.75 compression image stabilization area 16%, and digital still camera with 18.1 million pixel frame readout, At 16: 9, if 1080 is cut out from the vertical 1164, 1080P (P
Is an acronym for Progressive), and a high-pixel CCD image sensor for digital TV capable of correcting camera shake by 8% can be easily realized.

For the progressive scan (PS) operation in NTSC or PAL, the horizontal drive frequency should be doubled and the compression ratio should be 1 / 1.0. If the number of pixels is further increased, it is possible to increase the resolution and to increase the camera shake correction area.

When calculated with the maximum compression ratio of 1 / 4.0 and the NTSC camera shake correction amount of 20% that can be realized within the range of the charge amount handled by the horizontal CCD, vertical; 485 × 4 × 1.2 = 2
With 328 pixels, horizontal; 2328 × 4/3 = 3104 pixels, down-conversion from a 7.23 million pixel CCD image sensor becomes possible.

When the horizontal 3104 pixels are used, the output data rate in the TV system becomes high. For example, even if the horizontal drive frequency is high, the reset gate frequency of the charge detection section 36 is reduced by half, and the reset operation is skipped once so that the floating operation is performed. If horizontal two-pixel addition is performed by the diffusion FD,
From M / Y / G / C independent reading of frame reading,
Color difference signals such as M + Y and G + C or Y + G and C + M can be output at a rate of 1/2 of the horizontal drive frequency.

That is, horizontal compression can be performed on data output corresponding to horizontal 3104/2 = 1552 pixels. Latter stage C
This is an advantageous compression means for a DS (correlated double sampling) circuit, an AGC (automatic gain control) circuit, an A / D converter, and a signal processing IC. The subsequent signal processing IC has 3
The information of 7.23 million pixels can be processed at a little less than 0 MHz. If only the luminance signal (black and white output) is sufficient, M / Y
The output data rate can be reduced to 1/4 by adding all the pixel information of the four colors / G / C by the floating diffusion FD.

In each of the above embodiments, the CCD
As a color filter mounted on the imaging devices 10 and 30,
Although the case where the complementary color filters of M / Y / G / C are used has been described as an example, the same can be said for the case where not only the complementary color filters but also the primary color filters are used.

FIG. 16 is a schematic diagram showing an example of the configuration of a camera system according to the present invention using the CCD image pickup device according to the first or second embodiment as an image pickup device. The camera system includes a CCD image sensor 61, a lens 62 forming a part of an optical system, a CCD driving circuit 63, an imaging mode setting section 64, and a signal processing circuit 65. The CCD image sensor 61 is equipped with a color filter having color coding of two vertical repetitions.

In the camera system having such a configuration, incident light (image light) from a subject (not shown) passes through a color filter (not shown) by a lens 62 of an optical system to a CC filter.
An image is formed on the imaging surface of the D imaging element 61. The CCD image sensor 61 is driven by the CCD driving circuit 63 in accordance with the imaging mode set by the imaging mode setting section 64. Here, the imaging mode setting unit 64 determines whether a still image or a moving image (NTS
It is possible to set each imaging mode of C / PAL / Hi-Vision) and PS (progressive scan).

In the still image mode, the CCD driving circuit 63 drives the CCD image sensor 61 so as to perform well-known frame reading. In video mode, as mentioned earlier,
The color difference signals Cr and Cb are output in a line-sequential arrangement and dot-sequential output by horizontal two-pixel mixed readout, and the CCD image sensor 61 is driven so as to perform vertical compression processing in a horizontal CCD.
By the operation in the moving image mode, as described above, the vertical mixing process is performed while holding the color difference signals Cr and Cb,
Down conversion to a television signal such as NTSC / PAL is performed.

When the PS mode is set, the signal processing circuit 65 converts the color difference signals Cr and Cb obtained in a line sequential arrangement and dot sequential output by horizontal two-pixel mixed reading,
The signals are separated into odd bits and even bits, and the signals in the odd and even rows are independently processed. Accordingly, the same progressive (P) as reading signal charges independently for each row is used.
S) Operation can be realized.

As described above, a camera system capable of performing arbitrary vertical compression and horizontal output data rate compression, and capable of supporting still / moving picture / PS imaging modes with balanced vertical / horizontal resolutions. realizable. Thus, by using a multi-pixel CCD image pickup device for a digital still camera as an image pickup device, it becomes possible to monitor a television image of the NTSC system or the PAL system without deteriorating the image quality.

[0156]

As described above, according to the present invention,
Among the plurality of sensor units, each signal charge of the sensor unit group located in every other row is transferred to the first transfer unit group arranged in every other column, and each signal charge of the sensor unit group located in every other row. Is read out to every other column in the second transfer unit group, and the signal charges of two pixels adjacent in the column direction are added in the same transfer unit. The retention allows arbitrary vertical compression and horizontal output data rate compression, as well as balancing vertical / horizontal resolution.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a CCD imaging device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of color coding.

FIG. 3 is a timing chart in a normal mode.

FIG. 4 is a plan pattern diagram illustrating an example of a specific configuration around a sensor unit.

FIG. 5 is a view showing a general complementary color coating.

FIG. 6 is an explanatory diagram of an operation at the time of field reading.

FIG. 7 is an explanatory diagram (part 1) of an operation at the time of frame reading.

FIG. 8 is an explanatory diagram (part 2) of an operation at the time of frame reading.

FIG. 9 is a schematic configuration diagram illustrating a CCD imaging device according to a second embodiment of the present invention.

FIG. 10 is a plan pattern diagram illustrating an example of a specific configuration of a vertical output gate unit.

FIG. 11 is a potential diagram of a vertical output gate unit.

FIG. 12 is an explanatory diagram of the operation at the time of vertical 2: 3 addition-1 / 1.25 compression.

FIG. 13 is an operation explanatory diagram at the time of vertical 3: 3 addition-1 / 1.5 compression.

FIG. 14 is an explanatory diagram of the operation when complementing the displacement of the center of gravity.

FIG. 15 is a wiring pattern diagram for realizing the center of gravity deviation complementation.

FIG. 16 is a block diagram showing an example of a camera system according to the present invention.

FIG. 17 shows color difference signals Cr and C in a conventional example (part 1).
It is a figure showing arrangement relation of b.

FIG. 18 shows color difference signals Cr and C in a conventional example (part 2).
It is a figure showing arrangement relation of b.

FIG. 19 is a diagram illustrating the operation of vertical compression in the case of the conventional example (part 2).

[Explanation of symbols]

10, 30, 61: CCD image pickup device, 11 (11o, 1)
1e), 31 ... Sensor part, 12 (12o, 12e), 3
2 (32o, 32e) ... vertical CCD, 13, 33 ... readout gate unit, 14, 34 ... horizontal CCD, 16, 36 ...
Charge detection section, 35o, 35e ... hold gate section

Continued on the front page F-term (reference) 4M118 AB01 BA13 CA03 DB03 DB06 DB08 DD04 DD08 DD12 FA06 FA26 FA35 GC09 5C024 AA01 CA11 DA01 DA05 FA01 FA13 FA14 GA11 GA16 HA05 HA17 5C065 AA01 CC01 CC04 DD01 DD02 DD03 DD07 EE03 AE05 AE08 GG10 DA09 EA08 FA03 FA08 FB08 FB21 FB23 FB27 XA10

Claims (21)

[Claims] 1. A plurality of sensor units arranged in a matrix, a first transfer unit group arranged every other row with respect to the plurality of sensor units, and arranged every other row. Second
A vertical transfer section comprising a transfer section group of the plurality of sensor sections, and a signal charge of each of the sensor section groups located in every other row among the plurality of sensor sections being placed in the first transfer section group and a sensor being placed in every other row. A first drive system for reading each signal charge of the unit group to the second transfer unit group; and a column direction read from the plurality of sensor units in each of the first and second transfer unit groups. And a second drive system for adding signal charges of two adjacent pixels. 2. The method according to claim 1, wherein the first drive system includes: a signal unit of a sensor unit group located in every other column and every other row; and a signal charge of a sensor unit group located in another every other column and every other row. And reading out each signal charge of the sensor unit group located in every other row and the sensor unit group located in another every other column and every other row independently.
The solid-state imaging device according to any one of the preceding claims. 3. The first drive system according to claim 1, wherein each signal charge of a sensor unit group located in every other column and every other row, and each signal of a sensor unit group located in another every other column and every other row. The charge and the signal charges of the sensor units located in every other column and every other row and the signal charges of the sensor units located in every other column and every other row are read out independently. The solid-state imaging device according to claim 1. 4. The first drive system includes a gate electrode having a two-layer structure in a portion for reading signal charges from each sensor portion,
Reading out each signal charge of the sensor unit group located in every other column and every other row and the sensor unit group located in every other column and every other row through the gate electrode of the first layer,
The signal charges of a sensor unit group located in every other column and every other row and a signal charge of another sensor unit group located in every other column and every other row are read out through the gate electrode of the second layer. 2. The solid-state imaging device according to 1. 5. A plurality of sensor sections arranged in a matrix, and a color coding scheme in which the same color is repeated for every two pixels in a row direction while being arranged corresponding to each of the plurality of sensor sections. A color filter, a first transfer unit group disposed every other row for the plurality of sensor units, and a second transfer unit group disposed every other row.
A vertical transfer section comprising a transfer section group of the plurality of sensor sections, and a signal charge of each of the sensor section groups located in every other row among the plurality of sensor sections being placed in the first transfer section group and a sensor being placed in every other row. A first drive system for reading out each signal charge of the unit group to the second transfer unit group. 6. The solid-state imaging device according to claim 5, further comprising: signal charges of two pixels adjacent to each other in the column direction read from the plurality of sensor units in each of the first and second transfer unit groups. And a second drive system for adding the following. 7. The first driving system according to claim 1, wherein each of the signal charges of a sensor unit group located in every other row and every other row and a sensor charge group located in another every other row and every other row is connected to every other column. And reading out each signal charge of the sensor unit group located in every other row and the sensor unit group located in another every other column and every other row independently.
The solid-state imaging device according to any one of the preceding claims. 8. The first driving system according to claim 1, wherein each of the signal charges of the sensor unit group located in every other column and every other row and each signal of the sensor unit group located in another every other column and every other row. The charge and the signal charges of the sensor units located in every other column and every other row and the signal charges of the sensor units located in every other column and every other row are read out independently. The solid-state imaging device according to claim 5, wherein 9. The first drive system includes a gate electrode having a two-layer structure in a portion for reading out signal charges from each sensor portion,
Reading out each signal charge of the sensor unit group located in every other column and every other row and the sensor unit group located in every other column and every other row through the gate electrode of the first layer,
The signal charges of a sensor unit group located in every other column and every other row and a signal charge of another sensor unit group located in every other column and every other row are read out through the gate electrode of the second layer. 6. The solid-state imaging device according to 5. 10. The color filter has a four-color filter in which four pixels are repeated in a row direction, and the first color is provided every other row.
When the second color, the third color, and the fourth color are arranged, the other line is the third color.
6. The solid-state imaging device according to claim 5, wherein a color is a filter arrangement of a fourth color, a first color, and a second color. 11. A plurality of sensor units arranged in a matrix, each signal charge of a sensor unit group located in every other row is transferred to a first transfer unit group arranged in every other column, and the other signal charges are added to another row. Each signal charge of the sensor unit group positioned every other is read out to the second transfer unit group arranged every other column, and in each of the first and second transfer unit groups, the signal charges are read from the plurality of sensor units. A method for driving a solid-state imaging device, comprising: adding read signal charges of two pixels adjacent in a column direction. 12. A solid-state imaging device having a color filter having a color coding in which the same color is repeated for every two pixels in a row direction and is arranged corresponding to each of a plurality of sensor units arranged in a matrix. Out of the plurality of sensor units, the first vertical transfer unit group in which each signal charge of the sensor unit group located in every other row is arranged every other column; A method for driving a solid-state imaging device, wherein each signal charge is read out to a second vertical transfer unit group arranged every other column. 13. The color filter includes a four-color filter in which four pixels are repeated in a row direction, and a first color for every other row.
When the second color, the third color, and the fourth color are arranged, the other line is the third color.
13. The driving method for a solid-state imaging device according to claim 12, wherein a color is a filter array of a fourth color, a first color, and a second color. 14. The method according to claim 1, wherein in each of the first and second groups of vertical transfer units, signal charges of two pixels adjacent in the column direction read from the plurality of sensor units are added. 14. A method for driving a solid-state imaging device according to item 13. 15. The method of driving a solid-state imaging device according to claim 13, wherein each signal of a sensor group located in every other column and every other row and a sensor group located in every other row and every other row. A solid-state imaging device, wherein the charge and the signal charges of the sensor units located in every other row and every other row and the sensor units located in every other column and every other row are read out independently. Drive method. 16. The driving method for a solid-state imaging device according to claim 15, wherein in the horizontal transfer unit, signal charges in the row direction are added by performing a bit shift. 17. The method according to claim 15, wherein the charge detection section adds the signal charges in the column direction by thinning out the reset operation. 18. A plurality of sensor units arranged in a matrix, each signal charge of a sensor unit group located in every other row is transferred to a first transfer unit group arranged in every other column, and the other signal charges are added to another row. The signal charges of the sensor units located at every other row are read out to the second transfer unit group arranged at every other row, and the first and second signal charges are read out.
A solid-state imaging device capable of adding and outputting signal charges of two pixels adjacent in the column direction read from the plurality of sensor units in each of the transfer unit groups, and selecting a still image mode or a moving image mode Image-pickup mode setting means that can be set as desired; driving means for driving the solid-state image sensor according to the image-pickup mode set by the image-pickup mode setting means; A camera system comprising: 19. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided corresponding to each of the plurality of sensor units, and has a color filter of a color coding in which the same color is repeated for every two pixels in a row direction. 19. The camera system according to claim 18, wherein 20. The color filter has a four-color filter in which four pixels are repeated in a row direction, and the first color is provided every other row.
When the second color, the third color, and the fourth color are arranged, the other line is the third color.
20. The camera system according to claim 19, wherein the color is a filter arrangement of a fourth color, a first color, and a second color. 21. The imaging mode setting means can alternatively set a progressive operation mode for obtaining a signal for each row of the solid-state imaging device. The signal processing means is configured to be progressive by the imaging mode setting means. When an operation mode is set, a signal output from the solid-state imaging device is separated into odd bits and even bits, and a signal on every other row and a signal on every other row are independently processed. Item 19. The camera system according to Item 18.