JP2000183179A - Semiconductor integrated circuit and wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the operating speed of a semiconductor integrated circuit by forming the semiconductor integrated circuit on a substrate having a com pound semiconductor layer on an embedded insulation layer. SOLUTION: On a Si substrate 2 an embedded insulation layer 3 is formed, a Si epitaxial layer 4 is formed on the insulation layer 3, a single-crystal compd. semiconductor layer 5 is formed on the single-crystal Si epitaxial layer 4, whereby the Si substrate 2, the embedded insulation layer 3, the Si epitaxial layer 4 and the single-crystal compound semiconductor layer 5 form a semiconductor substrate 1, and transistors 21 are formed as active elements on the substrate 1, using the semiconductor layer 5. Thus since the operating speed of the active elements 21 on the semiconductor layer 5 is improved, it is possible to improve the operating speed of the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a wafer on which the semiconductor integrated circuit is formed, and more particularly, to a semiconductor integrated circuit composed of active elements such as transistors and such a semiconductor integrated circuit. It concerns a wafer.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit is formed on a silicon substrate, for example. As one type of silicon substrate, there is an SOI (silicon on insulator) substrate in which a single crystal silicon layer is formed over a buried insulating layer. The use of an SOI substrate is effective in increasing the speed of a semiconductor integrated circuit and preventing latch-up.

Further, a conventional semiconductor integrated circuit is sometimes formed on a compound semiconductor substrate. A semiconductor integrated circuit formed on a compound semiconductor substrate generally includes an element having characteristics that cannot be achieved by an element formed on a silicon substrate. As an element having such characteristics, for example, there are a transistor having good high-frequency characteristics, a transistor suitable for high-speed operation, a short-wavelength light-emitting diode and a laser diode.

[0004]

The conventional semiconductor integrated circuit is configured as described above, and the active elements of the semiconductor integrated circuit formed on the SOI substrate have higher frequency characteristics.
When high-speed performance is required, compound semiconductor substrate
Although it is desirable to form a semiconductor integrated circuit on the same structure as the OI substrate, there is a first problem that there is no semiconductor substrate formed by forming a crystalline compound semiconductor layer on the buried insulating layer. is there.

In a conventional semiconductor integrated circuit, a first element forming a circuit suitable for a silicon substrate is formed on a silicon substrate, and a second element forming a circuit suitable for a compound semiconductor substrate is formed on a compound semiconductor substrate. Formed. Therefore, there is a second problem that two semiconductor substrates must be used, and it is difficult to improve the degree of integration.

[0008] Therefore, as shown in FIG. 11, for example, two substrates 100 and 101 are required, and a bus for connecting the substrates (for example, a wiring indicated by reference numeral 12 is a part of the bus). There is a third problem that the operation speed as a whole becomes slower. Of course, when the first and second elements are formed on the silicon substrate, and when the first and second elements are formed on the compound semiconductor substrate, the characteristics of the first element or the second element are changed. A problem of deterioration occurs.

The first invention has been made to solve the first problem, and has as its object to improve the operation speed of a semiconductor integrated circuit by forming a compound semiconductor layer on an insulating layer. And

The second invention has been made to solve the second and third problems, and provides a substrate on which a silicon layer and a compound semiconductor layer can be exposed on the same main surface.
By separately forming a first element and a second element suitable for each layer in each layer, a circuit suitable for a silicon substrate and a circuit suitable for a compound semiconductor substrate are formed on one substrate. The purpose is to improve the operation speed.

[0009]

A semiconductor integrated circuit according to a first aspect of the present invention includes a semiconductor substrate having a buried insulating layer and a crystalline compound semiconductor layer formed on the buried insulating layer; And a plurality of active elements formed and operating in association with each other.

A semiconductor integrated circuit according to a second aspect of the present invention is the semiconductor integrated circuit according to the first aspect, wherein the semiconductor substrate includes a seed crystal of the compound semiconductor layer between the buried insulating layer and the compound semiconductor layer. Characterized by further comprising a single-crystal silicon layer.

A semiconductor integrated circuit according to a third invention is the semiconductor integrated circuit according to the second invention, wherein the buried insulating layer is a buried insulating layer of an SOI substrate, and the single-crystal silicon layer is It is an SOI layer.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a base having one main surface of crystalline silicon; a crystalline compound semiconductor layer selectively formed on the one main surface of the base; A first element is formed on one main surface of the base, and a second element is formed on the compound semiconductor layer and performs an active operation in relation to the first element. .

A semiconductor integrated circuit according to a fifth aspect of the present invention is the semiconductor integrated circuit according to the fourth aspect, wherein the base is made of SO
An SOI substrate, wherein the crystalline silicon is an SOI layer of the SOI substrate.

A semiconductor integrated circuit according to a sixth aspect is the semiconductor integrated circuit according to the fourth or fifth aspect, wherein an insulator for electrically isolating the first element and the second element is provided. In addition, it is configured.

A semiconductor integrated circuit according to a seventh invention is the semiconductor integrated circuit according to the sixth invention, wherein the insulator is a silicon oxide film formed below the compound semiconductor layer and on the base. It is characterized by the following.

The semiconductor integrated circuit according to an eighth aspect is the semiconductor integrated circuit according to the fifth aspect, wherein the first element and the second element are electrically separated in the SOI layer of the SOI substrate. Further provided with an insulator.

A semiconductor integrated circuit according to a ninth aspect is the semiconductor integrated circuit according to any one of the fourth to eighth aspects, wherein the first element is a component of a digital circuit, and the second element is Is a component of an analog circuit.

A wafer according to a tenth aspect includes a buried insulating layer and a crystalline compound semiconductor layer formed on the buried insulating layer.

The wafer according to the eleventh invention has a tenth aspect.
The wafer according to the invention, further comprising a single crystal silicon layer disposed on the buried insulating layer and being a seed crystal of the compound semiconductor layer.

The wafer according to the twelfth aspect is the eleventh aspect.
In the wafer according to the invention, the buried insulating layer is formed of S
It is a buried insulating layer of an OI wafer, and the single crystal silicon layer is an SOI layer of the SOI wafer.

[0021] A wafer according to a thirteenth aspect includes a substrate having one main surface of crystalline silicon, and a crystalline compound semiconductor layer selectively formed on the one main surface of the substrate. Be composed.

The wafer according to the fourteenth invention is the thirteenth invention.
In the wafer according to the aspect of the invention, the base is an SOI substrate, and the crystalline silicon is an SOI substrate of the SOI substrate.
It is an I layer.

The wafer according to the fifteenth invention is the thirteenth invention.
Alternatively, in the wafer according to a fourteenth aspect, the wafer further comprises an insulator for electrically separating the compound semiconductor layer and the portion of the base exposed on the one main surface.

The wafer according to the sixteenth invention is the fifteenth invention.
In the wafer according to the invention, the insulator is a silicon oxide film formed below the compound semiconductor layer and on the base.

A semiconductor integrated circuit according to a seventeenth aspect of the present invention comprises:
In a semiconductor integrated circuit according to a fifteenth aspect, the semiconductor device further includes an insulator in the SOI layer of the SOI substrate for electrically separating the first element and the second element.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a semiconductor integrated circuit according to the first embodiment and a wafer used for forming the semiconductor integrated circuit will be described. FIG. 1 is a diagram showing a cross-sectional structure of a wafer (semiconductor substrate) on which a semiconductor integrated circuit according to the first embodiment is formed. The plurality of transistors 21 formed in the crystalline compound semiconductor layer 5 include:
Active elements that operate in conjunction with each other. Embodiment 1
The semiconductor integrated circuit of the present invention has such a plurality of transistors 2
1 is formed. Although not shown in FIG. 1, the plurality of transistors 21 are connected by wiring formed on the wafer 1. When the operation speed of these transistors 21 is improved, the operation speed of the semiconductor integrated circuit is improved.

Next, a wafer on which the semiconductor integrated circuit of FIG. 1 is formed will be described. A buried insulating layer 3 is formed of silicon oxide in a silicon substrate 2. On the buried insulating layer 3, a silicon epitaxial layer 4 is formed. A single-crystal compound semiconductor layer 5 is formed on the single-crystal silicon epitaxial layer 4. As described above, in the semiconductor substrate 1 including the silicon substrate 2, the buried insulating layer 3, the silicon epitaxial layer 4, and the compound semiconductor layer 5, an active element is formed using the compound semiconductor layer 5. One example of the compound semiconductor layer 5 is a gallium arsenide (GaAs) layer. In this case, for example, the buried insulating layer 3 is 4000 angstroms, and the silicon epitaxial layer 4 is 2000-3.
The thickness of the compound semiconductor layer 5 made of GaAs and 000 Å is 3 to 4 μm. Here, the silicon epitaxial layer 4 is formed as a seed crystal for crystal-growing the compound semiconductor layer 5, and with such a configuration, a wafer having a larger area than a wafer consisting of only a compound semiconductor can be used. It can be used and is suitable for mass production. As the silicon epitaxial layer 4, an SOI layer of an SOI wafer can be used. In that case, the commonly used off-the-shelf SO
The use of an I-wafer can simplify the manufacturing process. The silicon epitaxial layer 4 used as a seed crystal
Does not need to have a thickness capable of forming an element, but only needs to have a sufficient thickness on which the compound semiconductor layer 5 can be grown.

Various methods have been proposed for epitaxially growing GaAs on a single crystal silicon substrate. For example, a GaAs layer can be formed on the silicon epitaxial layer 5 under the following conditions. GaAs
The conditions for growing s are as follows: (1,0,
0) A crystal is grown on an SOI substrate having a silicon layer whose main surface is a plane, the substrate temperature during crystal growth is 560 ° C., the growth rate is 1 μm / hour, and the AsH ₃ gas pressure is 7 × 10 ⁻⁷ Torr.
It is.

FIG. 2 is a graph showing a simulation result of a source-drain current and a gate voltage in the MOS transistor as the transistor 21 of FIG. In FIG. 2, the vertical axis and the horizontal axis compare the magnitudes of the characteristic values of the MOS transistors, and do not have a specific unit. Note that the vertical axis is logarithmic. The MOS transistors compared in FIG. 2 are a MOS transistor formed on a single crystal silicon substrate, a MOS transistor formed on an SOI substrate, and a semiconductor substrate 1 shown in FIG.
This is the MOS transistor formed above. The characteristics of the MOS transistors on the silicon substrate are indicated by solid lines with reference numeral 6, the characteristics of the MOS transistors on the SOI substrate are indicated by reference numeral 7, and the characteristics of the MOS transistors on the semiconductor substrate 1 are reference numeral 8. It is shown. As shown in FIG. 2, the gate voltage applied to flow the same source / drain current is the smallest for the MOS transistor on the semiconductor substrate 1, and the operation of the semiconductor integrated circuit including the MOS transistor on the semiconductor substrate 1 It can be seen that the speed is increased. That is, a semiconductor integrated circuit formed on an SOI substrate is more suitable for high-speed operation than a semiconductor integrated circuit formed on a single crystal silicon substrate. The semiconductor integrated circuit built on the semiconductor substrate formed in
The operation speed can be further improved as compared with a semiconductor integrated circuit formed on an SOI substrate.

The silicon epitaxial layer 4 shown in FIG.
It has been confirmed that the operation speed is improved even if there is no, as compared with the case of reference numeral 7 in FIG. Therefore, in the semiconductor integrated circuit of FIG. 1, the compound semiconductor layer 5 is formed on the silicon epitaxial layer 4, but the compound semiconductor layer 5 is directly formed on the buried insulating layer 3 by using a conventionally known molecular beam epitaxy method. It is also possible to epitaxially grow the crystalline compound semiconductor layer 5. In that case, for example, a compound semiconductor seed crystal is formed over the entire surface of the buried insulating layer 3 by a molecular beam epitaxy method, and then the compound semiconductor layer 5 is epitaxially grown. Note that as the compound semiconductor to be epitaxially grown on the single crystal silicon layer, Ga
In addition to As, there are indium phosphide (InP), silicon germanium (SiGe), and the like.

Embodiment 2 Next, a semiconductor integrated circuit according to a second embodiment and a wafer used for forming the semiconductor integrated circuit will be described. FIG. 3 is a cross-sectional view illustrating a configuration of the semiconductor integrated circuit according to the second embodiment. In the semiconductor integrated circuit of FIG. 3, a transistor 20 is formed using the SOI layer 9, and a transistor 21 is formed using the single crystal compound semiconductor layer 5 made of GaAs. That is, the transistor 20 is a first element formed in a crystalline silicon layer, the transistor 21 is formed in a crystalline compound semiconductor layer, and a second element which performs an active operation in relation to the first element. Device. Here, the term “operate in relation” means that the first and second elements operate together to perform a desired function of the semiconductor integrated circuit during the operation of the semiconductor integrated circuit.
Assuming that the transistor 21 and the transistor 20 are the same type of transistor, for example, a MOS transistor,
While the transistor 21 operates faster than the transistor 20, the transistor 20 operates with lower power consumption and lower noise than the transistor 21. In a semiconductor integrated circuit, a transistor 21 configured by using the compound semiconductor layer 5 is used for a circuit portion that requires high-speed operation, and an SOI layer 9 is used for a circuit portion that requires low power consumption and low noise. The use of the transistor 20 configured as described above makes it possible to increase the speed of the entire semiconductor integrated circuit formed on one semiconductor substrate, and simultaneously realize low power consumption and low noise. As described above, the degree of integration can be improved by being formed on one semiconductor substrate, and the occupied area can be reduced as compared with the case where the semiconductor device is formed with two semiconductor substrates. Further, as compared with the case where the transistor 20 and the transistor 21 are formed on two semiconductor substrates, for example, the distance of the bus connecting the different semiconductor substrates 100 and 101 does not pass through the wiring 12 as shown in FIG. The operating speed of the semiconductor integrated circuit is improved. Further, power consumption due to the presence of the wiring 12 can be reduced.

FIG. 4 is a block diagram showing an example of the semiconductor integrated circuit according to the second embodiment. The semiconductor integrated circuit of FIG. 4 is, for example, a semiconductor device for a mobile phone. The baseband unit 43 is a circuit unit that performs a digital operation for processing a baseband signal, and requires low power consumption and low noise. This baseband section 43
Is formed using the SOI layer 9. On the other hand, the switch section 40, the reception section 41, and the transmission section 42 are circuit sections that perform analog operation and require high-speed element operation, and are formed using the compound semiconductor layer 5. . The switch unit 40, the receiving unit 41, the transmitting unit 42, and the baseband unit 43 are connected by wiring formed on one semiconductor substrate 100. Therefore, the switch unit 4
0, at least one of the receiving unit 41 and the transmitting unit 42 and the baseband unit 43 are connected by a short bus, and the operation of the semiconductor integrated circuit is accelerated.

Next, the wafer 1A (semiconductor substrate) on which the semiconductor integrated circuit of FIG. 3 is formed will be described. The compound semiconductor layer 5 of the wafer 1A is made of, for example, gallium arsenide (G
aAs), and has a thickness of, for example, 3 to 4 μm. The compound semiconductor layer 5 is formed on an SOI layer 9 having a thickness of, for example, 3 to 4 μm with a silicon oxide film 10 interposed therebetween. Below the SOI layer 9, for example, 4000
There is a buried insulating layer 3 having a thickness of Angstrom, and a silicon substrate 2 thereunder. Here, the compound semiconductor layer 5 and the SOI layer 9 are insulated by the silicon oxide film 10, so that crosstalk between the transistors 20 and 21 can be reduced.

FIGS. 5 to 8 are views showing a cross-sectional structure of the wafer 1A during the manufacturing process of the wafer 1A shown in FIG. First, S having a silicon oxide film 10 on the surface
A member as shown in FIG. 5, in which a compound semiconductor layer 5 made of GaAs single crystal is formed on the entire surface of the SOI layer 9 of the OI wafer, is prepared. Silicon oxide film 10
In order to form the compound semiconductor layer 5 thereon, for example, a molecular beam epitaxy method is used. Single crystal compound semiconductor layer 5 on seed crystal formed by molecular beam epitaxy
Is epitaxially grown. Next, a resist 30 is formed on the compound semiconductor layer 5 to be left after the etching (see FIG. 6). Using the resist 7 as a mask, etching is performed using chlorine (Cl ₂ ) -based plasma to expose the silicon oxide film 10 (see FIG. 7). By removing the silicon oxide film 10 and the resist 30, S
The OI layer 9 is exposed, and the wafer 1A used to form the semiconductor integrated circuit of FIG. 1 is obtained (see FIG. 8). Each element formed on the wafer 1A is formed by applying a method conventionally formed on an SOI substrate and a method formed on a compound semiconductor substrate.

In the second embodiment, the SOI layer 9
Although the compound semiconductor layer 5 is formed on the substrate 1, a wafer 1B in which the compound semiconductor layer 5 is selectively formed on the single crystal silicon substrate 2 as shown in FIG. Has the effect of

In the second embodiment, the compound semiconductor layer 5 is formed on the silicon oxide film 10.
As shown in FIG. 1, a wafer 1 in which a compound semiconductor layer 5 is selectively formed directly on an SOI layer 9 by epitaxial growth.
C may be used, and the same effects as in the above embodiment can be obtained. In this case, an element formed on the compound semiconductor layer 5 and an element formed on the SOI layer 9 cooperate with the buried insulating layer 3 in order to avoid crosstalk between the transistors 20 and 21. It is desirable to provide an insulator 11 for electrical isolation. Further, a field oxide film may be used as silicon oxide film 10 of wafers 1A and 1B of the second embodiment.

[0037]

As described above, according to the semiconductor integrated circuit of the first aspect, the operating speed of the plurality of active elements formed in the compound semiconductor layer is improved, so that the operating speed is improved. is there.

According to the semiconductor integrated circuit of the second aspect,
There is an effect that a semiconductor integrated circuit having a structure suitable for mass production can be obtained.

According to the semiconductor integrated circuit of the third aspect,
An off-the-shelf SOI wafer that is usually used can be used, and the manufacturing process can be simplified.

According to the semiconductor integrated circuit of the fourth aspect,
The first element and the second element can be formed on one base, which has an effect of improving the degree of integration. Then, the first element and the second element can be connected by a short wiring, and the operation speed of the semiconductor integrated circuit can be improved.

According to the semiconductor integrated circuit of the fifth aspect,
An off-the-shelf SOI wafer that is usually used can be used, and the manufacturing process can be simplified.

According to the semiconductor integrated circuit of the present invention, since the first element and the second element are separated by the insulator, crosstalk between the elements can be reduced. This has the effect.

According to the semiconductor integrated circuit of the seventh aspect,
There is an effect that crosstalk between the first element and the second element can be reduced with a simple configuration of a silicon oxide film.

According to the semiconductor integrated circuit of the ninth aspect,
By utilizing the features of the first and second elements, it is possible to obtain a configuration in which the operation speed can be easily improved.

According to the tenth aspect of the present invention, for example, when a semiconductor integrated circuit including active elements is formed on the wafer, there is an effect that a semiconductor integrated circuit with an improved operation speed can be easily obtained.

According to the wafer of the eleventh aspect, there is an effect that a large-area wafer can be easily obtained.

According to the twelfth aspect of the invention, an off-the-shelf SOI wafer that is normally used can be used, and the production process can be simplified.

According to the wafer of the thirteenth aspect, by forming elements suitable for the silicon layer and the compound semiconductor layer, respectively, compared with the case of forming elements suitable for the silicon substrate and the compound semiconductor substrate, respectively. (1) The first element and the second element can be formed on one base, and the degree of integration can be improved. Then, these elements can be connected with a short wiring, and the operation speed of the semiconductor integrated circuit formed on the wafer can be improved.

According to the wafer of the fourteenth aspect, an off-the-shelf SOI wafer that is usually used can be used, and the production process can be simplified.

According to the wafer of the fifteenth aspect, there is an effect that crosstalk between the device formed in the silicon layer and the device formed in the compound semiconductor layer can be reduced.

According to the wafer of the sixteenth aspect, there is an effect that the crosstalk between the first element and the second element can be reduced with a simple structure of the recon oxide film.

According to the wafer of the seventeenth aspect, there is an effect that a wafer capable of reducing the crosstalk between the device formed in the silicon layer and the device formed in the compound semiconductor layer can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a semiconductor integrated circuit according to a first embodiment;

FIG. 2 is a graph for explaining operation characteristics of the transistor of FIG.

FIG. 3 is a sectional view illustrating a semiconductor integrated circuit according to a second embodiment;

FIG. 4 is a block diagram illustrating an example of a semiconductor integrated circuit according to a second embodiment;

FIG. 5 is a cross-sectional view for illustrating a manufacturing step of the semiconductor integrated circuit according to the second embodiment.

FIG. 6 is a cross-sectional view for illustrating a manufacturing step of the semiconductor integrated circuit according to the second embodiment.

FIG. 7 is a cross-sectional view for illustrating a manufacturing step of the semiconductor integrated circuit according to the second embodiment.

FIG. 8 is a cross-sectional view for illustrating a manufacturing step of the semiconductor integrated circuit according to the second embodiment.

FIG. 9 is a sectional view illustrating a semiconductor integrated circuit according to a second embodiment;

FIG. 10 is a sectional view illustrating a semiconductor integrated circuit according to a second embodiment;

FIG. 11 is a perspective view illustrating a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1, 1A, 1B, 1C wafer, 2 semiconductor substrate, 3
Buried insulating layer, 4 silicon epitaxial layer, 5
Compound semiconductor layer, 9 SOI layers, 20, 21 transistors.

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Claims (17)

[Claims] A semiconductor substrate having a buried insulating layer and a crystalline compound semiconductor layer formed on the buried insulating layer; and a plurality of active elements formed in the compound semiconductor layer and operating in association with each other. Semiconductor integrated circuit. 2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate further includes a single crystal silicon layer which is a seed crystal of the compound semiconductor layer, between the buried insulating layer and the compound semiconductor layer. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said buried insulating layer is a buried insulating layer of an SOI substrate, and said single-crystal silicon layer is an SOI layer of said SOI substrate. 4. A base having one main surface of crystalline silicon, a crystalline compound semiconductor layer selectively formed on the one main surface of the base, and a first compound formed on one main surface of the base. And a second element formed in the compound semiconductor layer and performing an active operation in association with the first element. 5. The semiconductor integrated circuit according to claim 4, wherein said base is an SOI substrate, and said crystalline silicon is an SOI layer of said SOI substrate. 6. The semiconductor device according to claim 4, further comprising an insulator for electrically separating said first element and said second element.
Or a semiconductor integrated circuit according to claim 5. 7. The semiconductor integrated circuit according to claim 6, wherein said insulator is a silicon oxide film formed under said compound semiconductor layer and on said base. 8. The method according to claim 1, wherein the first layer is formed in an SOI layer of the SOI substrate.
6. The semiconductor integrated circuit according to claim 5, further comprising an insulator for electrically separating said element from said second element. 9. The method according to claim 4, wherein the first element is a component of a digital circuit, and the second element is a component of an analog circuit. 2. The semiconductor integrated circuit according to claim 1. 10. A wafer comprising: a buried insulating layer; and a crystalline compound semiconductor layer formed on the buried insulating layer. 11. The wafer according to claim 10, further comprising a single-crystal silicon layer disposed on the buried insulating layer and being a seed crystal of the compound semiconductor layer. 12. The buried insulating layer is a buried insulating layer of an SOI wafer, and the single crystal silicon layer is a SOI wafer of the SOI wafer.
The wafer of claim 11, wherein the wafer is a layer. 13. A wafer comprising: a base having one main surface of crystalline silicon; and a crystalline compound semiconductor layer selectively formed on the one main surface of the base. 14. The wafer according to claim 13, wherein the base is an SOI substrate, and the crystalline silicon is an SOI layer of the SOI substrate. 15. The wafer according to claim 13, further comprising an insulator for electrically separating said compound semiconductor layer and a portion of said base exposed on said one main surface. 16. The semiconductor device according to claim 15, wherein the insulator is a silicon oxide film formed below the compound semiconductor layer and on the base.
The described wafer. 17. The wafer according to claim 15, further comprising an insulator in the SOI layer of the SOI substrate for electrically separating the first element and the second element.