JP2000183161A - Manufacture of electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for manufacturing electronic device having a multilayer wiring and to improve the manufacturing yield. SOLUTION: A CMOS transistor is formed on an Si substrate 2, and an interlayer insulation film 22, having wiring grooves 23, 24 in the upper part thereof via a BPSG film 17 for manufacturing a first substrate 1, while after a three-layer wiring is formed on a glass substrate 31, wirings 54, 55 having pattern shapes with mirror image relation with the pattern shapes of the grooves 23, 24 are formed to manufacture a second substrate 30. After the first substrate 1 and the second substrate 30 are interposed in such a way that they face each other to embed the wiring 54, 55 in the grooves 23, 24, the first and second substrates are heated, and then they are bonded. A glass substrate 31 is removed from the second substrate by etching a film 32 for removal, so that a CMOSLSI is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic device, and more particularly, to an ASIC (Application Specific Insulator).
It is suitable for application to the manufacture of a semiconductor device having a multilayer wiring such as an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in the manufacture of a semiconductor device having a multilayer wiring, a thin film is formed on a semiconductor substrate such as a transistor or the like on which a semiconductor element or an element isolation region is formed by a thermal oxidation method or a chemical vapor deposition (CVD) method. Is formed, a part of the thin film is removed by a lithography process and an etching process, and ion implantation or thermal diffusion of impurities is performed as necessary.
Further, a series of steps of forming a thin film in an upper layer is sequentially repeated to form a wiring sequentially from a lowermost layer to an uppermost layer, thereby forming a multilayer wiring.

The following method is known as a method of manufacturing a semiconductor device having a multilayer wiring, in addition to a method of forming a multilayer wiring by sequentially forming a wiring above a semiconductor element.

That is, first, a semiconductor element such as a transistor and an element isolation region are formed on a first semiconductor substrate. At the same time, a multi-layer wiring is formed by sequentially forming an interlayer insulating film, a plug, and a wiring of a predetermined pattern on the second semiconductor substrate from the lowermost layer to the uppermost layer. Next, the multilayer wiring is peeled from the second semiconductor substrate. Then, the lower surface of the peeled multilayer wiring is bonded to the upper surface of the first semiconductor substrate in accordance with the pattern. Thus, a semiconductor device having a multilayer wiring is manufactured.

[0005] By adopting such a method,
The formation of the semiconductor element or element isolation region and the formation of the multilayer wiring can be performed separately. Therefore, there is an advantage that the time required for manufacturing a semiconductor device can be significantly reduced.

[0006]

However, the multilayer wiring is separated from the second semiconductor substrate, and the multilayer wiring is removed from the first semiconductor substrate.
In order to align and bond the pattern on the upper surface of the semiconductor substrate, it is necessary to maintain the multilayer wiring as it is after being peeled off from the second semiconductor substrate. However, even when the multilayer wiring is actually peeled off from the second semiconductor substrate, and the multilayer wiring is bonded to the upper surface of the first semiconductor substrate with the pattern aligned, the multilayer wiring is maintained in the state at the time of formation. This is extremely difficult, and it can be seen that deviation occurs.

For this reason, the multilayer wiring can be maintained as it is when it is formed, and can be accurately bonded to the upper surface of a predetermined substrate, and the time required for manufacturing an electronic device such as a semiconductor device having the multilayer wiring can be reduced. The development of technology that can do this is desired.

Accordingly, an object of the present invention is to provide a method of manufacturing an electronic device capable of shortening the time required for manufacturing an electronic device having multilayer wiring and improving the manufacturing yield. It is in.

[0009]

In order to achieve the above object, the present invention relates to a method of manufacturing an electronic device in which an M-layer wiring is provided on a substrate provided with an electronic device, and the method comprises the steps of: One main surface of the first substrate having N layers less than M layers excluding the local wiring of the electronic element provided above, a supporting substrate, and (M−
(N) The semiconductor device is characterized in that it is bonded to one main surface of a second substrate having wiring of a layer (N).

[0010] In the present invention, the N layer and the M layer are
≤N <M (N and M are integers).

In the present invention, typically, an insulating film having a groove is provided on one principal surface of the first substrate, and a pattern shape of the groove of the insulating film of the first substrate and an insulating film having a groove on the second substrate. The wiring pattern of the upper layer has a mirror image relationship with each other, and the wiring of the uppermost layer is fitted in the groove so that one main surface of the first substrate and one main surface of the second substrate are bonded to each other. . Further, in the present invention, in order to favorably insert the wiring of the second substrate into the groove of the insulating film of the first substrate, preferably, the insulating film provided on one main surface of the first substrate is formed. A guide part is provided on the upper part of the groove. This guide portion has, for example, a tapered shape.

Further, in the present invention, in order to electrically connect the local wiring of the electronic element on the first substrate and / or the wiring of the N layer and the wiring of the (MN) layer of the second substrate, Typically, after the uppermost layer wiring of the second substrate is inserted into the groove of the insulating film of the first substrate, the first substrate and the second substrate are heated.

In the present invention, in order to electrically connect the local wiring of the electronic element on the first substrate and / or the wiring of the N layer and the wiring of the (MN) layer of the second substrate, Typically, the wiring of the uppermost layer of the second substrate is fitted into the groove of the insulating film of the first substrate while heating the first substrate and the second substrate.

In the present invention, typically, an insulating film having a groove is provided on one main surface of the second substrate, and the wiring pattern of the uppermost layer of the first substrate and the insulating film of the second substrate are formed. The pattern shapes of the grooves of the film are in a mirror image relationship with each other, and the wiring of the uppermost layer is fitted in the grooves so that one main surface of the first substrate and one main surface of the second substrate are bonded to each other. . Further, in the present invention, in order to satisfactorily insert the wiring of the first substrate into the groove of the insulating film of the second substrate, preferably, the insulating film provided on one main surface of the second substrate is formed. A guide part is provided on the upper part of the groove. This guide portion has, for example, a tapered shape.

In the present invention, the local wiring of the electronic element and / or the wiring of the N layer on the first substrate may include:
In order to electrically connect to the wiring of the (MN) layer of the second substrate, typically, the first groove is formed in the groove of the insulating film of the second substrate.
After the wiring of the uppermost layer of the substrate is inserted, the first substrate and the second substrate are heated.

Further, in the present invention, the local wiring of the electronic element and / or the wiring of the N layer on the first substrate;
In order to electrically connect the wiring of the (MN) layer of the second substrate, typically, the first substrate and the second substrate are heated while the insulating film of the second substrate is heated. The uppermost layer wiring of the first substrate is fitted into the groove.

In the present invention, typically, after bonding one main surface of the first substrate and one main surface of the second substrate,
The supporting substrate is removed from the second substrate.

In the present invention, in order to easily align the first substrate and the second substrate, the second substrate preferably reflects at least the main surface of the first substrate. It is made of a material that transmits light. Specifically, a plurality of first alignment marks are provided at predetermined positions of the first substrate, and the first alignment mark is formed on the second substrate. A plurality of second alignment marks are provided at positions that are in a mirror image relationship with the predetermined position of the first substrate, and after the one main surface of the first substrate and the one main surface of the second substrate are arranged to face each other. By irradiating light from the back side of the second substrate and observing light reflected on one principal surface of the first substrate, the first
And the second substrate are aligned.

In the present invention, the wiring used for the multilayer wiring is specifically copper (Cu), aluminum (A
1), gold (Au), tungsten (W), silver (Ag) and the like.

According to the method of manufacturing the electronic device according to the present invention having the above-described structure, the N-layer wirings of less than M layers, excluding the local wiring of the electronic element, provided on the electronic element and the electronic element are formed. An electronic device by bonding one main surface of the first substrate having the first substrate and one main surface of the second substrate having the support substrate and the wiring of the (MN) layer provided on the support substrate. Accordingly, in the manufacture of the electronic device, the formation of the electronic element and the formation of the multilayer wiring can be performed in parallel.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding portions are denoted by the same reference numerals.

A method of manufacturing a CMOS LSI having four layers of wiring according to the first embodiment of the present invention will be described.

First, the first substrate 1 on which a semiconductor element is formed will be described below. 1 to 3 show a method of manufacturing the first substrate 1 according to the first embodiment.

That is, as shown in FIG. 1, by selectively ion-implanting an n-type impurity such as phosphorus (P) into a predetermined portion of the upper portion of the silicon (Si) substrate 2,
An n-type well region 3 is formed. Subsequently, a p-type well region 4 is formed by selectively ion-implanting a p-type impurity such as boron (B). After that, a field oxide film 5 is formed on the Si substrate 2 by, for example, the LOCOS method to perform element isolation.

Next, gate oxide films 6 and 7 are formed in the active region on the surface of the Si substrate 2 by, for example, a thermal oxidation method. next,
After a polycrystalline Si film doped with, for example, P is formed on the entire surface by, for example, a CVD method, the gate electrodes 8 and 9 are formed by patterning the polycrystalline Si film into a predetermined shape.

Next, using the gate electrode 9 as a mask, an n-type impurity such as P is ion-implanted into the p-type well region 4 to form a low-concentration n ^- type source / drain region in the n-channel MOS transistor. Is formed. Subsequently, p-type impurities such as B are ion-implanted into the n-type well region 3 using the gate electrode 8 as a mask, so that the p ⁻ -type semiconductor region 11 becomes a low-concentration source / drain region in the p-channel MOS transistor. To form

Next, a silicon oxide (SiO ₂ ) film is formed on the entire surface by, eg, CVD. Thereafter, spacers 12 and 13 made of SiO ₂ are formed on the side walls of the gate electrodes 8 and 9 by performing, for example, the entire surface etch back by the reactive ion etching (RIE) method.

Next, for example, arsenic (As) is formed in the p-type well region 4 using the gate electrode 9 and the spacer 13 as a mask.
By implanting n-type impurities such as ions, an n ⁺ -type semiconductor region 14 serving as a high-concentration source / drain region in the n-channel MOS transistor is formed. Subsequently, ions of a p-type impurity such as B are ion-implanted into the n-type well region 3 using the gate electrode 8 and the spacer 12 as a mask, thereby forming a p ⁺ -type source / drain region having high concentration in the p-channel MOS transistor. Of the semiconductor region 15 is formed.

Next, as shown in FIG. 2, an SiO ₂ film 16 and a boron phosphorus silicate glass (BPSG) film 17 are sequentially formed on the first substrate 1 by, for example, a CVD method. Thereafter, 850 to 95 in a nitrogen (N ₂ ) gas atmosphere.
By heating to a temperature of 0 ° C., the surface of the BPSG film 17 is flattened.

Next, a resist pattern (not shown) having an opening at a predetermined position is formed on the BPSG film 17, and the BPSG film 17 and the SiO ₂ film 16 are sequentially etched using the resist pattern as a mask. Thereby, the semiconductor region 1 of the n-channel MOS transistor
SiO ₂ film 16 and BPSG film 17 in a portion above semiconductor region 15 of semiconductor device 4 and p-channel MOS transistor
Then, contact holes 18 and 19 are formed, respectively.

Next, after a tungsten (W) film is formed on the entire surface by, for example, blanket CVD, for example, RI
The contact plugs 20 and 21 made of W are buried in the contact holes 18 and 19 by performing the entire surface etch back by the E method.

Next, as shown in FIG. 3, an interlayer insulating film 22 made of, for example, an SiO ₂ film is formed on the entire surface by, for example, a plasma CVD method. The thickness of the interlayer insulating film 22 is, for example, 500 nm. Here, as an example of the CVD conditions for forming the interlayer insulating film 22, for example, a TEOS (tetraethoxysilane) gas is used as a reaction gas, and the substrate heating temperature is, for example, 400 ° C.

Next, after a resist pattern (not shown) having a predetermined shape is formed on the interlayer insulating film 22, the resist pattern is used as a mask until the surfaces of the contact plugs 20 and 21 are exposed by, eg, RIE. The insulating film 22 is etched. Thereby, the interlayer insulating film 22
Wiring grooves 23 and 24 are formed at predetermined portions of the wiring. here,
The width of these wiring grooves 23 and 24 is about 1.2 times the wiring width of the wiring to be inserted into these wiring grooves 23 and 24 described later. For example, when the wiring width of the wiring to be inserted into the wiring grooves 23 and 24 is about 300 nm, the width of the wiring grooves 23 and 24 is about 360 nm.

Next, the surface of the interlayer insulating film 22 in which the wiring grooves 23 and 24 are formed is cleaned by, for example, a sputter etching method. Here, in this sputter etching method, for example, Ar gas is used as an etching gas, RF power is set to 1 kW, and 10
Etching equivalent to nm is performed.

Next, a good ohmic characteristic with a tantalum (Ta) film as a diffusion preventing film for preventing diffusion of Cu and a wiring on a second substrate to be described later is obtained on the entire surface by, for example, a sputtering method. Cu / Ta by sequentially forming a Cu film as an adhesion film for
A film 25 is formed. Each of the Ta film and the Cu film has a thickness of, for example, 50 nm. Note that a tantalum nitride (TaN) film can be used instead of the Ta film.

Next, the Cu / Ta film 25 on the upper surface of the interlayer insulating film 22 is removed by, for example, a chemical mechanical polishing (CMP) method, whereby the Cu / Ta film 25 is formed on the bottom surfaces and the side walls of the wiring grooves 23 and 24. Will be left.

As described above, the first substrate 1 provided with the semiconductor element according to the first embodiment is manufactured.

Next, a second substrate 30 having four layers of wiring
A method of manufacturing the device will be described. 4 to 7 show a method of manufacturing the second substrate 30 according to the first embodiment.

That is, as shown in FIG. 4, a peeling film 32 made of, for example, an SiO ₂ film is formed on a glass substrate 31 serving as a supporting substrate by, for example, a plasma CVD method.
The thickness of the peeling film 32 is, for example, 1.0 μm. Here, as an example of the CVD conditions in forming the peeling film 32, a TEOS gas is used as a reaction gas, and the substrate heating temperature is 400 ° C.

Next, an overcoat film 33 made of, for example, a silicon nitride (SiN) film and an interlayer insulating film 34 are sequentially formed on the entire surface of the peeling film 32 by, for example, a plasma CVD method. The thickness of each of the overcoat film 33 and the interlayer insulating film 34 is, for example, 1 μm. The overcoat film 33 and the interlayer insulating film 3
The substrate heating temperature in forming 4 is, for example, 400 ° C.

Next, a resist pattern (not shown) having a mirror image and a desired wiring pattern is formed on the interlayer insulating film 34, and the resist pattern is used as a mask to form an interlayer insulating film by, for example, a plasma etching method. The film 34 is etched. Thus, a wiring groove 35 having a desired wiring shape and a mirror image pattern shape is formed in the interlayer insulating film 34. Each of the width and the depth of the wiring groove 35 is, for example, 1 μm. Thereafter, a diffusion preventing film 36 made of, for example, Ta or TaN is formed on the entire surface by, for example, a sputtering method.

Next, a Cu film having a thickness of, for example, 200 nm is formed on the entire surface by, for example, a sputtering method. Subsequently, a Cu film having a thickness of, for example, 1.3 μm is formed on the entire surface so as to be embedded in the wiring groove 35 by, for example, a plating method. Next, the Cu film and the diffusion prevention film 36 in portions other than the inside of the wiring groove 35 are sequentially polished and removed by, for example, a CMP method. As a result, a trench wiring 37 made of Cu having a pattern shape in a mirror image relationship with a desired wiring shape is formed using the diffusion prevention film 36 as a base film.

Next, as shown in FIG. 5, by a plasma CVD method using a TEOS gas as a reaction gas, for example,
An interlayer insulating film made of a SiO ₂ film is formed on the interlayer insulating film and the trench wiring 37. Next, a connection hole 39 and a wiring groove 40 are formed in the interlayer insulating film 38 by sequentially performing a lithography process and an etching process. Subsequently, a diffusion prevention film 41 made of, for example, Ta or TaN is formed on the entire surface by, for example, a sputtering method. Next, formation of a Cu film by, for example, a sputtering method and formation of a Cu film by, for example, a plating method are sequentially performed, and the connection holes 39 and the wiring grooves 40 are filled with Cu. After that, the Cu film and the diffusion prevention film 41 in portions other than the inside of the connection hole 39 and the wiring groove 40 are sequentially polished and removed by, for example, a CMP method. As a result, the plug 42 and the trench wiring 43 made of Cu are formed (Dual Damascene method).

Thereafter, the groove wiring forming process from the formation of the interlayer insulating film 38 to the formation of the plugs 42 and the groove wirings 43 is sequentially repeated a predetermined number of times. Here, in this trench wiring forming step, if the desired number of wiring layers is M, (M−
2) Do it twice. That is, in the first embodiment, since the number of desired wiring layers is four, the groove wiring forming step is performed twice in total. Thereby, as shown in FIG. 6, on the interlayer insulating film 38 and the trench wiring 43, the interlayer insulating film 4
4. A connection hole 45, a wiring groove 46, a diffusion prevention film 47, a plug 48, and a groove wiring 49 are sequentially formed.

Next, as shown in FIG. 7, an interlayer insulating film 50 made of a SiO ₂ film is formed on the entire surface by, for example, a plasma CVD method. The thickness of the interlayer insulating film 50 is, for example, 0.7 μm. Here, as an example of the CVD conditions in forming the interlayer insulating film 50, for example, a TEOS gas is used as a reaction gas, and a substrate heating temperature is set to, for example, 40.
0 ° C. Next, after forming a resist pattern (not shown) having an opening at a portion where a connection hole is formed on the interlayer insulating film 50 by a lithography process, the resist pattern is used as a mask to form the groove wiring 49 by, for example, a plasma etching method. The etching of the interlayer insulating film 50 is performed until the surface is exposed. Thereby, the connection hole 51 is formed. The diameter of the connection hole 51 is, for example, 240 nm.

Next, the surface of the interlayer insulating film 50 is cleaned by, for example, a sputter etching method. In this sputter etching method, for example, Ar gas is used as an etching gas, RF power is set to, for example, 1 kW, and etching equivalent to 10 nm in terms of a thermal oxide film is performed.

Next, in order to prevent diffusion of the Cu film, for example, Ta or Ta
A diffusion prevention film 52 made of N is formed. The thickness of the diffusion prevention film 52 is, for example, 50 nm. Then, for example, C
By the VD method, a Cu film is formed on the entire surface so as to be embedded in the connection hole 51. The thickness of this Cu film is, for example, 150
nm. Next, the Cu film and the diffusion prevention film 52 in portions other than the inside of the connection holes 51 are removed by polishing sequentially by, for example, a CMP method. Thereby, the connection hole 51
A plug 53 made of Cu with the diffusion prevention film 52 as a base is formed inside the substrate.

Next, the surface of the interlayer insulating film 50 on which the plug 53 has been formed is cleaned by, for example, sputter etching. In this sputter etching method,
For example, Ar gas is used as an etching gas, RF power is set to, for example, 1 kW, and etching equivalent to 10 nm in terms of a thermal oxide film is performed.

Next, a diffusion prevention film made of, for example, Ta or TaN, and a Cu film are sequentially formed on the interlayer insulating film 50 by, for example, a sputtering method. The thickness of this Cu film is, for example, 480 nm. Next, on this Cu film, a resist pattern (not shown) having a mirror image-related pattern shape with the wiring grooves 23 and 24 formed in the uppermost interlayer insulating film 22 of the first substrate 1 described above. ) Is formed. Next, using the resist pattern as a mask, the Cu film and the diffusion preventing film are sequentially etched by, for example, a high-temperature plasma etching method. Thereby, the wiring groove 2
3 and 24, each having a mirror image-related pattern shape, and having the diffusion prevention films 54a and 55a as bases, respectively.
U wirings 54 and 55 are formed. These Cu wirings 5
The wiring width of each of the wirings 4 and 55 is, for example, 300 nm.

As described above, the second wiring provided with the multilayer wiring having a pattern shape having a mirror image relationship with the desired wiring shape is provided.
The substrate 30 is manufactured.

Next, a method of bonding the first substrate 1 and the second substrate 30 manufactured as described above will be described.

That is, as shown in FIG.
The substrate 1 is placed so that the bonding surface thereof is on the upper surface, and the second substrate 30 is held above the first substrate 1 such that the bonding surface is on the lower surface.

Next, light is irradiated from the back side of the second substrate 30. Thus, the light passes through the alignment mark 61 provided inside the chip portion 60 in the second substrate 30, and the alignment mark provided inside the semiconductor chip 62 on the first substrate 1. Irradiated at 63. This light is applied to the alignment marks 6 on the first substrate 1.
It is reflected at 3. By observing the reflected light, rough alignment between the first substrate 1 and the second substrate 30 is performed.

Next, the bonding surface of the first substrate 1 and the second
The substrate 30 to be bonded. Then, as shown in FIG. 9, the uppermost interlayer insulating film 2 of the first substrate 1 is formed.
The Cu wirings 54 and 55 formed on the uppermost layer of the second substrate 30 are fitted into the wiring grooves 23 and 24 formed on the second substrate 2, respectively. As a result, precise alignment is performed.

Thereafter, the first substrate 1 and the second substrate 30 are placed in a mixed gas atmosphere in which N ₂ gas and a reducing gas such as hydrogen (H ₂ ) gas are mixed.
It is heated to a temperature of 450 ° C., specifically, for example, 400 ° C. The heating temperature is selected in a range where the material used for the wiring flows on the surface. Thereby, the wiring groove 23,
The Cu film and the Cu wirings 54 and 55 of the Cu / Ta film 25 formed on the bottom and side walls of the 24 are reduced and flow on the surface. Then, the wiring grooves 23, 24 and the Cu wirings 54, 5
5 is filled with the surface-flowed Cu, and the local wiring of the CMOS transistor of the first substrate 1 and the multilayer wiring of the second substrate 30 are electrically connected.

Next, as shown in FIG. 10, the peeling film 32 is etched by, for example, a wet etching method using dilute hydrofluoric acid (HF) to form the first substrate 1.
While leaving the multilayer wiring and the overcoat film 33 thereon,
The glass substrate 31 is peeled off.

As described above, a CMOS LSI in which a predetermined multilayer wiring is provided above a CMOS transistor is manufactured.

As described above, according to the first embodiment, the CMOS transistor is formed on the Si substrate 2 to manufacture the first substrate 1, and the desired multilayer is formed on the glass substrate 31. Since the second substrate 30 is manufactured by forming four layers of wiring having a mirror image-related pattern shape with the wiring, a semiconductor element such as a CMOS transistor and a multilayer wiring can be formed in parallel. CM
The time required for manufacturing an electronic device such as an OSLSI can be significantly reduced. In addition, the multilayer wiring is applied to the glass substrate 3
By attaching the multilayer wiring to the upper surface of the first substrate 1 while holding it at 1, the multilayer wiring on the glass substrate 31 can be maintained as it was at the time of formation, and the multilayer wiring It can be easily attached to the upper surface of the substrate 1. Further, wiring grooves 23 and 24 are provided in the uppermost interlayer insulating film 22 of the first substrate 1, and Cu having a mirror image pattern shape with the wiring groove 23 and 24 pattern is formed in the uppermost layer of the second substrate 30. Wirings 54 and 55 are formed, and Cu wirings 54 and 55 are fitted and fitted in these wiring grooves 23 and 24, respectively.
When bonding the second substrate 30 to the second substrate 30, the difficulty of alignment can be reduced. Also, the second substrate 30
Since the supporting substrate is a glass substrate that transmits light, the light used for alignment can be transmitted through the second substrate 30 and irradiated on the first substrate 1. The alignment with the second substrate 30 can be easily performed. In addition, since the manufacture of the semiconductor element and the manufacture of the multilayer wiring are performed separately, the first substrate 1 is manufactured in large quantities, and the second substrate 30 having the wiring pattern according to the user's request is manufactured. The semiconductor device can be manufactured, the frequency of occurrence of defects and the like in the manufacture of the semiconductor device can be reduced, and the manufacturing yield can be improved when applied to the manufacture of an ASIC or the like.

Next, 5 according to the second embodiment of the present invention.
A method of manufacturing a CMOS LSI having layer wiring will be described.

First, the first substrate 101 having a semiconductor element and two layers of wiring provided thereon will be described. 11 to 13 show a method of manufacturing the first substrate 101 according to the second embodiment.

That is, as shown in FIG.
In the first substrate 101 according to the embodiment, as in the first embodiment, a CMOS transistor, a SiO ₂ film 16, a BPSG film 17, contact holes 18, 19, and contact plugs 20, 21 are formed on a Si substrate 2. , An interlayer insulating film 22, and wiring grooves 23 and 24 are sequentially formed.
Thereafter, the surface of the interlayer insulating film 22 in which the wiring grooves 23 and 24 are formed is cleaned by, for example, a sputter etching method using Ar gas.

Then, for example, Ta or Ta for preventing the diffusion of Cu
An anti-diffusion film made of N is formed. Next, a film thickness of, for example, 200
A Cu film of nm is formed. Next, a Cu film having a thickness of, for example, 1.3 μm is formed so as to be embedded in the wiring grooves 23 and 24 by, for example, a plating method. Next, the Cu film and the diffusion prevention film 102 on the upper surface of the interlayer insulating film 22 are removed by polishing sequentially by, for example, a CMP method. As a result, a trench wiring 103 made of Cu with the diffusion prevention film 102 as a base is formed.

Next, as shown in FIG. 12, for example, S is deposited on the interlayer insulating film 22 and the trench wiring 103 by a plasma CVD method using a TEOS gas as a reaction gas.
An interlayer insulating film 104 made of an iO ₂ film is formed. next,
A resist pattern (not shown) having an opening at a portion where a connection hole is formed on interlayer insulating film 22 by a lithography process
After forming this, using this resist pattern as a mask,
For example, the interlayer insulating film 104 is etched by plasma etching until the surface of the trench wiring 103 is exposed. Thereby, the connection hole 105 is formed.

Next, the surface of the interlayer insulating film 104 in which the connection holes 105 are formed is cleaned by, for example, a sputter etching method.

Next, a diffusion preventing film 106 made of, for example, Ta or TaN is formed on the entire surface by, for example, a sputtering method. The thickness of the diffusion prevention film 106 is, for example, 50 nm. Thereafter, a Cu film is formed by, for example, a CVD method so as to be embedded in the connection holes 105. The thickness of the Cu film is, for example, 150 nm. Then, for example, CMP
According to the method, the Cu film and the diffusion prevention film 106 in portions other than the inside of the connection hole 105 are sequentially polished and removed. As a result, Cu having the diffusion prevention film 106 as a base
Is formed.

Next, the surface of the interlayer insulating film 104 on which the plug 107 is formed is cleaned by, for example, sputter etching.

Next, as shown in FIG. 13, a diffusion preventing film made of, for example, Ta or TaN, and a Cu film are sequentially formed on the interlayer insulating film 104 by, for example, a sputtering method. The thickness of this Cu film is, for example, 480 nm. Next, a resist pattern (not shown) having a predetermined shape is formed on the Cu film. Next, using this resist pattern as a mask, C
The u film and the diffusion prevention film are sequentially etched. As a result, the Cu wirings 108, 10
9 is formed. The wiring width of these Cu wirings 108 and 109 is, for example, 300 nm.

As described above, according to the second embodiment, the first substrate 101 having the semiconductor element and the two-layer wiring provided thereon is manufactured.

Next, the second substrate 11 having three layers of wiring
0 will be described. 14 and 15 show a method for manufacturing the second substrate 110 according to the second embodiment.

That is, as shown in FIG.
In the second substrate 110 according to the second embodiment, the glass substrate 31 serving as a support substrate is similar to the first embodiment.
On top of this, the peeling film 32, the overcoat film 33, the interlayer insulating film 34, the wiring groove 35, the diffusion preventing film 36, and the groove wiring 3
7 are sequentially formed, and a groove wiring forming step similar to that in the first embodiment is repeated twice, whereby the layers from the interlayer insulating film 38 to the plug 48 and the groove wiring 49 are sequentially formed. Note that the above-described trench wiring forming step is performed (M−1−N) times if the desired number of wiring layers is M and the number of wiring layers provided on the first substrate is N. . In the second embodiment, the desired number of wiring layers is five, and the number of wiring layers provided on the first substrate 101 is two. -1-2 =) twice.

Next, as shown in FIG. 15, an interlayer insulating film 50 made of, for example, an SiO ₂ film is formed on the entire surface by, for example, a plasma CVD method. The thickness of the interlayer insulating film 50 is, for example, 0.7 μm. Here, the interlayer insulating film 50
As an example of the CVD conditions in the formation of the substrate, for example, TEOS gas is used as a reaction gas, and the substrate heating temperature is set to, for example, 400 ° C. Next, a resist pattern (not shown) having an opening at a portion where a connection hole is formed is formed on interlayer insulating film 50 by a lithography process. Next, using the resist pattern as a mask, the interlayer insulating film 50 is etched by, for example, a plasma etching method until the surface of the trench wiring 49 is exposed. Thereby, the connection hole 51 is formed. The diameter of the connection hole 51 is, for example, 240 nm.

Next, the surface of the interlayer insulating film 50 in which the connection holes 51 are formed is cleaned by, for example, a sputter etching method.

Next, a diffusion preventing film 52 made of, for example, Ta or TaN is formed on the entire surface by, for example, a sputtering method. The thickness of the diffusion prevention film 52 is, for example, 50 nm. Thereafter, a Cu film is formed by, for example, a CVD method so as to be embedded in the connection hole 51. The thickness of the Cu film is, for example, 150 nm. Next, the Cu film and the diffusion prevention film 52 in portions other than the inside of the connection holes 51 are removed by polishing sequentially by, for example, a CMP method. Thereby, the C with the diffusion prevention film 52 as a base is formed inside the connection hole 51.
A plug 53 made of u is formed.

Next, an interlayer insulating film 111 made of, for example, an SiO ₂ film is formed on the interlayer insulating film 50 by, for example, a plasma CVD method. The thickness of the interlayer insulating film 111 is, for example, 500 nm. Next, on the interlayer insulating film 111, a resist pattern (not shown) having an opening having a pattern shape mirror-image-related to the pattern shape of the uppermost Cu wirings 108 and 109 on the first substrate 101 is formed. . Next, using this resist pattern as a mask,
For example, etching is performed by a plasma etching method until the upper surface of the plug 53 is exposed. Thus, the wiring groove 1 having a pattern shape mirror-related to the pattern shape of the uppermost Cu wirings 108 and 109 on the first substrate 101 is formed.
12, 113 are formed. Here, these wiring grooves 1
In the formation of the first and second wirings 12 and 113, the widths of the wiring grooves are adjusted by the Cu wiring 1 provided on the uppermost layer of the first substrate 101.
It is set to about 360 nm which is about 1.2 times the wiring width of the wirings 08 and 109. Further, a first substrate 101 and a second substrate 11 which will be described later.
In order to easily perform alignment and bonding with zero, tapered guide portions are provided in the interlayer insulating film 111 above the wiring grooves 112 and 113, respectively.

Next, the interlayer insulating film 11 in which the wiring grooves 112 and 113 are formed by, for example, a sputter etching method.
1 is cleaned.

Next, a Ta film as a diffusion prevention film and a Cu film as an adhesion film are sequentially formed on the entire surface by, for example, a sputtering method, so that the Cu / Ta film 11 is formed.
4 is formed. Each of the Ta film and the Cu film has a thickness of, for example, 50 nm.

Next, the interlayer insulating film 1 is formed by, eg, CMP.
The Cu / Ta film 114 on the upper surface of the substrate 11 is removed by polishing. This leaves the Cu / Ta film 114 on the bottom and side walls of the wiring grooves 112 and 113.

As described above, the second substrate 110 having the three-layer wiring having the desired wiring shape and the pattern shape in a mirror image relationship is manufactured.

Next, as shown in FIG. 16, the first substrate 101 and the second substrate 110 manufactured as described above are attached to each other in the same manner as in the first embodiment. Then, the bonding surface of the first substrate 101 and the bonding surface of the second substrate 110 are brought into close contact with each other, and the Cu wiring 10 is formed.
More precise alignment is performed by fitting and matching the wiring grooves 8 and 109 with the wiring grooves 112 and 113, respectively.

Next, the first substrate 10 is placed in a mixed gas atmosphere of a reducing gas such as N ₂ gas and H ₂ gas.
The first and second substrates 110 are heated to a temperature of 400 to 450 ° C., specifically, for example, 400 ° C. The heating temperature is selected in a range where the material used for the wiring flows on the surface. As a result, the Cu film and the Cu wirings 108 and 109 of the Cu / Ta film 25 formed on the bottom and side walls of the wiring grooves 112 and 113 are reduced and flow on the surface. Then, the wiring grooves 112 and 113 and the Cu wiring 10
The gaps between the wirings 8 and 109 are filled with the surface-flowed Cu, and the two-layer wiring on the first substrate 101 and the three-layer wiring on the second substrate 110 are electrically connected.

Next, as shown in FIG. 17, the second substrate 110 is wet-etched using, for example, HF.
Is etched. Thereby, the first
Wiring and overcoat film 33 on substrate 101
The glass substrate 31 is exfoliated while remaining.

As described above, a CMOS LSI in which five layers of wiring are provided above the CMOS transistor is manufactured.

As described above, according to the CMOS LSI manufacturing method according to the second embodiment, the CMOS transistor and the two-layer wiring are formed on the first substrate 101 and the second substrate After three layers of wiring are formed on the first substrate 110 and the second substrate 11
The effect similar to that of the first embodiment can be obtained by pasting 0 to each other. Further, by providing a tapered guide portion in the interlayer insulating film 111 above the wiring grooves 112 and 113, the first
When bonding the substrate 101 and the second substrate 110 to each other, the Cu wirings 108 and 109
Can be easily fitted into the wiring grooves 112 and 113,
Positioning can be easily performed.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, in the above embodiment, the CM
Although the description has been given of the manufacture of the OSLSI, the present invention is applicable not only to the manufacture of a CMOS LSI but also to the manufacture of an electronic device having elements such as an oxide element, a dielectric element, and a superconducting element.

Further, for example, the numerical values, materials, film forming methods, and etching methods described in the above embodiments are merely examples, and different numerical values, materials, film forming methods, and etching methods may be used as necessary. Is also good.

In the first and second embodiments, for example, the SiO ₂ film formed by using the TEOS gas as the reaction gas is used as the interlayer insulating film, but the interlayer insulating film made of another material is used. A film can be used, and a low dielectric constant film can be used.

In the first and second embodiments described above, for example, the first substrate and the second substrate are heated after the first substrate and the second substrate are bonded. Heats the first and second substrates to the first
May be performed at the same time when the substrate is bonded to the second substrate.

[0089]

As described above, according to the present invention, one main surface of the first substrate having N-layer wirings less than M layers provided on the electronic element, the supporting substrate and the supporting substrate An electronic device having M-layer wiring is manufactured by bonding an upper surface of a second substrate having (MN) -layer wiring provided thereon to an electronic device having M-layer wiring. In addition to shortening the time required for manufacturing the semiconductor device, the manufacturing yield can be improved.

[Brief description of the drawings]

FIG. 1 is a CMOSLS according to a first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a first substrate for describing a method of manufacturing a CMOS transistor portion of I.

FIG. 2 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a first substrate for describing a method of manufacturing a CMOS transistor portion of I.

FIG. 3 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a first substrate for describing a method of manufacturing a CMOS transistor portion of I.

FIG. 4 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a second substrate for describing a method for manufacturing a multilayer wiring portion of I.

FIG. 5 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a second substrate for describing a method for manufacturing a multilayer wiring portion of I.

FIG. 6 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a second substrate for describing a method for manufacturing a multilayer wiring portion of I.

FIG. 7 is a CMOSLS according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of a second substrate for describing a method for manufacturing a multilayer wiring portion of I.

FIG. 8 is a perspective view for explaining a method of bonding the first substrate and the second substrate according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of a CMOS LSI in which a first substrate and a second substrate are bonded together according to the first embodiment of the present invention.

FIG. 10 shows a CMOSL according to the first embodiment of the present invention;
It is sectional drawing which shows SI.

FIG. 11 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing of the 1st board | substrate used for manufacture of SI.

FIG. 12 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing of the 1st board | substrate used for manufacture of SI.

FIG. 13 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing of the 1st board | substrate used for manufacture of SI.

FIG. 14 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing of the 2nd board | substrate used for manufacture of SI.

FIG. 15 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing of the 2nd board | substrate used for manufacture of SI.

FIG. 16 is a cross-sectional view of a CMOS LSI obtained by bonding a first substrate and a second substrate according to a second embodiment of the present invention.

FIG. 17 shows a CMOSL according to a second embodiment of the present invention;
It is sectional drawing which shows SI.

[Explanation of symbols]

1, 101: first substrate, 2: Si substrate, 3
0, 110: second substrate, 31: glass substrate,
32 ... peeling film, 54, 55, 108, 109 ...
Cu wiring, 23, 24, 35, 40, 46, 112,
113 ・ ・ ・ Wiring groove

Continued on the front page F-term (reference) RR15 SS04 SS15 TT02 XX33 XX34 5F064 AA01 CC10 CC12 DD01 DD04 DD05 DD47 DD50 EE26 EE27 EE32 EE33 EE34 EE36 EE51 GG01 GG03 GG07 GG10

Claims (12)

[Claims] 1. A method of manufacturing an electronic device in which an M-layer wiring is provided on a substrate on which an electronic element is provided, wherein the electronic element and a local wiring of the electronic element provided on the electronic element are removed. One main surface of a first substrate having N layers of less than M layers, and one main surface of a second substrate having a (MN) layer wiring provided on the support substrate and the support substrate. And a method of manufacturing an electronic device. 2. An insulating film having a groove on the one main surface of the first substrate, wherein a pattern shape of the groove of the insulating film of the first substrate and an uppermost layer of the second substrate are provided. And the pattern shape of the wiring is in a mirror image relationship with each other, and the main surface of the first substrate and the main surface of the second substrate are connected so that the wiring of the uppermost layer is fitted in the groove. 2. The method for manufacturing an electronic device according to claim 1, wherein the electronic device is bonded. 3. The method for manufacturing an electronic device according to claim 2, wherein a guide portion is provided above the groove of the insulating film. 4. After the wiring of the uppermost layer of the second substrate is inserted into the groove of the insulating film of the first substrate, the first substrate and the second substrate are heated. Thus, the local wiring of the first substrate and / or the wiring of the N layer and the wiring of the (MN) layer of the second substrate are electrically connected. A method for manufacturing an electronic device according to claim 2. 5. The wiring of the uppermost layer of the second substrate is fitted into the groove of the insulating film of the first substrate while heating the first substrate and the second substrate. The local wiring of the first substrate and / or the wiring of the N layer and the wiring of the (MN) layer of the second substrate are electrically connected to each other. Item 3. A method for manufacturing an electronic device according to Item 2. 6. An insulating film having a groove on the one main surface of the second substrate, wherein a pattern shape of an uppermost layer wiring of the first substrate and an insulating film of the insulating film of the second substrate are provided. The pattern shape of the groove has a mirror image relationship with each other, and the main surface of the first substrate and the main surface of the second substrate are connected so that the wiring of the uppermost layer is fitted in the groove. 2. The method for manufacturing an electronic device according to claim 1, wherein the electronic device is bonded. 7. The method of manufacturing an electronic device according to claim 6, wherein a guide portion is provided above the groove of the insulating film. 8. After the wiring of the uppermost layer of the first substrate is inserted into the groove of the insulating film of the second substrate, the first substrate and the second substrate are heated. Thus, the local wiring and / or the N-layer wiring of the first substrate and the (MN) of the second substrate
7. The method for manufacturing an electronic device according to claim 6, wherein the wiring of the layer is electrically connected. 9. By heating the first substrate and the second substrate and fitting the uppermost layer wiring of the first substrate into the grooves of the insulating film of the second substrate, The local wiring and / or the wiring of the N layer of the first substrate and the wiring of the (MN) layer of the second substrate are electrically connected to each other. 7. The method for manufacturing an electronic device according to item 6. 10. The method according to claim 1, wherein the one main surface of the first substrate and the one main surface of the second substrate are bonded, and then the support substrate is removed from the second substrate. The method for manufacturing an electronic device according to claim 1, wherein: 11. The method according to claim 1, wherein the support substrate is made of a material that transmits light reflected on the one main surface of the first substrate. 12. A plurality of first alignment marks are provided at predetermined positions on the first substrate, and positions in the second substrate that are in a mirror image relationship with the predetermined positions of the first substrate. Are provided with a plurality of second alignment marks, and the one main surface of the first substrate and the second alignment mark are provided.
After arranging the one main surface of the substrate facing the other side, irradiating light from the back surface side of the second substrate, and observing light reflected by the one main surface of the first substrate, 12. The method according to claim 11, wherein the first substrate and the second substrate are aligned.