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JP2000174064A - Method of mounting semiconductor device - Google Patents

Method of mounting semiconductor device

Info

Publication number
JP2000174064A
JP2000174064A JP10344596A JP34459698A JP2000174064A JP 2000174064 A JP2000174064 A JP 2000174064A JP 10344596 A JP10344596 A JP 10344596A JP 34459698 A JP34459698 A JP 34459698A JP 2000174064 A JP2000174064 A JP 2000174064A
Authority
JP
Japan
Prior art keywords
bump
bumps
circuit board
semiconductor chip
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10344596A
Other languages
Japanese (ja)
Other versions
JP3777840B2 (en
Inventor
Masami Tsurumi
正美 鶴見
Mitsuru Mura
満 村
Masaru Sasaki
大 佐々木
Masuo Kato
益雄 加藤
Tsutomu Sakurai
勉 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP34459698A priority Critical patent/JP3777840B2/en
Publication of JP2000174064A publication Critical patent/JP2000174064A/en
Application granted granted Critical
Publication of JP3777840B2 publication Critical patent/JP3777840B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81194—Lateral distribution of the bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To make the bump pitch fine and improve the bump bond strength. SOLUTION: Bumps 13A, 13B are formed on the bottom face of a semiconductor chip 11 and the top face of a circuit board 14 facing it. The bumps 13A, 13B are made protrudent so that the semiconductor chip 121 is mounted on a circuit board 14 in the layout that the bumps 13B at the circuit board 14 intrude between the bumps 13A at the semiconductor chip 11. This enables the bump connection at more fine pitches and makes it possible to improve the ball shear strength because the bump size can be more increased, without widening the bump pitch.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の実装
方法に関し、更に詳しくは、フェイスダウンボンディン
グ法による回路基板へのフリップチップの実装方法に関
する。The present invention relates to a method for mounting a semiconductor device, and more particularly, to a method for mounting a flip chip on a circuit board by a face-down bonding method.

【０００２】[0002]

【従来の技術】近年の半導体装置の実装技術では、高密
度、高信頼性、信号伝達距離の短縮化等を図る観点か
ら、フリップチップのフェイスダウンボンディング方法
が提案、実用化されている。この方法は、例えば図７お
よび図８に示すように、チップ状の半導体素子（以下、
半導体チップという）１の底面に単列、複数列あるいは
マトリックス状（面配列）に配列された複数の電極部２
にバンプ３を形成し、このバンプ３を対向する回路基板
４上の電極部５へ接合剤６を用いて接合し、半導体チッ
プ１と回路基板４とを電気的に接続する方法である。な
お、図７では半導体チップ１の底面を上方にして示して
いる。2. Description of the Related Art A flip-chip face-down bonding method has been proposed and put into practical use in recent semiconductor device mounting techniques from the viewpoint of achieving high density, high reliability, and a reduction in signal transmission distance. This method uses, for example, a chip-shaped semiconductor element (hereinafter, referred to as FIG. 7 and FIG. 8).
A plurality of electrode portions 2 arranged in a single row, a plurality of rows, or in a matrix (plane arrangement) on the bottom surface of a semiconductor chip 1)
In this method, the semiconductor chip 1 and the circuit board 4 are electrically connected to each other by forming the bumps 3 and bonding the bumps 3 to the electrode portions 5 on the opposing circuit board 4 using a bonding agent 6. FIG. 7 shows the semiconductor chip 1 with the bottom surface facing upward.

【０００３】バンプ３は、電極部２にボールボンディン
グあるいはワイヤボンディングと同様な手法で、金ワイ
ヤをキャピラリで押し潰した後、ワイヤを切断すること
により形成される。接合剤６は非導電性の熱硬化性樹脂
（例えばエポキシ樹脂）で予め回路基板４上に塗布され
ており、接合時はバンプ３を回路基板４の電極部５に圧
接させながら接合剤６を加熱して硬化させる。The bump 3 is formed by crushing a gold wire with a capillary in the same manner as ball bonding or wire bonding on the electrode portion 2 and then cutting the wire. The bonding agent 6 is previously coated on the circuit board 4 with a non-conductive thermosetting resin (for example, epoxy resin). At the time of bonding, the bonding agent 6 is pressed while the bumps 3 are pressed against the electrode portions 5 of the circuit board 4. Heat to cure.

【０００４】以上のように、従来では半導体チップ１側
にバンプ３を形成し、これを回路基板４の電極部５と位
置合わせを行い、フェイスダウン方式で半導体チップ１
を実装している。しかしながら、この方法では、バンプ
ピッチが２００μｍ→１５０μｍ→１０５μｍ→８５μ
ｍ→５０μｍとファイン化（狭ピッチ化）するとき、特
に１００μｍ以下の場合はバンプ形成時にキャピラリ隣
接条件とボールシェアの接合強度条件によりバンプピッ
チのファイン化が困難であるといった問題がある。すな
わち、バンプピッチが狭いとバンプ同士が接触してしま
い、又、バンプサイズを極端に小さくしてファイン化を
図ればバンプシェア強度が低下してしまい、信頼性が損
なわれる。As described above, conventionally, the bumps 3 are formed on the semiconductor chip 1 side, the bumps 3 are aligned with the electrode portions 5 of the circuit board 4, and the semiconductor chip 1 is face-down type.
Is implemented. However, in this method, the bump pitch is 200 μm → 150 μm → 105 μm → 85 μm.
When the fineness is reduced from m to 50 μm (narrow pitch), particularly when the pitch is 100 μm or less, there is a problem that it is difficult to finely adjust the bump pitch due to the condition of the adjacent capillary and the bonding strength of the ball shear when forming the bump. In other words, if the bump pitch is narrow, the bumps will contact each other, and if the bump size is made extremely small to achieve fineness, the bump shear strength will be reduced and reliability will be impaired.

【０００５】[0005]

【発明が解決しようとする課題】本発明は上述の問題に
鑑みてなされ、バンプピッチのファイン化、バンプ接合
強度の向上を図ることができる半導体装置の実装方法を
提供することを課題とする。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and has as its object to provide a method of mounting a semiconductor device capable of achieving finer bump pitch and improved bump bonding strength.

【０００６】[0006]

【課題を解決するための手段】以上の課題を解決するに
当たり、本発明は、半導体素子の底面とこれに対向する
回路基板の上面の双方にバンプを形成するとともに、バ
ンプの先端をその底部よりも小径となるように形成する
ことにより、半導体素子側のバンプ間に回路基板側のバ
ンプが介入する配置関係で半導体素子を回路基板上へ実
装する。これにより、半導体素子側のバンプ間の隙間
を、回路基板側のバンプの小径部が介入するだけの隙間
を残して形成すればよいので、バンプサイズを極端に小
さくすることなく従来よりも更なるファインピッチのバ
ンプ接続を可能とする。また一方、従来のバンプピッチ
においても、バンプサイズをより大きくすることができ
るので、応力に強くなり、ボールシェア強度を向上させ
て信頼性を高めることができる。In order to solve the above-mentioned problems, the present invention provides a method for forming a bump on both a bottom surface of a semiconductor element and a top surface of a circuit board facing the semiconductor element, and moving a tip of the bump from the bottom. Also, the semiconductor element is mounted on the circuit board in such an arrangement that the bumps on the circuit board side intervene between the bumps on the semiconductor element side. Thereby, the gap between the bumps on the semiconductor element side may be formed leaving a gap for the small-diameter portion of the bump on the circuit board side to intervene, so that the bump size is further reduced without extremely reducing the bump size. Enables fine pitch bump connection. On the other hand, even in the conventional bump pitch, the bump size can be made larger, so that the bump strength is increased, the ball shear strength is improved, and the reliability can be improved.

【０００７】[0007]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

【０００８】図１から図６は、本発明の実施の形態を示
している。図１は本実施の形態における半導体チップ１
１の底面を示しており、図示するように半導体チップ１
１の底面の周縁部に交互に配列された例えばアルミニウ
ムから成る電極部１２ａ、１２ｂのうち一方の電極部１
２ａに、後述する形状の金で成るバンプ１３Ａが形成さ
れている。一方、図２は本実施の形態における回路基板
１４を示しており、図示するように半導体チップ１１の
電極部１２ａ、１２ｂに対応して交互に配列された例え
ばアルミニウムから成る電極部１５ａ、１５ｂのうち一
方の電極部１５ａに、半導体チップ１１側と同一構成の
バンプ１３Ｂが形成されている。FIGS. 1 to 6 show an embodiment of the present invention. FIG. 1 shows a semiconductor chip 1 according to this embodiment.
1 shows the bottom surface of the semiconductor chip 1 as shown in FIG.
One of the electrode portions 12a and 12b made of, for example, aluminum, which are alternately arranged on the peripheral portion of the bottom surface of the first electrode portion 1.
A bump 13A made of gold having a shape described later is formed on 2a. On the other hand, FIG. 2 shows a circuit board 14 according to the present embodiment. As shown in FIG. 2, electrode portions 15a and 15b made of, for example, aluminum are alternately arranged corresponding to the electrode portions 12a and 12b of the semiconductor chip 11. A bump 13B having the same configuration as that of the semiconductor chip 11 is formed on one of the electrode portions 15a.

【０００９】次にバンプ１３Ａ、１３Ｂの詳細につい
て、図３を参照して説明する。図は半導体チップ１１の
底面に設けられるバンプ１３Ａを示しているが、回路基
板１４側に設けられるバンプ１３Ｂも同様に構成される
ものとする。Next, details of the bumps 13A and 13B will be described with reference to FIG. Although the figure shows the bump 13A provided on the bottom surface of the semiconductor chip 11, the bump 13B provided on the circuit board 14 side has the same configuration.

【００１０】本実施の形態におけるバンプ１３Ａは、電
極部１２ａに対し、キャピラリ１８を使用したワイヤボ
ンディング時の途中で金（Ａｕ）ワイヤを引き千切り、
その先端をレベリングすることにより形成され、電極部
１２ａ側の底部に大径部１３１、先端側に小径部１３２
を有している。この小径部１３２の高さｈは大径部１３
１の高さＨよりも大きく形成されている。本実施の形態
では、電極部１２ａ、１２ｂはそれぞれ交互に配置され
ることにより、バンプ１３Ａ間に電極部１２ｂが位置す
る。In the present embodiment, the bump 13A cuts a gold (Au) wire from the electrode portion 12a during wire bonding using the capillary 18,
The large-diameter portion 131 is formed at the bottom on the side of the electrode portion 12a, and the small-diameter portion 132 is formed at the front end.
have. The height h of the small diameter portion 132 is
1 is formed larger than the height H. In the present embodiment, the electrode portions 12a and 12b are alternately arranged, so that the electrode portion 12b is located between the bumps 13A.

【００１１】回路基板１４側のバンプ１３Ｂも上述と同
様に構成されるとともに、その電極部１５ａ、１５ｂも
またそれぞれ交互に配置されることにより、バンプ１３
Ｂ間に電極部１５ｂが位置する。このとき、半導体チッ
プ１１側のバンプ１３Ａが形成されていない位置にバン
プ１３Ｂが配置されるように構成する。The bumps 13B on the circuit board 14 side are also configured in the same manner as described above, and the electrode portions 15a and 15b are also arranged alternately, so that the bumps 13B are formed.
The electrode portion 15b is located between B. At this time, the configuration is such that the bump 13B is arranged at a position where the bump 13A is not formed on the semiconductor chip 11 side.

【００１２】また、電極部１２ｂ、１５ｂは、それぞれ
バンプ１３Ｂ、１３Ａの小径部１３２と接続できるだけ
の面積があれば十分であるので、他方の電極部１２ａ、
１５ａの面積よりも小さく形成されている。Further, the electrode portions 12b and 15b only need to have an area enough to be connected to the small-diameter portions 132 of the bumps 13B and 13A, respectively.
15a is formed smaller than the area.

【００１３】次に、半導体チップ１１と回路基板１４と
の実装方法について説明すると、図４及び図５を参照し
て、半導体チップ１１の底面と回路基板１４の表面とを
対向させ（図４Ａ）、半導体チップ１１側のバンプ１３
Ａの小径部１３２を回路基板１４の電極部１５ｂに接続
するともに、回路基板１４側のバンプ１３Ｂの小径部１
３２を半導体チップ１１の電極部１２ｂに接続し（図４
Ｂ）、バンプ１３Ａ間にバンプ１３Ｂが介入する配置関
係となるように、半導体チップ１１を回路基板１４へ実
装する。ここで本実施の形態では、図示するようにバン
プ１３Ａとバンプ１３Ｂとが交互に配置されるよう構成
される。なお、回路基板１４上には非導電性の熱硬化性
樹脂（例えばエポキシ樹脂）から成る接合剤１６が予め
塗布され、これは実装時、半導体チップ１１を回路基板
１４に圧接しながら加熱され硬化する。Next, a method of mounting the semiconductor chip 11 and the circuit board 14 will be described. Referring to FIGS. 4 and 5, the bottom surface of the semiconductor chip 11 is opposed to the surface of the circuit board 14 (FIG. 4A). , Bump 13 on the side of semiconductor chip 11
A small diameter portion 132 of A is connected to electrode portion 15b of circuit board 14, and small diameter portion 1 of bump 13B on circuit board 14 side.
32 is connected to the electrode portion 12b of the semiconductor chip 11 (FIG. 4).
B) The semiconductor chip 11 is mounted on the circuit board 14 such that the bumps 13B are interposed between the bumps 13A. Here, in the present embodiment, as illustrated, the bumps 13A and the bumps 13B are configured to be arranged alternately. A bonding agent 16 made of a non-conductive thermosetting resin (for example, epoxy resin) is applied on the circuit board 14 in advance, and is heated and cured while pressing the semiconductor chip 11 against the circuit board 14 during mounting. I do.

【００１４】以上の構成および作用から、以下のような
効果を得ることができる。From the above configuration and operation, the following effects can be obtained.

【００１５】すなわち、本実施の形態によれば、半導体
素子１１側のバンプ１３Ａ間の隙間を、回路基板１４側
のバンプ１３Ｂの小径部１３２が介入するだけの隙間を
残して形成すればよいので、図６Ｂに示す従来のバンプ
ピッチＰ’（バンプ３とバンプ３との配置間隔）より
も、図６Ａに示すようにバンプピッチＰを小さくするこ
とができる。このとき、バンプ小径部１３２の高さｈを
大径部１３１の高さＨよりも高くしているので、実装
時、半導体チップ１１側のバンプ大径部１３１と回路基
板１４側のバンプ大径部１３１とが接触することはな
い。したがって、バンプサイズを極端に縮小することな
く、換言すれば信頼性を維持したまま、バンプを配列さ
せて接続することができ、従来よりもファインピッチの
実装が可能となる。That is, according to the present embodiment, the gap between the bumps 13A on the semiconductor element 11 side may be formed leaving a gap for the small diameter portion 132 of the bump 13B on the circuit board 14 side to intervene. 6A, the bump pitch P can be made smaller than the conventional bump pitch P ′ (arrangement interval between the bumps 3) shown in FIG. 6B. At this time, since the height h of the bump small diameter portion 132 is higher than the height H of the large diameter portion 131, the bump large diameter portion 131 on the semiconductor chip 11 side and the bump large diameter on the circuit board 14 side during mounting. The part 131 does not contact. Therefore, the bumps can be arranged and connected without extremely reducing the bump size, in other words, while maintaining the reliability, and mounting at a finer pitch than before can be achieved.

【００１６】また、バンプを従来のバンプピッチＰ’で
配列しても、バンプサイズをより大きくすることができ
るので、半導体チップ１１と回路基板１４との熱膨張係
数の違いで生じる応力に強くなり、ボールシェア強度を
向上させて信頼性を高めることができる。Further, even if the bumps are arranged at the conventional bump pitch P ', the bump size can be made larger, so that the semiconductor chip 11 and the circuit board 14 are more resistant to stress caused by a difference in the coefficient of thermal expansion. In addition, the ball shear strength can be improved to increase reliability.

【００１７】以上、本発明の実施の形態について説明し
たが、勿論、本発明はこれに限定されることなく、本発
明の技術的思想に基づいて種々の変形が可能である。Although the embodiments of the present invention have been described above, the present invention is, of course, not limited thereto, and various modifications can be made based on the technical concept of the present invention.

【００１８】例えば以上の実施の形態では、バンプ１３
Ａ、１３Ｂの形状を凸型としたが、例えば円錐台形状の
ように、底部に対して先端が小径となる形状のバンプで
もよい。For example, in the above embodiment, the bump 13
Although the shapes of A and 13B are convex, bumps having a small diameter at the tip with respect to the bottom, such as a truncated cone, may be used.

【００１９】また、以上の実施の形態では、バンプ１３
Ａの配列を半導体チップ１１の周縁部に沿った単列とし
たが、複数列あるいはマトリックス状（面配列）のバン
プ配列にも、本発明は適用可能であることは言うまでも
ない。In the above embodiment, the bump 13
Although the arrangement of A is a single row along the periphery of the semiconductor chip 11, it is needless to say that the present invention is applicable to a plurality of rows or a matrix (plane arrangement) bump arrangement.

【００２０】更に、以上の実施の形態では、半導体チッ
プ１１側のバンプ１３Ａと回路基板１４側のバンプ１３
Ｂとが実装時、交互に配列される配置関係となるように
構成したが、必要に応じて配置の構成を変更することも
可能である。例えば、回路基板側のバンプ数を半導体チ
ップ側のバンプ数よりも少なくして、半導体チップ側の
バンプ間の任意の位置に回路基板側のバンプを介入させ
る配置関係としてもよい。Further, in the above embodiment, the bump 13A on the semiconductor chip 11 side and the bump 13A on the circuit board 14 side are used.
Although B is configured so as to have an arrangement relationship of being alternately arranged at the time of mounting, it is also possible to change the arrangement configuration as needed. For example, the arrangement may be such that the number of bumps on the circuit board is smaller than the number of bumps on the semiconductor chip, and the bumps on the circuit board are interposed at arbitrary positions between the bumps on the semiconductor chip.

【００２１】[0021]

【発明の効果】以上述べたように、本発明の半導体装置
の実装方法によれば、バンプサイズを極端に小さくする
ことなく従来よりも更なるファインピッチのバンプ接続
が可能となる。また一方、従来のバンプピッチにおいて
も、バンプサイズをより大きくすることができるので、
応力に強くなり、ボールシェア強度を向上させて信頼性
を高めることができる。As described above, according to the semiconductor device mounting method of the present invention, it is possible to connect bumps with a finer pitch than ever before without extremely reducing the bump size. On the other hand, even with the conventional bump pitch, the bump size can be made larger,
It becomes resistant to stress, and improves ball shear strength to improve reliability.

【００２２】また、請求項２の発明によれば、半導体素
子側のバンプと回路基板側のバンプとを接触させること
なく確実に実装することができる。Further, according to the second aspect of the present invention, the bumps on the semiconductor element and the bumps on the circuit board can be securely mounted without contacting each other.

【００２３】更に、請求項３の発明により、半導体素子
側および回路基板側へのバンプ形成を容易に行うことが
できる。Further, according to the third aspect of the present invention, bumps can be easily formed on the semiconductor element side and the circuit board side.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態における半導体チップ側の
バンプ配列を示す半導体チップの裏面図である。FIG. 1 is a rear view of a semiconductor chip showing a bump arrangement on a semiconductor chip side according to an embodiment of the present invention.

【図２】同回路基板側のバンプ配列を示す回路基板の要
部の平面図である。FIG. 2 is a plan view of a main part of the circuit board, showing a bump arrangement on the circuit board side.

【図３】同半導体チップ／回路基板のバンプ形状の詳細
を示す側断面図である。FIG. 3 is a side sectional view showing details of a bump shape of the semiconductor chip / circuit board.

【図４】同半導体チップと回路基板との実装方法を示す
側断面図であり、Ａは実装前、Ｂは実装後を示してい
る。FIG. 4 is a side sectional view showing a mounting method of the semiconductor chip and a circuit board, wherein A shows before mounting and B shows after mounting.

【図５】同実装後の半導体チップと回路基板とを示す斜
視図である。FIG. 5 is a perspective view showing a semiconductor chip and a circuit board after the mounting.

【図６】本発明の実施の形態による実装方法で実装した
バンプピッチと、従来の実装方法で実装したバンプピッ
チとを示す側面図であり、Ａは本発明を、Ｂは従来例を
示している。FIG. 6 is a side view showing a bump pitch mounted by a mounting method according to an embodiment of the present invention and a bump pitch mounted by a conventional mounting method, wherein A shows the present invention and B shows a conventional example. I have.

【図７】従来の半導体チップのバンプ配列を示す側断面
図である。FIG. 7 is a side sectional view showing a bump arrangement of a conventional semiconductor chip.

【図８】従来の実装後の半導体チップと回路基板とを示
す側断面図である。FIG. 8 is a side sectional view showing a conventional semiconductor chip and a circuit board after mounting.

【符号の説明】[Explanation of symbols]

１１……半導体チップ、１２ａ、１２ｂ、１５ａ、１５
ｂ……電極部、１３Ａ、１３Ｂ……バンプ、１４……回
路基板、１６……接合剤、１３１……大径部、１３２…
…小径部、Ｈ……大径部の高さ、ｈ……小径部の高さ。11: semiconductor chip, 12a, 12b, 15a, 15
b ... electrode portion, 13A, 13B ... bump, 14 ... circuit board, 16 ... bonding agent, 131 ... large diameter portion, 132 ...
... Small diameter part, H ... Height of large diameter part, h ... Height of small diameter part.

フロントページの続き (72)発明者 加藤 益雄 愛知県額田郡幸田町大字坂崎字雀ヶ入１番 地 ソニー幸田株式会社内 (72)発明者 櫻井 勉 愛知県額田郡幸田町大字坂崎字雀ヶ入１番 地 ソニー幸田株式会社内 Ｆターム(参考） 5F044 CC05 KK17 KK19 LL11 QQ02 QQ04 Continuing on the front page (72) Inventor Masuo Kato No. 1, Koda-cho, Nada-gun, Aichi Prefecture, within the area of Sony Koda Co., Ltd. (72) Inventor Tsutomu Sakurai, Kota-cho, Nada-gun, Aichi Prefecture No. 1 Sony Koda Co., Ltd. F-term (reference) 5F044 CC05 KK17 KK19 LL11 QQ02 QQ04

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 チップ状の半導体素子を回路基板上にバ
ンプを介して導電接続する半導体装置の実装方法におい
て、 前記半導体素子の底面とこれに対向する前記回路基板の
上面の双方に前記バンプを形成するとともに、 前記バンプの先端をその底部よりも小径となるように形
成することにより、 前記半導体素子側のバンプ間に前記回路基板側のバンプ
が介入する配置関係で前記半導体素子を前記回路基板上
へ実装することを特徴とする半導体装置の実装方法。1. A method of mounting a semiconductor device in which a chip-shaped semiconductor element is conductively connected on a circuit board via a bump, wherein the bump is formed on both a bottom surface of the semiconductor element and an upper surface of the circuit board opposed thereto. The bumps on the circuit board side are interposed between the bumps on the semiconductor element side so that the bumps on the circuit board side intervene between the bumps on the semiconductor element side. A method of mounting a semiconductor device, wherein the semiconductor device is mounted on the semiconductor device. 【請求項２】 前記バンプの形状を、その底部側に大径
部、先端側に小径部を有する凸型とし、かつ、 前記小径部の高さを前記大径部の高さよりも大きくした
ことを特徴とする請求項１に記載の半導体装置の実装方
法。2. The bump has a convex shape having a large-diameter portion on the bottom side and a small-diameter portion on the tip side, and the height of the small-diameter portion is larger than the height of the large-diameter portion. The method for mounting a semiconductor device according to claim 1, wherein: 【請求項３】 前記バンプは、ワイヤボンディングの途
中でワイヤを切断することにより形成されることを特徴
とする請求項２に記載の半導体装置の実装方法。3. The method according to claim 2, wherein the bump is formed by cutting a wire during wire bonding.
JP34459698A 1998-12-03 1998-12-03 Mounting method of semiconductor device Expired - Fee Related JP3777840B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34459698A JP3777840B2 (en) 1998-12-03 1998-12-03 Mounting method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34459698A JP3777840B2 (en) 1998-12-03 1998-12-03 Mounting method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2000174064A true JP2000174064A (en) 2000-06-23
JP3777840B2 JP3777840B2 (en) 2006-05-24

Family

ID=18370502

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149836A (en) * 2005-11-25 2007-06-14 Toshiba Corp Semiconductor device
US8129840B2 (en) 2008-07-15 2012-03-06 Samsung Electronics Co., Ltd. Semiconductor package and methods of manufacturing the same
CN105489579A (en) * 2014-10-06 2016-04-13 爱思开海力士有限公司 Ko Hyeong Jun

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149836A (en) * 2005-11-25 2007-06-14 Toshiba Corp Semiconductor device
US7880308B2 (en) 2005-11-25 2011-02-01 Kabushiki Kaisha Toshiba Semiconductor device
US8129840B2 (en) 2008-07-15 2012-03-06 Samsung Electronics Co., Ltd. Semiconductor package and methods of manufacturing the same
CN105489579A (en) * 2014-10-06 2016-04-13 爱思开海力士有限公司 Ko Hyeong Jun

Also Published As

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