JP2000173270A - Semiconductor memory - Google Patents

Abstract

(57) Abstract: In a static semiconductor memory, reading and writing to the same cell can be performed in one cycle, and two-port operations of reading and writing are simultaneously performed in one cycle required for reading. Thus, the system throughput can be improved with a small area SRAM cell. SOLUTION: A memory cell array 10 is constituted by 1-port SRAM cells, and is read out on the basis of a first clock edge and written on the basis of a second clock edge. Times word line W
Activate L. After the data read from the memory cell is transmitted to the sense circuit 30 by the first word line WL activation, the sense circuit disconnection switch 35 disconnects the bit line pair BL, BLB from the sense circuit 30. Next, the write control switch 55 is turned on to transfer the write data to the bit line pair BL, NBL.
Data is written to the memory cell by activating L.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a static semiconductor memory capable of simultaneously performing two-port operation of reading and writing with a small occupation area in one cycle.

[0002]

2. Description of the Related Art In recent years, the performance of micro-processors has been remarkably improved by process technology and circuit technology. In access to the cache memory, there is a demand to improve the system throughput by executing read access / write access simultaneously. Further, with the increase in processors such as superscalar processors that issue a plurality of instructions at the same time, the demand for cache memories capable of simultaneously executing a plurality of read accesses / write accesses is increasing. Such a cache memory is constituted by a static memory (hereinafter, referred to as “SRAM”).

A conventional SRA having a plurality of ports will be described below.
M will be described. FIG. 11 shows a conventional two-port SR capable of simultaneously executing read access / write access.
FIG. 3 is a block diagram illustrating an example of a configuration of an AM. FIG.
Two-port SR constituting memory cell array 11 in FIG.
The AM cell 111 is shown.

In FIG. 12, a two-port SRAM cell 1
Numeral 11 holds data in the storage nodes N1 and N2 by cross-connecting the inputs and outputs of a pair of inverter circuits. This is similar to a normal one-port SRAM cell. A pair of storage nodes N1 and N2 are connected to data transfer circuits MA1A, MA2A, MA1B and MA2B selected by word lines WLA and WLB corresponding to two ports, respectively, and a bit line pair corresponding to each port. BLA, N
Data is input / output by BLA, BLB, NBLB.
MD1 and MD2 are driving MOSFETs for a pair of cross-coupled inverter circuits, and ML1 and ML2 are load MOSFETs.

[0005] The two-port SRAM shown in FIG. 11 has two address input ports ADA and ADB, and shows data input / output when the A port is read-only and the B port is write-only. If a data input / output circuit is provided for each port, a configuration is possible in which reading and writing can be performed on both the AB ports. 21 is a column switch, 25 is a common bus line, and 30 is a sense circuit. Reference numeral 40 denotes a data output buffer for the A port data output DOA. 50
Is a data input buffer for B port data input. A timing control circuit 81 receives a clock CLK and a control signal SIG, outputs a word line control signal 820 to an A port word line driver 71 and a B port word line driver 72, and outputs a word line control signal 820 to the sense circuit 30.
To output an activation signal.

A two-port SRAM configured as described above
The operation will be described below. The A port address signal ADA is decoded by the A port word line decoder 61, and the A port word line driver 71 drives the A port word line WLA. On the other hand, the B port address signal AD
B is decoded by a B port word line decoder 62 and a B port word line driver 72 drives a B port word line WLB.

The reading of data from the storage nodes N1 and N2 and the writing of data to the storage nodes N1 and N2 are performed by A
This is performed by the pair of port bit lines BLA and NBLA and the pair of B port bit lines BLB and NBLB. As for the A port, by activating the A port word line WLA, data input / output of the A port is performed from the A port bit line pair BLA, NBLA via the data transfer circuits MA1A, MA2A. On the other hand, for the B port, the B port word line W
By activating LB, the data transfer circuit MA1B,
B port bit line pair BLB, NBLB via MA2B
Input and output of data from the B port.

As described above, each word line operates independently with respect to two address signals, and furthermore, data is input / output from two bit line pairs corresponding to each port, whereby a plurality of ports can be simultaneously operated in one cycle. , A read operation or a write operation is realized.

In other words, the conventional multi-port SRAM
Is constituted by a multi-port SRAM cell having a plurality of word lines and a plurality of bit line pairs in order to realize a read operation or a write operation from a plurality of ports simultaneously in one cycle.

[0010]

However, in the above-described conventional configuration, the two-port SRAM cell 111 has a plurality of data transfer circuits MA1A, MA2A, MA1B, MA.
2B and a plurality of word lines WLA, WL
B, a plurality of bit line pairs BLA, NBLA, BLB, NB
Since the LB is required, the area is larger than that of a normal one-port SRAM cell.

The SRAM cell has a data transfer MOS.
It is necessary to secure the cell noise margin by increasing the performance of the driving MOSFETs MD1 and MD2 of the pair of cross-coupled inverter circuits with respect to the performance of the FET. In the case of a two-port SRAM cell, the word lines WLA and WLB of two ports may be activated at the same time. At this time, the capability of the data transfer MOSFET is the sum of the capabilities of a plurality of data transfer MOSFETs, ie, 1
This is equivalent to twice the capacity of a pair of data transfer MOSFETs. Even in this case, in order to secure the noise margin of the cell, one port S having one pair of MOSFETs for data transfer is used.
MD, which is a driving MOSFET, is different from the case of a RAM cell.
1. It is necessary to increase the capacity of MD2, that is, the transistor size. This also causes the area of the two-port SRAM cell to be larger than that of a normal one-port SRAM cell.

For the above reasons, a two-port SRAM cell generally occupies about twice the area of a one-port SRAM cell.

As described above, there is a problem that the two-port SRAM cell occupies a much larger area than the one-port SRAM cell.

In the conventional configuration, if a read operation and a write operation are performed on the same address, that is, the same SRAM cell from two ports in the same cycle, read data is not guaranteed. That is, the storage nodes N1, N2 of the two-port SRAM cell 111
2 is being read to one port, data is written from another port to the same storage nodes N1 and N2. Therefore, the read data is not the data of the SRAM cell to be read, but another data. Write data from the port is output instead.

The two-port SRAM constituted by the two-port SRAM cells has a problem that a read operation and a write operation cannot be simultaneously performed on the same address, that is, the same SRAM cell in the same cycle. However, there is a problem that reading and writing to the same address require different accesses, that is, two cycles, which lowers the system throughput.

Further, a time-division access is performed to simulate 2
The realization of a multi-port SRAM with more than two ports is also described, for example, in ISSCC, 1994, pp. 262-263, which is 1.5 or 2 times the cycle required for read or write operations. Multiple operations are performed by time-sharing the cycle. That is, a cycle longer than that required for the read or write operation is required. In other words, multiple port access within the minimum cycle time required for a read or write operation cannot be realized.

The present invention solves the above-mentioned conventional problems and uses a one-port SRAM cell having a small area to perform a two-port operation of a read operation and a write operation in a small occupied area within one cycle time required for a read operation. It is another object of the present invention to provide a static memory which can simultaneously realize a read operation and a write operation to the same address in the same cycle.

[0018]

In order to solve the above-mentioned problems, the present invention is directed to a word line for a certain period of time with reference to a first clock edge at the time of reading and with reference to a second clock edge at the time of writing. In an active state.

As a result, the read operation and the write operation for the same address can be executed simultaneously in one cycle required for the read operation, and the system throughput can be improved.

[0020]

A semiconductor memory according to the first aspect of the present invention is a static semiconductor memory including a memory cell array including a plurality of memory cells and performing a read / write operation in one clock cycle. A word line activation signal for activating the word line only for a certain period of time based on the first clock edge during writing and for a certain period of time based on the second clock edge during writing. After reading the data of the word line control circuit and the bit line pair to the sense circuit, the circuit for disconnecting the bit line pair and the sense circuit and its control means, and the connection between the bit line pair and the sense circuit are disconnected. After that, a circuit for transmitting write data from the write data line to the bit line pair and a control means therefor are provided for one cycle required for reading. In, in which to perform the writing to the same memory cell simultaneously with the reading.

According to a second aspect of the present invention, when a read access and a write access occur in the same cycle, the word line control circuit activates the same word line twice in the same cycle with respect to each clock edge. The configuration is such that a word line activation signal is generated so that

A semiconductor memory according to a third aspect of the present invention is a static semiconductor memory including a memory cell array composed of a plurality of memory cells and executing a read / write operation in one clock cycle. A word line control circuit for generating a word line activation signal for activating a word line only for a certain period of time with reference to a clock edge of the above, and for activating the word line only for a certain period of time with reference to a second clock edge during writing A circuit for disconnecting between the bit line pair and the sense circuit after reading the data of the bit line pair to the sense circuit, and control means therefor;
Among the input / output bits simultaneously input / output, a control circuit capable of independently controlling writing of at least one specific bit and another bit, and disconnection between the bit line pair and the sense circuit for the specific bit Later, a circuit for transmitting the write data from the write data line to the bit line pair and a control means therefor are provided, and in one cycle required for the read, the write is performed on the memory cell of the specific bit at the same time as the read. Things.

According to a fourth aspect of the present invention, when the word line control circuit writes data only to the specific bit in the same cycle as the data read cycle, the same word line is controlled in the same cycle with respect to each clock edge. Is activated twice to generate a word line activation signal.

A semiconductor memory according to a fifth aspect of the present invention is a static semiconductor memory including a memory cell array including a plurality of memory cells and performing a read / write operation in one clock cycle. And a read address input port and a write address input port which can be input independently of each other, and activates the word line only for a certain period of time with reference to the first clock edge at the time of reading, and sets the second clock edge at the time of writing. A word line control circuit for generating a word line activation signal for controlling a word line driver so that the word line is activated only for a certain period based on a reference; and A circuit for disconnecting between a pair and a sense circuit, and a control means therefor, and a bit line pair A circuit for transmitting write data from a write data line to a bit line pair after disconnection from a sense circuit and a control unit therefor, and a read address among the addresses input from the address input port, In response to a word line activation signal for controlling a word line to be in an active state only for a certain period based on a clock edge, the word line driver is input to the word line driver, and a write address is set based on the second clock edge. Corresponding to a word line activation signal for controlling a word line to be in an active state only for a certain period, and a circuit for inputting to the word line driver and control means therefor,
In one cycle required for reading, the data at the read address is read and the data is written to the write address at the same time.

According to a sixth aspect of the present invention, when the word line control circuit performs a read access and a write access in the same cycle, the word line corresponding to the address input with respect to each clock edge in the same cycle. The word line activation signal is set to 2 so that each is activated.
And a control circuit for inputting the word line driver and the control means for the word line driver sequentially change the read address and the write address sequentially in response to the two word line activation signals. This is a configuration that can be controlled so as to reach the word line driver.

According to a seventh aspect of the present invention, the memory cell comprises one
One storage circuit portion formed by cross-connecting each input terminal and output terminal of a pair of MOS inverter circuits, and one storage circuit portion connected between a pair of storage nodes of the storage circuit portion and a bit line pair. And a static memory cell having a transfer MOSFET.

The semiconductor memory according to the present invention is a static semiconductor memory having a memory cell array composed of a plurality of memory cells and executing a read / write operation in one cycle of a clock, wherein at least N (N Is an integer of 1 or more), a memory cell array including a plurality of memory cells having a plurality of ports, at least 2N address input ports, and at least 2N data input ports and data output ports respectively corresponding to the address input ports. The word line driver activates the word line only for a certain period of time with reference to the first clock edge during reading, and activates the word line only for a certain period of time with reference to the second clock edge during writing. A word line control circuit for generating a word line activation signal to be controlled, and a bit line And a control means for disconnecting between the bit line pair and the sense circuit after reading out the data to the sense circuit, and writing data from the write data line after disconnection between the bit line pair and the sense circuit. And a control means for transmitting the read address to the bit line pair, and the read address among the addresses input from the address input port is set so that the word line is activated only for a predetermined period with reference to the first clock edge. A word line for inputting to the word line driver in response to a word line activation signal to be controlled and for controlling a write address so that the word line is activated only for a certain period of time with reference to the second clock edge. A circuit for inputting to the word line driver in response to an activation signal, and control means therefor;
A data input / output port switching circuit for performing data input / output from the data input port and the data output port corresponding to the address input port, and a control unit therefor; And the input data is written to the write address at the same time as the data is read.

According to a ninth aspect of the present invention, when the word line control circuit performs a read access and a write access in the same cycle, the word line corresponding to the address input in the same cycle with respect to each clock edge is set. The word line activation signal is set to 2 so that each is activated.
And a circuit for inputting to the word line driver and a control means therefor are arranged so that address inputs are sequentially sent to the word line driver in response to the two word line activation signals. The configuration is such that it can be controlled to reach.

According to a tenth aspect of the present invention, the memory cell comprises:
One storage circuit unit formed by cross-connecting each input terminal and output terminal of a pair of MOS inverter circuits, and at least one of the storage circuit units connected between a pair of storage nodes and a bit line pair. It is configured by a static memory cell having a pair of transfer MOSFETs.

In the static semiconductor memory according to the first, second and seventh aspects of the present invention, a one-port SRAM cell is used as a memory cell, and a read operation is performed based on a first clock edge. Time is second
Is controlled so that the word line is activated only for a certain period of time based on the clock edge of. Further, when a read access and a write access occur in the same cycle, the word line is controlled to be activated twice in the same cycle with reference to the time, and the data read from the memory cell is transmitted to the sense circuit. After that, the bit line pair is disconnected from the sense circuit, and write data is transmitted from the write circuit to the bit line pair. As a result, the read operation and the write operation for the same SRAM cell, that is, the same address, can be performed simultaneously in one cycle required for the read operation, and the system throughput can be improved.

In the semiconductor memory according to the third and fourth aspects of the present invention, at least one specific bit of input / output bits simultaneously input / output, for example, a specific bit such as a cache memory and an address translation buffer (TLB) is used. Only in this case, the read operation and the write operation can be performed simultaneously in the same cycle, and the system throughput can be improved.

Further, in the semiconductor memory according to the fifth and sixth aspects of the present invention, the word line corresponding to the read address is activated based on the first clock edge, and the write address is activated based on the second clock edge. Control is performed to activate the corresponding word line. Thereby, Claim 1,
In addition to the same operations as those of the inventions described in 2 and 7, in addition to the 1-port SRAM cell having a small area, the 2-port operation of the read operation and the write operation for different addresses is performed in the same manner as the 2-port SRAM. Since they can be implemented simultaneously in cycles, it is possible to improve the throughput of the system and at the same time, to reduce the area.

In the semiconductor memory according to the eighth, ninth and tenth aspects of the present invention, a read operation and a write operation of a static memory having a plurality of input / output ports are simultaneously executed in one cycle required for the read operation. By that
Memory cells having a smaller number of ports than input / output ports can be used, and a small area can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a static semiconductor memory according to a first embodiment of the present invention. FIG. 2 shows the memory cell array 1 of FIG.
FIG. 4 is a circuit diagram of a 1-port SRAM cell 101 constituting 0.

In FIG. 1, a word line control pulse signal 810 generated by a timing control circuit 80 controls a word line driver 70 to activate a word line WL.
Clock signal CLK and control signal SIG are input to timing control circuit 80. AD is address input, 6
0 is a word line decoder. 25 is a common bus line,
Reference numeral 35 denotes a switch for disconnecting the common bus line 25 from the sense circuit 30, and reference numeral 55 denotes a switch for transmitting input data to the common bus line 25.

1-port SRAM cell 101 shown in FIG.
Are commonly used, and the storage node N is cross-coupled between the input and output of a pair of inverter circuits.
1. Data is held in N2. A pair of storage nodes N1,
The data transfer circuits MA1 and MA2 selected by the word line WL are connected to N2, and the bit line pair BL and NB
L inputs and outputs data. ML1 and ML2 are load PMOSFETs and MD1 and MD2 are drive NMOS FEs.
T.

Hereinafter, the operation of the static memory according to this embodiment will be described with reference to the schematic timing waveforms of the main parts shown in FIGS. FIG. 3 shows a schematic waveform of a main part during a read operation.

In the read operation, the word line WL is activated only for a predetermined period by an activation pulse generated based on the first edge of the clock CLK to the timing control circuit 80. Specifically, the timing control circuit 8
At 0, a word line control pulse signal 810 is generated, and the word line driver 70 activates the word line WL only for a certain period. Then, the data of the memory cell 101 is stored in the bit line pair B.
L and NBL, and a small potential difference is generated between the bit line pair BL and NBL. Then, the data of the bit line pair selected by the column switch 20 is transmitted to the common bus line 25. At this time, the sense circuit disconnecting switch 35 is in a connected state, and the potential difference between the pair of bit lines BL and NBL is transmitted to the sense circuit 30. After a certain period of time, the timing control circuit 80 generates the sense circuit activation signal SAE, activates the sense circuit 30, and simultaneously turns off the sense circuit disconnecting switch 35 to disconnect the sense circuit 30 from the common bus line 25. . The data amplified by the sense circuit 30 is output from the data output buffer 40 as a data output DO. When the sense circuit 30 is activated, the sense circuit 30 is disconnected from the bit lines BL and NBL, so that the word line WL may be returned to the inactive state.

FIG. 4 shows a schematic waveform of a main part during a write operation. During a write operation, a write control signal WS generated by the timing control circuit 80
The write control switch 55 is turned on by W, the input data DI is transmitted from the data input buffer 50 to the common bus line 25, and the data corresponding to the data input DI is transmitted to the bit line pair BL, NBL selected by the column switch 20. You. Unlike the reading operation, the word line WL is activated based on the second edge of the clock CLK.
It is controlled by a word line control pulse signal 810. Therefore, when the word line WL is activated, the bit line pair BL,
Input data transmitted to NBL is written to memory cell storage nodes N1 and N2.

FIG. 5 shows schematic waveforms when a read operation and a write operation are performed simultaneously in one cycle. 1
When a read operation and a write operation are performed simultaneously in a cycle, a word line control pulse signal 810 is generated so that the word line WL is activated twice in one cycle. Word line W
L is activated for reading on the basis of the first edge of the clock CLK and activated for writing on the basis of the second edge of the clock CLK in the same manner as the respective references at the time of reading and writing. Is done.

In this operation, first, the clock CL
The word line WL is activated based on the first edge of K, and the read operation is started. Next, the sense circuit activation signal SA
When E is generated, the sense circuit 30 amplifies the signal and the data output DO is made. This is the same as the read operation. On the other hand, at the same time when the sense circuit 30 is activated by the sense circuit activation signal SAE, the sense circuit 30 is disconnected from the common bus line 25 and the pair of bit lines BL and NBL and the sense circuit 30. Thereafter, the write control signal WSW is activated, the write control switch 55 is turned on, and the input data DI is transmitted to the common bus line 25,
The signal is transmitted to the bit line pair BL and NBL through the column switch 20. At this time, since the sense circuit 30 has already been disconnected, the input data and the output data do not affect each other. That is, even if the writing is started and the write data is transmitted to the common bus line 25, the data read from the memory cell 101 is correctly amplified by the sense circuit 30. At this time, the common bus line 25 or the bit line pair B
Even if read data remains on L and NBL, that is, even if a potential difference remains, the potential difference in the case of reading is small, so that write data is immediately transmitted to the bit line pair BL and NBL. Next, the word line WL is activated for the second time for writing, and data is written to the memory cell storage nodes N1 and N2 in the same manner as in the write operation. While the write operation is being performed, the sense circuit 30 and subsequent ones operate, and the data of the memory cell before the write operation is correctly output.

The bit line pair BL, NBL shown in FIG.
Is a bit line pair selected by the column switch 20, which performs the same operation via the common bus line 25 and the column switch 20.

FIG. 6 shows an example of a read circuit and a write circuit of a static memory according to the present invention. In FIG. 6, the sense circuit disconnecting switch 35 is
When the sense circuit activation signal SAE goes to the “H (high)” level at the time of reading, the sense circuit 30 is activated, and at the same time, the sense circuit disconnecting switch 35 is turned off, and the sense circuit 30 and the common bus line are connected. 25 and is cut off. Write control switch 55 is NMOSF
ET, and a write control signal WSW at the time of writing.
At the "H (high)" level, the data input DI to the data input buffer 50 is transmitted to the common bus line 25.

In FIG. 6, the common bus line 25, the sense circuit output 26, the precharge circuit for the pair of bit lines BL and NBL, and the control thereof are not shown.

As described above, according to the first embodiment, the one-port SRAM cell 101 is used as a memory cell, the first edge of the clock CLK is used for reading, and the second edge is used for writing. Are controlled so that the word lines WL are activated only for a certain period of time with reference to the edge of. Further, when a read access and a write access occur in the same cycle, the word line WL is controlled so as to be activated twice in the same cycle based on the time, and the data read from the memory cell 101 is sensed. After being transmitted to 30, the bit line pair BL, NBL and the sense circuit 30 are disconnected, and write data is transmitted from the write circuit to the bit line pair BL, NBL. As a result, the read operation and the write operation for the same SRAM cell, that is, the same address,
They can be executed simultaneously in a cycle, and the system throughput can be improved.

FIG. 7 is a diagram showing the concept of bit control of a static memory according to the second embodiment of the present invention. FIG. 7 shows a case where the output bits are composed of 32-bit normal bits D0 to D31 and a dirty bit DB as a specific bit. The dirty bit DB is used, for example, as a bit for holding information as to whether the data at the address is the same as the data in the main memory.

The operation of the static memory according to the second embodiment will be described. Other configurations are the same as those of the first embodiment shown in FIG. The read operation is performed in the same manner as for all bits. On the other hand, at the time of writing, the normal bits D0 to D31 correspond to the normal bit write control signal WS.
The dirty bit DB as a specific bit is controlled by a dirty bit control signal WSWD. In the case of a normal write operation, both write control signals are activated to write all bits. On the other hand, when the read operation and the write operation are simultaneously performed in one cycle, control is performed so that only the dirty bit control signal WSWD is activated, and the read operation and the intra-cycle operation are performed by the method described in the first embodiment. And writing to. As a result, the read operation and the write operation can be performed simultaneously in only one cycle of the dirty bit DB. These controls are performed by the timing control circuit 80 according to the control signal SIG.

As described above, according to the second embodiment, the read operation and the write operation are simultaneously performed in the same cycle for at least one specific bit among the input / output bits that are simultaneously input / output. it can. For example, specific bits such as information holding bits are added to output bits of a cache memory, an address translation buffer (TLB) and the like in addition to the normal bits. By performing this operation with respect to this specific bit, the information of the bit can be rewritten at the same time as the read operation, and the write cycle conventionally required for rewriting the data of the specific bit after reading can be eliminated. Thereby, the throughput of the system can be improved.

FIG. 8 is a block diagram showing a configuration example of a static memory according to the third embodiment of the present invention. In FIG. 8, the address input has a configuration in which an address input ADR for reading and an address input ADW for writing are independently input. The address selection signal 81 from the timing control circuit 80
1 to control the selector 91 and read address AD
One of R and the write address ADW is transmitted to the word line decoder 60. Other configurations are the same as those of the first embodiment shown in FIG.

FIG. 9 shows schematic waveforms when the read operation and the write operation are simultaneously performed in one cycle in the static memory according to the third embodiment shown in FIG. The case where the read operation and the write operation are performed independently in one cycle is the same as in the first embodiment shown in FIGS.

In the static memory according to the third embodiment, the case where the read operation and the write operation are simultaneously performed in one cycle as described above will be described below. As in the first embodiment, the word line W is output twice in one cycle.
The word line control pulse signal 810 is generated by the timing control circuit 80 so that L is activated. Further, as the word line WL is activated twice in one cycle,
The selector 9 is set so that the read address ADR and the write address ADW are sequentially input to the word line decoder 60.
Control 1 That is, the word line activated for reading based on the first edge of the clock CLK is the word line WL1 corresponding to the read address ADR, and is activated for writing based on the second edge of the clock CLK. The word line becomes the word line WL2 corresponding to the write address ADW.

The data read by activating the word line WL1 is read from the bit line pair BL1 and NBL1 corresponding to the read address ADR, and the common bus line 2
5. Output via the sense circuit 30. On the other hand, at the time of writing, the data input DI is transferred to the data input buffer 5.
0 to the common bus line 25, and data corresponding to the data input DI to the bit line pair BL2, NBL2 selected by the column switch 20, and the word line WL2 is activated, thereby causing the memory cell storage node N1 to be activated. , N2. At this time, the column decoder 20 also
The selector 91 is activated corresponding to the read address ADR and the write address ADW. The difference between FIG. 9 and FIG. 5 based on the first embodiment is that the same word line and bit line pair are selected in FIG.
In FIG. 9, a word line and a bit line pair corresponding to an address input are being selected. In the case of FIG. 9, both the read data and the write data are transmitted to the common bus line 25 of FIG.
Is disconnected from the sense circuit 30, the write control switch 55 is turned on and the input data is transmitted, so that no data conflict occurs. This is the same as in the first embodiment.

As described above, according to the third embodiment, the word line corresponding to the read address is activated on the basis of the first clock edge, and the write line is activated on the basis of the second clock edge. To activate the word line to be activated. As a result, in addition to the same operation as in the first embodiment, the two-port operation of the read operation and the write operation for different addresses can be performed by using the one-port SRAM cell having a small area, similarly to the two-port SRAM. It can be realized simultaneously in one cycle required for operation. Therefore, it is possible to reduce the area while improving the system throughput.

FIG. 10 is a block diagram showing a configuration example of a static memory according to the fourth embodiment of the present invention. In FIG. 10, the address input is to input the A port address input ADA and the B port address input ADB independently, and the selector 91 selects the input address. Further, it has two data input / output ports, A port and B port, and selects data input / output by selectors 92 and 93.
DOA is data output of A port, DOB is data output of B port, DIA is data input of A port, DIB is B
Port data input. Reference numeral 812 denotes an input / output port selection signal from the timing control circuit 80 to the selectors 92 and 93. Other configurations are the same as those of the third embodiment.

The operation is such that the data input / output has two ports and is selected by the selectors 92 and 93, and the address and data input / output two ports can be used for both reading and writing. Except for this, the third embodiment is the same as the third embodiment. Specifically, the read operation is performed by the selector 91 selecting an address input on the port side designated for the read, and selecting a word line and a bit line pair corresponding to the address input. For the data output, the selector 92
This is done by selecting In the write operation, the data input on the port side designated for the write is selected by the selector 9.
3 is selected, and the selector 91 selects a word line and a bit line pair corresponding to the address input on the port side designated for writing.

As described above, since both the address and the data input / output have two ports, the read operation from the A port and the write operation from the B port, and conversely, the read operation from the B port and the write operation from the A port The read operation and the write operation can be performed from either port. In other words, two operations of a read operation and a write operation can be simultaneously performed on any two ports in one cycle using a one-port SRAM cell having a small area.

Here, a case where two ports are applied to a one-port SRAM cell has been described.
If cells are used, read operation from two ports and 2
A total of four port operations including a write operation from one port can be simultaneously executed in one cycle. Further, if an N-port SRAM cell having N pairs of data transfer circuits is used, a total of 2N port operations of a read operation from N ports and a write operation from N ports can be simultaneously executed in one cycle. .

Thus, even in a cache memory used together with a processor that issues a plurality of instructions at the same time, such as a superscalar processor, by simultaneously executing a read operation and a write operation, an SRAM having a smaller number of ports than the required number of ports can be realized. Can be used.

As described above, according to the fourth embodiment, the read operation and the write operation of the static memory having a plurality of input / output ports are simultaneously executed in one cycle necessary for the read operation. , Memory cells with fewer ports than input / output ports can be used,
Small area can be realized.

[0060]

As described above, according to the present invention,
Since the word line is activated only for a certain period of time on the basis of the first clock edge at the time of reading and on the basis of the second clock edge at the time of writing, the read operation and the write operation for the same address can be read and written. The operations can be performed simultaneously in one cycle required for the operation, and the system throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a static semiconductor memory according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a one-port SRAM cell forming the memory cell array shown in FIG. 1;

3 is a diagram showing a schematic waveform at the time of a read operation in the semiconductor memory of FIG. 1;

FIG. 4 is a diagram showing a schematic waveform during a write operation in the semiconductor memory of FIG. 1;

5 is a diagram showing a schematic waveform at the time of simultaneous read / write operation in the semiconductor memory of FIG. 1;

FIG. 6 is a diagram illustrating an example of a read circuit and a write circuit in the semiconductor memory of FIG. 1;

FIG. 7 is a diagram illustrating a concept of bit control of a static semiconductor memory according to a second embodiment of the present invention;

FIG. 8 is a block diagram illustrating a configuration example of a static semiconductor memory according to a third embodiment of the present invention;

9 is a diagram showing a schematic waveform at the time of simultaneous read / write operation in the semiconductor memory of FIG. 8;

FIG. 10 is a block diagram illustrating a configuration example of a static semiconductor memory according to a fourth embodiment of the present invention;

FIG. 11 is a block diagram illustrating a configuration example of a conventional two-port static memory.

FIG. 12 is a circuit diagram showing a two-port SRAM cell forming the memory cell array in FIG. 11;

[Description of Signs] 10 Memory cell array 30 Sense circuit 35 Sense circuit disconnection switch 40 Data output buffer 50 Data input buffer 55 Write control switch 80 Timing control circuit 810 Word line control pulse signal DO Data output DI Data input AD Address input BL, NBL Bit line pair WL word line

Claims (10)

[Claims] 1. A static semiconductor memory comprising a memory cell array composed of a plurality of memory cells and performing a read / write operation in one cycle of a clock, wherein a read operation is performed only for a predetermined period based on a first clock edge. A word line control circuit for generating a word line activation signal for activating the word line and activating the word line only for a certain period of time with reference to a second clock edge during writing; and sensing data of the bit line pair. A circuit for disconnecting between the bit line pair and the sense circuit after reading to the circuit, and control means therefor; and, after disconnection between the bit line pair and the sense circuit, write data is transferred from the write data line to the bit line pair. And a control means for transmitting the data to the same memory cell simultaneously with the reading within one cycle required for the reading. Semiconductor memory is characterized in that to perform the write. 2. The word line control circuit according to claim 1, wherein when a read access and a write access occur in the same cycle, the word line control circuit activates the same word line twice in the same cycle with reference to each clock edge. 2. The semiconductor memory according to claim 1, wherein said semiconductor memory is configured to generate an activation signal. 3. A static semiconductor memory comprising a memory cell array composed of a plurality of memory cells and executing a read / write operation in one cycle of a clock, wherein a read operation is performed only for a predetermined period based on a first clock edge. A word line control circuit for generating a word line activation signal for activating the word line and activating the word line only for a certain period of time with reference to a second clock edge during writing; and sensing data of the bit line pair. A circuit for disconnecting between the bit line pair and the sense circuit after reading out to the circuit, and control means for the circuit; and at least one specific bit and another bit among input / output bits which are simultaneously input / output are independent of each other. A control circuit capable of controlling the writing, and for the specific bit, writing after the disconnection between the bit line pair and the sense circuit. A circuit for transmitting write data from the data line to the bit line pair and a control means therefor, and in one cycle required for reading, writing to the memory cell of the specific bit is performed simultaneously with reading. Characteristic semiconductor memory. 4. The word line control circuit activates the same word line twice in the same cycle based on each clock edge when writing data only to the specific bit in the same cycle as the data read cycle. 4. The semiconductor memory according to claim 3, wherein said semiconductor memory is configured to generate a word line activation signal. 5. A static semiconductor memory comprising a memory cell array composed of a plurality of memory cells and performing a read / write operation in one clock cycle, wherein a read address and a write address can be input independently of each other. The word line is activated only for a certain period of time with reference to the first clock edge during reading, and the word line is activated only for a certain period of time with reference to the second clock edge during reading. A word line control circuit that generates a word line activation signal that controls the word line driver to make it active, and disconnects the bit line pair and the sense circuit after reading the data of the bit line pair to the sense circuit After disconnection between the bit line pair and the sense circuit , A circuit and a control unit transmitting the bit line pair to write data from the write data line, in the address inputted from the address input port,
A read address is input to the word line driver in response to a word line activation signal for controlling a word line to be in an active state only for a predetermined period with reference to the first clock edge, and a write address is input to the word line driver. The second
A circuit for inputting to the word line driver in response to a word line activation signal for controlling the word line to be in an active state only for a certain period based on the clock edge of A semiconductor memory in which data at the read address is read and data is written to the write address within one required cycle. 6. The word line control circuit according to claim 1, wherein when performing read access and write access in the same cycle, the word lines corresponding to the address inputs are activated based on respective clock edges in the same cycle. The word line activation signal is generated twice, and a circuit for inputting to the word line driver and its control means are provided with a read address and a read address corresponding to each of the two word line activation signals. 6. The semiconductor memory according to claim 5, wherein the write address can be controlled so as to sequentially reach the word line driver. 7. A memory cell, comprising: a storage circuit portion formed by cross-connecting each input terminal and output terminal of a pair of MOS inverter circuits; a pair of storage nodes of the storage circuit portion and a bit line pair And a pair of transfer Ms respectively connected between
7. The semiconductor memory according to claim 1, comprising a static memory cell having an OSFET. 8. A static semiconductor memory comprising a memory cell array composed of a plurality of memory cells and performing a read / write operation in one clock cycle, wherein at least N (N is an integer of 1 or more) multiple ports A memory cell array comprising a plurality of memory cells having at least 2N address input ports, at least 2N data input ports and data output ports respectively corresponding to the address input ports, and a first clock edge at the time of reading. A word line activation signal for controlling the word line driver so that the word line is activated only for a certain period of time based on the second clock edge during writing, and the word line is activated only for a certain period of time based on the second clock edge. Read word line control circuit and bit line pair data to sense circuit A circuit for disconnecting the bit line pair and the sense circuit and control means therefor; a circuit for transmitting write data from the write data line to the bit line pair after the disconnection between the bit line pair and the sense circuit; and The control means, of the addresses input from the address input port,
A read address is input to the word line driver in response to a word line activation signal for controlling a word line to be in an active state only for a predetermined period with reference to the first clock edge, and a write address is input to the word line driver. The second
A circuit for inputting to the word line driver in response to a word line activating signal for controlling a word line to be in an active state only for a predetermined period based on a clock edge of A data input / output port switching circuit for inputting / outputting data from / to the data input port and the data output port, and a control unit therefor. Semiconductor memory, wherein input data is written to the write address. 9. The word line control circuit, when performing a read access and a write access in the same cycle, activates a word line corresponding to an address input based on each clock edge in the same cycle. A circuit for generating a word line activation signal twice, and a circuit for inputting the word line driver and a control means thereof, have an address input corresponding to each of the two word line activation signals. 9. The semiconductor memory according to claim 8, wherein the semiconductor memory can be controlled so as to sequentially reach the word line driver. 10. A memory cell comprising a pair of MOS inverter circuits each having an input terminal and an output terminal cross-coupled.
At least one storage circuit unit and at least one storage node connected between a pair of storage nodes of the storage circuit unit and a bit line pair.
10. A static memory cell having a pair of transfer MOSFETs.
The semiconductor memory according to any one of the preceding claims.