JP2000165235A - Charge pump circuit and pll frequency synthesizer circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a phase noise while increasing a speed of a lockup time by utilizing a delay of a gate of a phase difference signal outputted from a phase comparator. SOLUTION: A PLL frequency synthesizer circuit 16 comprises a reference frequency divider 2, a comparison frequency divider 3, a phase comparator 4, delay circuits 5A, 5B, and a charge pump circuit 17. The charge pump circuit 17 has constant current source circuits 6-9 and transistors(TRs) 10-13. The delay circuits 5A, 5B delay a phase difference signal being an output signal of the phase comparator 4 and the delay signals are given to the TRs 10-13 so that an output energy of the charge pump circuit 17 is increased when the phase difference is higher and an output energy of the charge pump circuit 17 is decreased to a degree not deteriorating the phase noise when the phase difference is smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit used in communication equipment such as a portable telephone and a cordless telephone, and a PLL frequency synthesizer circuit using the same. And a PLL frequency synthesizer circuit using the same.

[0002]

2. Description of the Related Art In recent years, with the spread of portable telephones, cordless telephones and the like, PLL frequency synthesizer circuits used in the above-mentioned communication equipment have been simultaneously switched with high-speed frequencies.
It is required that phase noise and the like be sufficiently removed. A PLL frequency synthesizer circuit is a system that creates a plurality of desired output frequencies from a certain reference frequency, but the frequency switching speed and the presence of phase noise, etc.
The magnitude of the output current of the charge pump circuit is related, and various measures have been devised for these improvements.
Hereinafter, two typical examples of the related art will be described.

<Conventional Example 1> As a conventional example 1, there is a PLL frequency synthesizer circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 5-308283, which will be described with reference to FIGS. As shown in FIG. 9, the PLL comprises a crystal oscillator 1, a reference frequency divider 2, a comparative frequency divider 3, a phase comparator 4, charge pump circuits 21A and 21B, a low-pass filter (hereinafter, LP).
F) 14, a voltage controlled oscillator (hereinafter, VCO) 15, and the like.

A reference frequency divider 2 divides an oscillation signal of a predetermined frequency of the crystal oscillator 1 into a reference frequency and outputs a reference signal fr shown in FIG. The comparison frequency divider 3 divides the output signal fv input from the VCO 15 based on the set frequency and outputs a comparison signal fp. The reference signal fr of the reference frequency divider 2 is input to the phase comparator 4, and the comparison frequency divider 3
Is input. Then, the phase comparator 4 compares the phases of the reference signal fr and the comparison signal fp,
The phase difference signals φR and φP based on the comparison result are output. Further, the phase comparator 4 includes a charge pump circuit 2
1A is connected and the charge pump circuit 21B
And the output terminals of both charge pump circuits 21A and 21B are connected to node α.

The charge pump circuits 21A and 21B have a PNP transistor Tr1 whose emitter terminal is connected to the power supply Vcc, a collector terminal connected to the collector terminal of the NPN transistor Tr2, and a collector terminal PN.
An NPN transistor Tr2 is connected to the collector terminal of the P transistor Tr1 and the emitter terminal is connected to the ground GND. The phase difference signal φR output from the phase comparator 4 is input to the base terminal of the PNP transistor Tr1, and the phase difference signal φP output from the phase comparator 4 is input to the base terminal of the NPN transistor Tr2. Then, PNP based on the level of the phase difference signal φR
By controlling the transistor Tr1 and controlling the NPN transistor Tr2 based on the level of the phase difference signal φP, the charge pump circuits 21A and 21
B outputs the voltage signal Do to the LPF 14. LPF
14 outputs an output signal Vt based on the level of the voltage signal Do, and the VCO 15 outputs an output signal fv having a frequency corresponding to the voltage value of the output signal Vt.
Will be returned to

FIG. 10 is a timing chart showing the operation of the PLL frequency synthesizer circuit 20. now,
During a period (E) in which the phase of the comparison signal fp of the comparison frequency divider 3 is faster than the phase of the reference signal fr of the reference frequency divider 2, the phase difference signal φR of the phase comparator 4 is held at the H level, The phase difference signal φP includes a positive pulse (H level pulse) of the phase difference. Therefore, during the period (E) in which the phase of the comparison signal fp is faster than the phase of the reference signal fr, each NPN of the charge pump circuits 21A and 21B is based on the positive pulse of the phase difference signal φP.
During the period when the transistor Tr2 is turned on and off and the positive pulse of the phase difference signal φP exists, the voltage signals Do1 and Do2 of the charge pump circuits 21A and 21B are controlled so as to decrease.

During a period (F) in which the phase of the comparison signal fp of the comparison frequency divider 3 is later than the phase of the reference signal fr of the reference frequency divider 2, the phase difference signal φP of the phase comparator 4 is L
And the phase difference signal φR includes a negative pulse (L level pulse) of the phase difference. Accordingly, during the period (F) in which the phase of the comparison signal fp is later than the phase of the reference signal fr, the charge pump circuits 21A, 21A,
During the period in which each of the PNP transistors Tr1 of 21B is turned on and off and the negative pulse of the phase difference signal φR exists, the voltage signals Do1, Do2 of the charge pump circuits 21A, 21B are controlled to increase.

Here, the energy level of the voltage signal Do at the node α is, as shown in FIG.
1 and Do2, the output signal Vt of the LPF 14 increases / decreases at twice the speed as compared with the case of only one of the voltage signals Do1 and Do2. As a result, the output signal fv of the VCO 15 increases / decreases at twice the speed.

That is, the two charge pump circuits 21
A, 21B are provided, and a voltage signal Do is output from each of the charge pump circuits 21A, 21B based on the phase difference signals φP, φR.
1 and Do2 are output to the LPF 14,
The load driving capability can be doubled, and the conversion gain of the phase comparator 4 and the charge pump circuits 21A and 21B can be improved to shorten the lock-up time.

<Conventional Example 2> Next, as a conventional example 2, there is a charge pump circuit disclosed in Japanese Patent Application Laid-Open No. 10-65531 and a phase locked loop circuit using the same, as shown in FIG. FIG.
2, the phase comparator 51 includes a charge pump circuit 3
8 is connected to the charge pump circuit 38 and the control voltage V
An LPF 40, which is a voltage setting device for setting c, is connected. A VCO 50 that generates a clock CK2 by oscillation based on the control voltage Vc is connected to the output side of the LPF 40. This clock CK2 is input to the phase comparator 51 as a feedback signal. The phase comparator 51 compares the phase of the reference clock CK1 with the phase of the feedback clock CK2 from the VCO 50, and compares the comparison result with two pulse signals Su and Sd.
Is output by using. The signal Su is the clock C
The signal Sd is an up signal for increasing the phase of K2, and the signal Sd is a down signal for decreasing the phase of the clock CK2. When the phase of the feedback clock CK2 is delayed as a result of the comparison, the phase comparator 51 forms a pulse having a width corresponding to the phase difference in the signal Su, and when the phase of the output clock CK2 is advanced, A pulse having a width corresponding to the phase difference is applied to the signal S.
d.

The charge pump circuit 38 is a P-channel MO which is a switching element for inputting a signal Su to a gate.
An N-channel MOS transistor 23 serving as a switching element having a gate input with a signal Sd1 via an S transistor 22 and an inverter 29c for inverting the signal Sd.
And P channel MO corresponding to node N1a
Between the source of the S transistor 22 and the power supply Vcc,
Constant current source circuits 24a and 24 constituting three current control means
4b and 24c are connected in series, and the source of N-channel MOS transistor 23 corresponding to node N1b and ground GN
Constant current source circuits 25a, 25b, and 25c constituting three current control means are connected in series with D.

The drain of the P-channel MOS transistor 22 and the drain of the N-channel MOS transistor 23 are connected, and the portion where the drains are connected is the output terminal 26 of the charge pump circuit 38. The above constant current source circuits 24a to 24c and 25a to 25c form a plurality of resistors. That is, each of the constant current source circuits 24a-2
4c, the internal resistances in 25a to 25c form a current path of the charging / discharging current and also act to make the value of the charging current or the discharging current constant.

The charge pump circuit 38 further has two pulse width conversion circuits 27 for receiving pulses formed in the signal Su and outputting pulses of different widths.
27a and 27b, two pulse width conversion circuits 28a and 28b for inputting pulses formed in the signal Sd and outputting pulses of different widths, and the pulse width conversion circuits 28a and 28b.
Inverters 29a, 29 connected to the output side of 8b, respectively.
b, a switch circuit 30 having two switches 30a and 30b, and a switch circuit 31 having two switches 31a and 31b.

FIG. 13 shows the pulse width conversion circuit 2 shown in FIG.
It is a circuit diagram which shows the structure of 7a, 27b, 28a, 28b. Each pulse width conversion circuit 27a, 27b, 28a, 28
b denotes an inverter 33 that receives the signal Su or the signal Sd, a resistor 34 having one end connected to the output side of the inverter 33, one electrode connected to the other end of the resistor 34, and the other electrode connected to the ground GND. A capacitor 35 connected to
It comprises an inverter 37 connected to a connection point 36 between a resistor 34 and a capacitor 35. That is, the insides of the pulse width conversion circuits 27a, 27b, 28a, and 28b are connected in the same manner, but the capacitor value of the capacitor 35 and the resistance value of the resistor 34 each have a time constant unique to each pulse width conversion circuit. It is possible to set.

Next, the operation of the conventional example 2 shown in FIG.
This will be described with reference to FIGS. FIG. 15 is a time chart when the phase of the clock CK2 is delayed with respect to the reference clock CK1. At this time, the phase comparator 51 supplies the signal Su with the L-level first pulse P1 having a width corresponding to the phase difference φ.
Is formed and output. The pulse P1 formed in the signal Su
Is applied to the gate of P-channel MOS transistor 22, and P-channel MOS transistor 22 is turned on. Further, the pulse P1 is supplied to the pulse width conversion circuits 27a, 27
b. At this time, the signal Sd is maintained at the H level, and the signal Sd1 inverted by the inverter 29c is maintained at the L level. Therefore, N-channel MOS transistor 23 is off.

FIG. 14 is a waveform chart for explaining the operation of the pulse width conversion circuit of FIG. In FIG. 14, the input signal Su has its logic level inverted by an inverter 33, that is,
When pulse P1 is applied, the voltage level output from inverter 33 rises, and capacitor 35 is charged via resistor 34. This charging causes the voltage at the connection point 36 to rise. Inverter 37 determines the voltage at node 36 based on threshold value Vth, and outputs “L” as the determination result. Here, the voltage rise at the connection point 36 depends on the time constant set by the resistor 34 and the capacitor 35, and the voltage rise at the connection point 36 in the pulse width conversion circuit having a small time constant is fast. After the period of the pulse P1, the output voltage of the inverter 33 decreases and the voltage of the connection point 36 also decreases, and the inverter 37 outputs "H". That is, since each of the pulse width conversion circuits 27a and 27b has a different time constant, the pulse width of the pulse P1 is changed, and pulses having different widths are formed and output (compared with the pulse width conversion circuit 27a). The time constant of the pulse width conversion circuit 27b is set large.

For example, when the phase difference φ between the reference clock CK1 and the returned clock CK2 is large, as in the period (1) shown in FIG. 15, the pulse width conversion circuit 27a has a width smaller than the width of the pulse P1. The pulse P2 is output, and the pulse width conversion circuit 27b outputs a pulse P3 having a smaller pulse width. These pulses P
2 and P3, switches 30a and 30b are turned on,
The constant current source circuits 24a and 24b are short-circuited, and the constant current source circuit 24c is connected to the power supply Vcc. In this state, it is equivalent to connecting only the internal resistance of constant current source circuit 24c between the source of P-channel MOS transistor 22 and power supply Vcc, and is set by the internal resistance of constant current source circuit 24c. The capacitor 42 is charged by the current via the resistor 41.

As shown in a period (2) in FIG. 15, the phase difference φ between the reference clock CK1 and the feedback clock CK2.
Is smaller, the pulse width conversion circuit 27a outputs a pulse P2 having a width smaller than the width of the pulse P1. However,
The pulse width conversion circuit 27b does not output the pulse P3 because there is no charging time for raising the voltage of the connection point 36 to the threshold voltage Vth or more. In this case, the pulse P2
As a result, the switch 30a is turned on, and the constant current source circuit 24a
Is short-circuited, and the constant current source circuits 24b and 24c
cc. That is, the constant current source circuit 2 is connected between the source of the P-channel MOS transistor 22 and the power supply Vcc.
4c and the internal resistance of the constant current source circuit 24b are connected in series, and the capacitor 42 is charged via the resistor 41 with the current set by these series internal resistances.

As shown in a period (3) in FIG. 15, the phase difference φ between the reference clock CK1 and the returned clock CK2.
Is smaller than (2), the pulse width conversion circuit 2
Also in 7a, the charging time is not enough and the pulse P2 is not output.
In this case, the switches 30a and 30b are both off,
The constant current source circuits 24a, 24b, 24c in series
c. That is, the constant current source circuit 24 is connected between the source of the P-channel MOS transistor 22 and the power supply Vcc.
The internal resistors a, 24b, and 24c are connected in series, and the capacitor 42 is charged via the resistor 41 with a current set by the series internal resistors.

FIG. 16 is a time chart when the phase of the clock CK2 is advanced with respect to the reference clock CK1. At this time, the phase comparator 51 forms and outputs an L-level second pulse P4 having a width corresponding to the phase difference φ to the signal Sd. The pulse P4 formed in the signal Sd is output from the inverter 2
At 9c, the pulse is inverted to the H level and becomes a pulse P4, which is applied to the gate of the N-channel MOS transistor 23, and the N-channel MOS transistor 23 is turned on. The pulse P4 is also given to the pulse width conversion circuits 28a and 28b. On the other hand, the signal Su is maintained at the H level. Therefore, P channel MOS transistor 22 is off.

FIG. 13 is a circuit diagram of the pulse width conversion circuits 28a and 28b.
When the phase difference between the reference clock CK1 and the returned clock CK2 is large as in the period (4) shown in FIG. 16, for example, the pulse width conversion circuit 28a outputs the pulse P4 Of the pulse width conversion circuit 28b, the pulse width conversion circuit 28b outputs a pulse P6 having a width smaller than that of the pulse width conversion circuit 28b (compared to the pulse width conversion circuit 28a, The time constant of the circuit is set large.) Pulses P5 and P inverted through inverters 29a and 29b
6, the switches 31a and 31b are turned on, the constant current source circuits 25a and 25b are short-circuited, and the constant current source circuits 25c
Are connected to the ground GND. In this state, it is equivalent to connecting only the internal resistance of constant current source circuit 25c between the source of N-channel MOS transistor 23 and ground GND, and is set by the internal resistance of constant current source circuit 25c. The capacitor 42 is discharged via the resistor 41 with a current flowing through the resistor 41.

When the phase difference between the reference clock CK1 and the returned clock CK2 is small as in the period (5) shown in FIG. 16, the pulse width conversion circuit 28a
A pulse width P5 having a width smaller than the width of P4 is output. However, the pulse width conversion circuit 28b does not output the pulse P6 because there is no charging time for raising the voltage at the connection point 36 to the threshold Vth or more. In this case, the switch 31a is turned on by the pulse P5, only the constant current source circuit 25a is short-circuited, and the constant current source circuits 25b and 25c are connected to the ground GN.
D is connected. That is, the constant current source circuit 2 is connected between the source of the N-channel MOS transistor 23 and the ground GND.
This is equivalent to the fact that the internal resistance 5c and the internal resistance of the constant current source circuit 25b are connected in series, and the capacitor 42 is discharged via the resistance 41 with a current set by these internal resistances.

If the phase difference between the reference clock CK1 and the clock CK2 fed back is smaller than that of (5) as in the period (6) shown in FIG. 16, the pulse width conversion circuit 28a also has a sufficient charging time. And the pulse width P5 is not output. In this case, the switches 31a and 31b are both off, and the series constant current source circuits 25a, 25b and 25c
Are connected to the ground GND. That is, N-channel MOS
Constant current source circuits 25a, 25b, 25c are connected in series between the source of the transistor 23 and the ground GND, and the capacitor 42 is discharged via the resistor 41 with a current set by the series internal resistance. .

As described above, in the second prior art, the pulse width conversion circuits 27a, 27b, 28a, 28 which change the widths of the pulses P1, P4 to form pulses having different widths from each other.
b and switch circuits 30 and 31 are provided to selectively short-circuit the constant current source circuits 24a to 24c and 25a to 25c arranged on the charge / discharge route in the charge pump circuit 38 in accordance with the widths of the pulses P1 and P4. ing. Therefore, the lock-up time when the phase difference φ is large as in the initial stage of control can be shortened, and the control proceeds and the phase difference φ
Is small, a PLL synthesizer circuit that does not cause an increase in phase difference noise by reducing the current of the charge pump output can be configured.

[0025]

However, in the first conventional example, a P-type switch using two or more charge pump circuits is simply used.
In the LL frequency synthesizer circuit, the lock-up time is shortened because the energy output from the charge pump circuit is large, but the voltage signal Do at the node α becomes unstable, the oscillation frequency of the VCO 27 fluctuates, and the jitter increases. become. That is, when the phase difference is large as in the initial stage of the phase synchronization operation process, it is better that the output energy of the charge pump circuit is large. The smaller the energy of the output, the better. However, in the PLL frequency synthesizer circuit using the charge pump circuit of the conventional example 1, the output current of the charge pump circuit is constant regardless of the phase difference, that is, the output energy of the charge pump circuit is proportional to the phase difference. Therefore, when the energy is large, the jitter is increased, that is, the phase noise is deteriorated. When the energy is small, the lock-up time is prolonged.

In the PLL frequency synthesizer circuit of the second conventional example, a circuit using a resistor and a capacitor, such as a pulse width conversion circuit, is easily affected by variations in process steps. Are connected in series, the switch circuits 30, 3
The phase difference signal input to 1 may be a simple delay by an inverter or the like, and it is not necessary to change the pulse width. That is,
When a pulse width conversion circuit that is easily affected by variations in process steps is used, parameters other than Vth of a transistor that largely determines the performance of the device are further increased, so that the variation in lock-up time and phase noise value is increased depending on the device. There was a problem. Furthermore, I
There is also a problem that realizing a resistor or a capacitor on C causes an increase in area.

An object of the present invention is to use a delay of a gate of a phase difference signal output from a phase comparator to reduce a phase noise while shortening a lock-up time. And a PLL frequency synthesizer circuit using the same.

[0028]

According to a first aspect of the present invention, there is provided a charge pump circuit for outputting a voltage signal based on an input pulse, wherein the delay circuit outputs a delay signal obtained by delaying the input pulse by a predetermined time. A first switching element that is turned on / off by the input pulse; a second switching element that is turned on / off by the delay signal; and a constant current power supply connected to one end of the switching element. Then, the output of the second switching element is added to the output from the other end of the first switching element turned on by the input pulse.

The invention according to claim 2 is the charge pump circuit according to claim 1, wherein the other end of the second switching element is connected to the other end of the first switching element.

The invention according to claim 3 is the charge pump circuit according to claim 1, wherein one end of the first switching element is connected to the other end of the second switching element.

According to a fourth aspect of the present invention, there is provided a PLL frequency synthesizer circuit for outputting a signal of a desired frequency based on an oscillation signal of a predetermined frequency and a feedback signal from a voltage-controlled oscillator arranged in an output stage. A reference frequency divider that divides the frequency of the feedback signal to output a reference signal, a comparison frequency divider that divides the feedback signal based on a set frequency and outputs a comparison signal, A phase comparator that performs a phase comparison and outputs a phase difference signal; and a charge pump circuit that receives the phase difference signal and outputs a voltage signal based on the phase difference signal. The charge pump circuit includes a delay circuit that outputs a delay signal obtained by delaying the phase difference signal by a predetermined time, a first switching element that is turned on / off by the phase difference signal, and that is turned on / off by the delay signal. A second switching element to be turned off; and a constant current power supply connected to one end of the switching element. Further, the output from the other end of the first switching element turned on by the phase difference signal is connected to a second switching element.
The outputs of the switching elements are added.

The invention according to claim 5 is the PLL frequency synthesizer circuit according to claim 4, wherein the other end of the second switching element is connected to the other end of the first switching element.

According to a sixth aspect of the present invention, there is provided the PLL frequency synthesizer circuit according to the fourth aspect, wherein one end of the first switching element is connected to the other end of the second switching element.

According to the present invention, the input pulse is delayed by a simple delay circuit, the input pulse is connected to the first switching element, and the delayed signal is connected to the second switching element to be turned on / off. The overlap time of the pulse width with the delay signal is proportional to the pulse width of the input pulse. Therefore, as the input pulse width increases, the overlap time of the pulse width with the delay signal increases, and the time during which the first switching element and the second switching element are commonly turned on increases.
Therefore, the output energy of the charge pump circuit increases. On the other hand, if the input pulse width is small, the time during which the first switching element and the second switching element are on in common decreases. Therefore, the output energy of the charge pump circuit decreases.

When such a charge pump circuit is used in a PLL frequency synthesizer circuit and a phase difference signal between a reference signal and a comparison signal is used as an input pulse, when the phase difference is large, the output energy of the charge pump circuit is increased, and When the phase difference is small, the output energy of the charge pump circuit is reduced to such an extent that the phase noise does not deteriorate.
As a result, by using the delay of the gate of a simple inverter or the like of the phase difference signal output from the phase comparator, it is possible to solve the contradictory problems of increasing the lock-up time and reducing the phase noise. .

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1> Embodiment 1 according to the present invention will be described with reference to FIGS. For convenience of description, the same components as those in FIGS. 9 and 12 are denoted by the same reference numerals, and the description thereof is partially omitted. In FIG. 1, the PLL
The frequency synthesizer circuit 16 includes a reference frequency divider 2, a comparison frequency divider 3, a phase comparator 4, and a charge pump circuit 17, and includes a crystal oscillator 1, an LPF 14, and a VCO 15
It has.

The reference frequency divider 2 divides an oscillation signal of the crystal oscillator 1 having a predetermined frequency into a reference frequency to obtain a reference signal fr. The comparison frequency divider 3 divides the output signal fv input from the VCO 15 based on the set frequency, and outputs a comparison signal fp. The phase comparator 4 includes a reference signal fr and a comparison signal f.
With p as an input, the two signals are compared, and phase difference signals φR and φP based on the comparison result are output.

The charge pump circuit 17 includes a delay circuit 5
A, 5B, constant current source circuits 6, 7, 8, 9 and P channel M
It comprises OS transistors 10 and 11 and N-channel MOS transistors 12 and 13. One end of the constant current source circuit 6 is connected to the power supply Vcc, and the other end is connected to the source terminal of the P-channel MOS transistor 10. One end of the constant current source circuit 7 is connected to the power supply Vcc, and the other end is connected to the source terminal of the P-channel MOS transistor 11. One end of the constant current source circuit 8 is connected to the ground GND, and the other end is N
Connected to the source terminal of channel MOS transistor 12. One end of the constant current source circuit 9 is connected to the ground GND,
The other end is connected to the source terminal of N-channel MOS transistor 13. P-channel MOS transistors 10, 1
1 and the drain terminals of the N-channel MOS transistors 12 and 13 are connected to the node α.

Also, the phase difference signal φR is a P-channel MO
Delay signal φRd input to the gate terminal of S transistor 10 and delaying phase difference signal φR by delay circuit 5A
Is input to the gate terminal of the P-channel MOS transistor 11. The phase difference signal φP is an N-channel MOS
The delay signal φPd input to the gate terminal of the transistor 12 and delaying the phase difference signal φP by the delay circuit 5B is
The signal is input to the gate terminal of the N-channel MOS transistor 13.

Here, FIGS. 2 and 3 show delay circuits 5A and 5A.
1 shows a circuit diagram of B and its operation. If the number of stages of the inverter in FIG. 2 is increased, the amount of delay increases. In this case, for example, the number of stages is four, and the amount of delay is τ (the delay at the rise is τ
B, on the other hand, the delay at the time of falling is τA).
Generally, when a delay operation is performed by an inverter circuit, if the signal input to the input terminal IN has a certain width W1, a signal delayed by the delay amount τ is output to the output terminal OUT. Output terminal OU
At T, there is a phenomenon that the signal of the width W2 is not output (see FIG. 3). The width W2 is several hundred ps, although there are differences depending on the process steps.

FIG. 4 is a time chart showing the operation of the PLL frequency synthesizer circuit. Now, during a period (A) in which the phase of the comparison signal fp of the comparison frequency divider 3 is faster than the phase of the reference signal fr of the reference frequency divider 2, the phase difference signal φR is held at the H level, while the phase difference signal φR is maintained at the H level. The signal φP includes a positive pulse having the phase difference. Since the phase difference signal φR that is the input of the delay circuit 5A is at the H level, the phase difference signal φRd that is the output is held at the H level, and the transistors 10 and 11 are turned off. On the other hand, the phase difference signal φPd output from the delay circuit 5B is obtained by delaying the input phase difference signal φP by the time τB. However, when the phase difference between the reference signal fr and the comparison signal fp is close and the width WB of the phase difference signal φP is equal to or smaller than the width W2 in FIG. 3, the phase difference signal φPd output from the delay circuit 5B is positive. No pulse is output.

Similarly, during a period (B) in which the phase of the comparison signal fp of the comparison frequency divider 3 is later than the phase of the reference signal fr of the reference frequency divider 2, the phase difference signal φP is held at L level. On the other hand, the phase difference signal φR includes a negative pulse of the phase difference. Since the phase difference signal φP, which is the input of the delay circuit 5B, is at the L level, the phase difference signal φPd, which is the output, is held at the L level.
2, 13 are turned off. On the other hand, the phase difference signal φRd output from the delay circuit 5A is obtained by delaying the input phase difference signal φR by the time τA. However, when the phase difference between the reference signal fr and the comparison signal fp becomes close and the width WA of the phase difference signal φR becomes smaller than the width W2 in FIG. 3, the phase difference signal φRd output from the delay circuit 5A is negative. No pulse is output.

From the above, the period (A) in FIG.
Since the phase difference signal φR and the delay signal φRd attain the H level, the P-channel MOS transistor 1
0, 11 maintain the off state. On the other hand, N channel MO
The S transistors 12 and 13 are turned on while the phase difference signal φP and the delay signal φPd are at the H level. As a result, while the transistor 12 is on, a current is drawn at the node α by the constant current source circuit 8 (current waveform Do1 in FIG. 4A). Further, while the transistor 13 is on, a current is drawn at the node α by the constant current source circuit 9 (FIG. 4).
(A) of the current waveform Do2).

The current waveform at the actual node α is Do, and this waveform is the sum of the above-mentioned Do1 and Do2. If the phase difference is large, the delayed phase difference signal φPd
Since the level state is present, the level is added by the constant current source circuits 8 and 9. However, if the phase difference becomes small and the width WB of the H level of the phase difference signal φP becomes equal to or less than W2, the H level of the delay signal φPd disappears.
Only the current is drawn by the constant current source circuit 8 during the H level period of the phase difference signal φP.

Next, the period of FIG. 4B will be described. In the period (B) in FIG. 4, the phase difference signal φ
Since P and delay signal φPd attain L level, N-channel MOS transistors 12 and 13 maintain the off state. On the other hand, P-channel MOS transistors 10 and 11
Is turned on while the phase difference signal φR and the delay signal φRd are at the L level. Thereby, the transistor 1
While 0 is on, a current is discharged from the node α by the constant current source circuit 6 (a current waveform component Do1 in a portion (B) of FIG. 4). Further, while the transistor 11 is on, a current is discharged from the node α by the constant current source circuit 7 (a current waveform component Do2 in a portion (B) of FIG. 4).

The current waveform at the actual node α is Do, and this waveform is the sum of Do1 and Do2 described above. If the phase difference is large, the delayed phase difference signal φRd
Since the level state exists, the sum is obtained by adding the constant current source circuits 6 and 7. However, when the phase difference decreases and the width WA of the L level of the phase difference signal φR becomes W2 or less, the delay signal φRd does not have the L level, so that the constant current source circuit 6 operates during the L level period of the phase difference signal φR. Only the current is discharged. It should be noted that the waveform Do of the sink current and the discharge current at the node α
o1 is output, then Do1 + Do2, and finally Do
2 is output.

Here, the locked state of the PLL is when the phase difference between the reference signal fr and the comparison signal fp is very close, and the phase difference is said to be several hundred ps. That is, WA and WB in FIG. 4 have the same width, and the current waveform signal Do2 does not change at that time.
The current waveform signal Do at the node α, which is the result of addition of the current waveform signals Do1 and Do2, has the current waveform signals Do1 and
o2, but when locked, the current waveform signal Do1
Only the potential.

The energy level of the current waveform signal Do at the node α is, as shown in FIG.
This is the sum of the energy levels Vp based on o1 and Do2. When the phase difference is more than several hundred ps (D
(when o1 and Do2 are added), the slope is half when the phase difference is several hundred ps or less. Therefore, when the phase difference is large, the output energy of the charge pump circuit 17 is large, and the lock-up time of the PLL frequency synthesizer circuit 16 can be reduced.
When the phase difference decreases as the lock state approaches, the output energy of the charge pump circuit 17 also decreases, and the PLL
The phase noise of the frequency synthesizer circuit 16 is reduced. In the locked state, the energy level is further reduced by half, and the phase noise is further reduced.

Thus, in the first embodiment, as shown in FIG. 4, the current waveform at the node α increases and decreases stepwise, so that the occurrence of current switching noise is small. In addition, since the delay circuit is configured using the delay of the gate, it can be easily formed into a single chip with a simple configuration, and the area is hardly increased. This is particularly suitable for a high-frequency PLL frequency synthesizer circuit.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. Note that, for convenience of description, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is partially omitted.

The PLL frequency synthesizer circuit 18 shown in FIG. 6 differs from the PLL frequency synthesizer circuit 16 of FIG.
Only. That is, the charge pump circuit 19 includes the delay circuits 5A and 5B, the constant current source circuits 6, 7, 8, and 9,
It comprises P-channel MOS transistors 10 and 11 and N-channel MOS transistors 12 and 13. One end of the constant current source circuit 6 is connected to the power supply Vcc, and the other end is connected to P
Connected to the source terminal (node β) of channel MOS transistor 10. One end of the constant current source circuit 7 is a power supply Vcc.
And the other end is connected to a P-channel MOS transistor 11
Connected to the source terminal. One end of the constant current source circuit 8 is connected to the ground GND, and the other end is connected to the source terminal (node γ) of the N-channel MOS transistor 12. One end of the constant current source circuit 9 is connected to the ground GND, and the other end is connected to the source terminal of the N-channel MOS transistor 13.

The drain terminals of P-channel MOS transistor 10 and N-channel MOS transistor 12 are connected to node α.
1 is connected to the node β, and the drain terminal of the N-channel MOS transistor 13 is connected to the node γ. Further, phase difference signal φR is input to the gate terminal of P-channel MOS transistor 10, and phase difference signal φR
Is delayed by the delay circuit 5A, and is input to the gate terminal of the P-channel MOS transistor 11. The phase difference signal φP is input to the gate terminal of the N-channel MOS transistor 12, and the delay signal φPd obtained by delaying the phase difference signal φP by the delay circuit 5B is input to the gate terminal of the N-channel MOS transistor 13.

FIG. 7 shows the operation of the PLL frequency synthesizer circuit 18 configured as described above. Now, the phase of the comparison signal fp of the comparison frequency divider 3 is equal to the reference signal fr of the reference frequency divider 2.
During the period (C) faster than the phase of the phase difference signal φ
R is held at the H level, while the phase difference signal φP contains a positive pulse of the phase difference. Since the phase difference signal φR that is the input of the delay circuit 5A is at the H level, the phase difference signal φRd that is the output is held at the H level, and the transistors 10 and 11 are turned off. On the other hand, the phase difference signal φPd output from the delay circuit 5B is obtained by delaying the input phase difference signal φP by the time τB. However, when the phase difference between the reference signal fr and the comparison signal fp becomes close, and the width WB of the phase difference signal φP is equal to or less than the width W2 in FIG. 3, the delay signal φ output from the delay circuit 5B is output.
No positive pulse is output to Pd.

Similarly, during a period (D) in which the phase of the comparison signal fp of the comparison frequency divider 3 is later than the phase of the reference signal fr of the reference frequency divider 2, the phase difference signal φP is held at the L level. , And the phase difference signal φR includes a negative pulse of the phase difference. Since the phase difference signal φP, which is the input of the delay circuit 5B, is at the L level, the delay signal φPd, which is the output, is held at the L level, so that the transistors 12, 13 are turned off. On the other hand, the delay signal φRd output from the delay circuit 5A is obtained by delaying the input phase difference signal φR by the time τA. However, when the phase difference between the reference signal fr and the comparison signal fp becomes close and the width WA of the phase difference signal φR becomes equal to or less than the width W2 in FIG.
No negative pulse is output to the delay signal φRd, which is the output of the delay circuit 5A.

From the above, the period (C) in FIG.
Since the phase difference signal φR and the delay signal φRd attain the H level, the P-channel MOS transistor 1
0, 11 maintain the off state. On the other hand, N channel MO
The S transistors 12 and 13 are turned on while the phase difference signal φP and the delay signal φPd are at the H level. As a result, while the transistor 12 is on, a current is drawn at the node α by the constant current source circuit 8 (a current waveform component Do1 in (C) of FIG. 7). Further, the transistor 12 is on and the transistor 1
3 is on, current is drawn at the node α by the constant current source circuit 9 (FIG. 7C).
Current waveform component Do2B).

The actual current waveform at the node α is Do, and this waveform is the sum of Do1 and Do2B described above.
When the phase difference is large, the delayed phase difference signal φPd has an H-level state, and therefore, is added by the constant current source circuits 8 and 9 where the N-channel MOS transistors 12 and 13 are on. Shape. However, when the phase difference decreases and the width WB of the H level of the phase difference signal φP becomes W2 or less, the H level of the delay signal φPd disappears. Only draws current.

Next, the period of FIG. 7D will be described. In the period (D) in FIG. 7, the phase difference signal φ
Since P and delay signal φPd attain L level, N-channel MOS transistors 12 and 13 maintain the off state. On the other hand, P-channel MOS transistors 10 and 11
Is turned on while the phase difference signal φR and the delay signal φRd are at the L level. Thereby, the transistor 1
While 0 is on, current is discharged from the node α by the constant current source circuit 6 (current waveform component Do1 in (D) section of FIG. 7). Further, the transistor 10 is turned on,
In addition, while the transistor 11 is on, a current is discharged from the node α by the constant current source circuit 7 (a current waveform component Do2A in a portion (D) in FIG. 7).

The actual current waveform at the node α is Do, and this waveform is the sum of Do1 and Do2B described above.
If the phase difference is large, the L level state exists in the delayed phase difference signal φRd, so that the constant current source circuits 6 and 7 add up the portions where the N-channel MOS transistors 10 and 11 are on. Shape. However, when the phase difference decreases and the width WA of the L level of the phase difference signal φR becomes W2 or less, the delay signal φRd does not have the L level, so that the constant current source circuit 6 operates during the L level period of the phase difference signal φR. Only the current is discharged. Note that the node α
As for the waveform Do of the drawing current and the discharging current in the current, a current waveform Do1 is first output, and then Do1 + Do2
A (or Do2B) is in the output form.

Here, the shaded portion in the period (C) in FIG. 7 indicates the phase difference WB between the reference signal fr and the comparison signal fp.
Indicates a case close to the delay time τB of the delay circuit 5B, and at this time, a positive pulse may be generated in the phase difference signal φPd output from the delay circuit 5B due to process variation or the like. That is, if the phase difference WB between the reference signal fr and the comparison signal fp is considerably smaller than the delay time τB of the delay circuit 5B, no positive pulse is generated in the phase difference signal φPd, but the phase difference WB between the reference signal fr and the comparison signal fp is obtained.
Is close to the delay time τB of the delay circuit 5B, a positive pulse may be generated in the phase difference signal φPd. However, the N-channel MOS transistor 12,
13 are connected in series via the node γ.
When the channel MOS transistor 12 is turned off, that is, when the phase difference signal φP falls to the L level, the constant current of the constant current source circuit 9 stops flowing from the node α.

Similarly, the hatched portion in the period (D) indicates that the phase difference WB between the reference signal fr and the comparison signal fp is equal to the delay circuit 5A.
The case where the delay time is close to the delay time τA of FIG.
A negative pulse may be generated in the phase difference signal φRd, which is the output of A, due to process variations or the like. That is, the phase difference WA between the reference signal fr and the comparison signal fp.
Is considerably smaller than the delay time τA of the delay circuit 5A,
Although no negative pulse is generated in the phase difference signal φRd, when the phase difference WA between the reference signal fr and the comparison signal fp is close to the delay time τA of the delay circuit 5A, the phase difference signal φRd
May cause a negative pulse.
However, since P-channel MOS transistors 10 and 11 are connected in series via node β, they are fixed when P-channel MOS transistor 10 is turned off, that is, when phase difference signal φR rises to H level. The constant current of the current source circuit 7 stops flowing to the node α.

As described above, in the second embodiment, P
The channel MOS transistors 10 and 11 and the N channel MOS transistors 12 and 13 are connected in series. As a result, the delay signal φPd in the shaded area in FIG.
And the influence of the pulse of φRd can be eliminated. That is,
Stable and reliable PLL with no variation between elements
A frequency synthesizer circuit can be realized.

The energy level of the current waveform signal Do at the node α is, as shown in FIG.
It is the sum of the energy levels Vp of o1, Do2A, and Do2B. The slope when the phase difference is several hundred ps or less is about half the slope when the phase difference is several hundred ps or more apart. Therefore, when the phase difference is large, the output energy of the charge pump circuit 19 is large, and the lock-up time of the PLL frequency synthesizer circuit 18 can be reduced. When the phase difference decreases as the lock state approaches, the output energy of the charge pump circuit 19 also decreases, and the phase noise of the PLL frequency synthesizer circuit 18 is reduced. In the locked state, the energy level is further reduced by half, and the phase noise is further reduced. Here, as shown in FIG. 8, the maximum energy level is ± 2 Vp
The reason why ± 2Vp-Δ |
This is because, as described above, current flows to node α only when P-channel MOS transistor 10 or N-channel MOS transistor 12 is on.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above-described embodiment, the constant current values of the respective constant current source circuits are the same, but the present invention can also be realized with constant current source circuits having different current values. Also,
In the above embodiment, for example, two sets of switch circuits and constant current source circuits such as P-channel MOS transistors 10 and 11 and constant current source circuits 6 and 7 are used as switch circuits. And a constant current source circuit, and at that time, it is also possible to form two or more delay circuits.

In the above embodiment, a MOS transistor is used as a switch circuit. However, the present invention can be realized with a switching element such as a bipolar transistor. In the above embodiment, the delay circuit has four inverters. However, the number of stages may be set in consideration of process conditions because the delay time varies depending on the process.

[0066]

As described above, according to the charge pump circuit of the present invention, the input pulse is delayed by the simple delay circuit, the input pulse is connected to the first switching element, and the delay signal is converted to the second switching element. , And each is turned on / off, so that the larger the input pulse width is,
The time during which the switching element and the second switching element are on in common is increased, and the output energy of the charge pump circuit can be increased. Further, if the input pulse width is small, the time during which the first switching element and the second switching element are on in common is reduced, and the output energy of the charge pump circuit can be reduced.

Therefore, in the PLL frequency synthesizer circuit using this charge pump circuit, when the phase difference signal is input to the charge pump circuit as an input pulse, when the phase difference is large, the output energy of the charge pump circuit is large and the phase difference is small. When it is small, the output energy of the charge pump circuit can be reduced to such an extent that the phase noise does not deteriorate, and the phase noise can be suppressed without increasing the lock-up time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing Embodiment 1 of a PLL frequency synthesizer circuit according to the present invention.

FIG. 2 is a circuit diagram of a delay circuit.

FIG. 3 is a time chart illustrating an operation of the delay circuit.

FIG. 4 is a time chart illustrating an operation of the PLL frequency synthesizer circuit of the first embodiment.

FIG. 5 is a characteristic diagram showing a relationship between a phase difference and energy output from the charge pump circuit of the first embodiment.

FIG. 6 is a block diagram showing Embodiment 2 of a PLL frequency synthesizer circuit according to the present invention.

FIG. 7 is a time chart illustrating an operation of the PLL frequency synthesizer circuit according to the second embodiment.

FIG. 8 is a characteristic diagram illustrating a relationship between a phase difference and energy output from the charge pump circuit according to the first embodiment.

FIG. 9 is a block diagram showing a PLL frequency synthesizer circuit in Conventional Example 1.

FIG. 10 is a time chart showing an operation of a PLL frequency synthesizer circuit in Conventional Example 1.

FIG. 11 is a characteristic diagram showing a relationship between a phase difference and energy output from the charge pump circuit of Conventional Example 1.

FIG. 12 is a block diagram showing a PLL frequency synthesizer circuit in Conventional Example 2.

FIG. 13 is a circuit diagram showing a pulse width conversion circuit in Conventional Example 2.

FIG. 14 is a time chart illustrating an operation of the pulse width conversion circuit in Conventional Example 2.

FIG. 15 illustrates a case where the feedback signal is delayed from the reference signal.
6 is a time chart illustrating an operation of the LL frequency synthesizer circuit.

FIG. 16 illustrates a case where a feedback signal is ahead of a reference signal.
6 is a time chart illustrating an operation of the LL frequency synthesizer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Crystal oscillator 2 Reference frequency divider 3 Comparative frequency divider 4 Phase comparator 5A, 5B Delay circuit 6,7,8,9 Constant current source circuit 10,11 P channel MOS transistor 12,13 N channel MOS transistor 14 LPF ( Low-pass filter) 15 VCO (voltage controlled oscillator) 16 PLL frequency synthesizer circuit 17 charge pump circuit

Claims (6)

[Claims] 1. A charge pump circuit for outputting a voltage signal based on an input pulse, a delay circuit for outputting a delay signal obtained by delaying the input pulse by a predetermined time, and a first switching for turning on / off by the input pulse. A second switching element that is turned on / off by the delay signal; and a constant current power supply that is connected to one end of the switching element, respectively, and an output from the other end of the first switching element that is turned on by the input pulse. The output of the second switching element is added to the charge pump circuit. 2. The charge pump circuit according to claim 1, wherein the other end of said second switching element is connected to the other end of said first switching element. 3. The charge pump circuit according to claim 1, wherein one end of said first switching element is connected to the other end of said second switching element. 4. A PLL frequency synthesizer circuit for outputting a signal of a desired frequency based on an oscillation signal of a predetermined frequency and a feedback signal from a voltage controlled oscillator arranged in an output stage, wherein said oscillation signal is frequency-divided to a reference frequency. A reference frequency divider for outputting a reference signal, a comparison frequency divider for dividing the feedback signal based on a set frequency and outputting a comparison signal, and performing a phase comparison between the reference signal and the comparison signal. A phase comparator that outputs a phase difference signal; and a charge pump circuit that receives the phase difference signal and outputs a voltage signal based on the phase difference signal. A delay circuit that outputs a delay signal delayed by the time, a first switching element that is turned on / off by the phase difference signal, and a second switch that is turned on / off by the delay signal. A switching element, and a constant current power supply connected to one end of the switching element. An output of the second switching element is added to an output from the other end of the first switching element that is turned on by the phase difference signal. A PLL frequency synthesizer circuit characterized in that: 5. The PLL frequency synthesizer circuit according to claim 4, wherein the other end of said second switching element is connected to the other end of said first switching element. 6. The PLL frequency synthesizer circuit according to claim 4, wherein one end of said first switching element is connected to the other end of said second switching element.