JP2000164545A - Polishing method of platinum metal film and cell forming method of semiconductor storage device - Google Patents
Polishing method of platinum metal film and cell forming method of semiconductor storage deviceInfo
- Publication number
- JP2000164545A JP2000164545A JP10332548A JP33254898A JP2000164545A JP 2000164545 A JP2000164545 A JP 2000164545A JP 10332548 A JP10332548 A JP 10332548A JP 33254898 A JP33254898 A JP 33254898A JP 2000164545 A JP2000164545 A JP 2000164545A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polishing
- metal film
- platinum group
- group metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 title claims abstract description 102
- 238000005498 polishing Methods 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000003860 storage Methods 0.000 title description 4
- 150000001875 compounds Chemical class 0.000 claims abstract description 26
- 239000002002 slurry Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000000126 substance Substances 0.000 claims abstract description 14
- 239000002904 solvent Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 101
- 239000002184 metal Substances 0.000 claims description 101
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 229910001507 metal halide Inorganic materials 0.000 claims description 5
- 150000005309 metal halides Chemical class 0.000 claims description 5
- 229910052976 metal sulfide Inorganic materials 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 16
- 230000009257 reactivity Effects 0.000 abstract description 11
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 167
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 230000015654 memory Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005660 chlorination reaction Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- -1 platinum group metals Chemical class 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000005987 sulfurization reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、白金族系金属膜
を化学機械的研磨法(以下CMP法と略記する)にて研
磨する研磨方法と、白金族系金属膜により構成される電
極を有する半導体記憶装置のセル形成方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing method for polishing a platinum group metal film by a chemical mechanical polishing method (hereinafter abbreviated as CMP method), and an electrode comprising the platinum group metal film. The present invention relates to a method for forming a cell of a semiconductor memory device.
【0002】[0002]
【従来の技術】近年、集積回路素子の高集積化が進み、
メモリセルにおいては特に記憶容量の増大などに対応す
べく高集積化の進行が著しい。そこで、メモリセルの一
部を構成する容量絶縁膜を構成する材料として、従来の
酸化けい素(SiO2 )に代えて、高誘電率で分極特性
を有するPZT(Pd(Zr,Ti)O3 )系強誘電体
薄膜や、BST((Ba,Sr)TiO3 )系高誘電体
薄膜を用い、これをDRAMキャパシタや不揮発メモリ
に応用する研究が活発になっている。この不揮発性メモ
リにおいて、データの書き換えを繰り返すと膜の電荷保
持特性等が劣化するという難点がある。これは、膜の疲
労と呼ばれるものであるが、この膜の劣化を防ぐために
膜を構成する材料である高誘電体や強誘電体自体の改良
が行われている。2. Description of the Related Art In recent years, high integration of integrated circuit elements has been progressing.
In memory cells, in particular, the progress of high integration has been remarkable in order to cope with an increase in storage capacity. Therefore, instead of the conventional silicon oxide (SiO 2 ), PZT (Pd (Zr, Ti) O 3 , which has a high dielectric constant and polarization characteristics, is used as a material for forming a capacitive insulating film forming a part of a memory cell. ) -Based ferroelectric thin films and BST ((Ba, Sr) TiO 3 ) -based high-dielectric thin films, and studies on applying them to DRAM capacitors and nonvolatile memories are being actively conducted. In this nonvolatile memory, there is a disadvantage that the charge retention characteristics and the like of the film are deteriorated when rewriting data is repeated. This is called fatigue of the film. In order to prevent the deterioration of the film, improvements have been made to the high dielectric material and the ferroelectric material which constitute the film.
【0003】一方、この膜の両面に接触する電極材料の
改良も積極的に行われている。強誘電体や高誘電体は金
属の酸化物であるため、その両面に接触している電極材
料の金属をも酸化してしまう傾向がある。そのために、
耐酸化性の大きい白金族系金属膜が電極として用いられ
ている。現在、電極として使用されている白金族系金属
は、白金(Pt),ルテニウム(Ru)が使用されてお
り、その他、イリジウム(Ir)などの使用も検討され
つつある。On the other hand, the improvement of the electrode material which is in contact with both surfaces of the film has been actively carried out. Since ferroelectrics and high dielectrics are metal oxides, they also tend to oxidize the metal of the electrode material in contact with both surfaces. for that reason,
A platinum group metal film having high oxidation resistance is used as an electrode. At present, platinum (Pt) and ruthenium (Ru) are used as platinum group metals used as electrodes, and the use of iridium (Ir) and the like is being studied.
【0004】ここで、これまでに使用されてきたセルの
形はスタック型で、塩素系ガスを用いたドライエッチン
グにより下部電極用の白金族系金属をパターニングして
きた。図4(a)〜(d)は、従来のプロセスを示す断
面図である。下地のシリコン酸化膜41に形成された埋
め込み溝内に配線としてポリシリコンを埋め込んで配線
43を形成した後、その上に下部電極となる白金系金属
膜42をスパッタあるいはCVD法などによって堆積す
る。その後、白金系金属膜42をドライエッチングによ
りパターニングし、下部電極44を形成する。そして、
基板上に、例えばBSTにより構成される高誘電体膜4
5を堆積した後、さらにその上に上部電極膜46を堆積
してセルを形成する。[0004] Here, the cell used so far is a stack type, and a platinum group metal for a lower electrode has been patterned by dry etching using a chlorine-based gas. 4A to 4D are cross-sectional views showing a conventional process. After forming a wiring 43 by burying polysilicon as a wiring in a buried groove formed in the underlying silicon oxide film 41, a platinum-based metal film 42 serving as a lower electrode is deposited thereon by sputtering or CVD. Thereafter, the platinum-based metal film 42 is patterned by dry etching to form a lower electrode 44. And
A high dielectric film 4 composed of, for example, BST on a substrate
After depositing 5, an upper electrode film 46 is further deposited thereon to form a cell.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の方法では、以下のような問題があった。However, the above-mentioned conventional method has the following problems.
【0006】最近では、1ギガビットのDRAM用のセ
ルは極めて微細となり、これまでのスタック型セル構造
では、ドライエッチングによる下地電極用の白金族系金
属膜42から下部電極44の形状にパターニングするの
が困難である。そのため、トレンチ型セル構造にする方
向で検討が進められている。このトレンチ型セル構造で
は、層間絶縁膜である酸化膜(例えばシリコン酸化膜)
に埋め込み溝等の開口部を形成するため、これまでのド
ライエッチングプロセスが応用できる。さらに、下部電
極用の白金族系金属膜をドライエッチングする必要がな
いので、これまでのスタック型セル構造より微細なパタ
ーン形成には有利である。In recent years, cells for 1 gigabit DRAMs have become extremely fine. In the conventional stacked cell structure, a pattern is formed from a platinum group metal film 42 for a base electrode to a lower electrode 44 by dry etching. Is difficult. For this reason, studies are being made toward a trench cell structure. In this trench type cell structure, an oxide film (for example, a silicon oxide film) which is an interlayer insulating film
In order to form an opening such as a buried groove, a conventional dry etching process can be applied. Further, since it is not necessary to dry-etch the platinum group metal film for the lower electrode, it is advantageous for forming a finer pattern than the conventional stacked cell structure.
【0007】しかし、トレンチ型セルを形成するプロセ
スにおいては、層間絶縁膜に形成された開口部内および
層間絶縁膜上に白金族系金属膜を堆積した後、CMP法
による平坦化を行って開口部内に白金族系金属膜を埋め
込む工程が必要となるが、その際、白金族系金属は化学
反応性に乏しく、CMP法による平坦化が困難であると
いう問題があった。However, in the process of forming the trench type cell, a platinum group metal film is deposited in the opening formed in the interlayer insulating film and on the interlayer insulating film, and then flattened by the CMP method to form the inside of the opening. Requires a step of embedding a platinum group metal film into the substrate, but at this time, there is a problem that the platinum group metal has poor chemical reactivity and is difficult to be planarized by the CMP method.
【0008】この発明の目的は、微細なパターン形成が
可能で、しかも従来からある研磨用スラリーを用いてC
MP法による平坦化を短時間で容易に行うことができる
白金族系金属膜の研磨方法と半導体記憶装置のセル形成
方法を提供するものである。[0008] An object of the present invention is to form a fine pattern and use a conventional polishing slurry to form C
An object of the present invention is to provide a method of polishing a platinum group metal film and a method of forming a cell of a semiconductor memory device, which can easily perform planarization by the MP method in a short time.
【0009】[0009]
【課題を解決するための手段】請求項1記載の白金族系
金属膜の研磨方法は、被加工物に設けた白金族系金属膜
の研磨箇所を反応性の高い化合物に変換し、化学機械的
研磨法により研磨することを特徴とするものである。According to a first aspect of the present invention, there is provided a method for polishing a platinum group metal film, comprising: converting a polished portion of a platinum group metal film provided on a workpiece into a highly reactive compound; Characterized by being polished by a mechanical polishing method.
【0010】なお、反応性の高い化合物としては、ハロ
ゲン化してなるハロゲン化金属、硫化してなる硫化金
属、酸化してなる酸化金属等が挙げられる。[0010] Examples of highly reactive compounds include halogenated metal halides, sulfurized metal sulfides, and oxidized metal oxides.
【0011】請求項1〜4記載の白金族系金属膜の研磨
方法によると、被加工物に設けた白金族系金属膜の研磨
箇所を、反応性の高い化合物(ハロゲン化金属、硫化金
属、酸化金属)に変換することで、研磨し易くなり、市
販されている研磨用スラリーを用いてCMP法による平
坦化を短時間で容易に行うことができる。According to the method for polishing a platinum group metal film according to any one of the first to fourth aspects of the present invention, the polishing portion of the platinum group metal film provided on the workpiece is made of a highly reactive compound (metal halide, metal sulfide, The conversion to (metal oxide) facilitates polishing, and planarization by the CMP method can be easily performed in a short time using a commercially available polishing slurry.
【0012】請求項5記載の白金族系金属膜の研磨方法
は、研磨用スラリーを研磨パッドと白金族系金属膜の研
磨箇所との間に供給し、研磨パッドと被加工物との間に
圧力を印加しながら、研磨パッドと被加工物とを相対的
に回転させて、白金族系金属膜の研磨箇所を研磨するこ
とを特徴とするものである。According to a fifth aspect of the present invention, in the method of polishing a platinum group metal film, a polishing slurry is supplied between the polishing pad and a portion to be polished of the platinum group metal film, and the polishing slurry is supplied between the polishing pad and the workpiece. The method is characterized in that a polishing pad and a workpiece are relatively rotated while applying pressure to polish a portion to be polished of a platinum group metal film.
【0013】請求項5記載の白金族系金属膜の研磨方法
によると、化学反応性が乏しい白金族系金属膜を、より
反応性の高い化合物に変換させたことで、市販の研磨用
スラリーを用いて、白金族系金属膜を容易かつ迅速に除
去できる。According to the method for polishing a platinum group metal film according to the fifth aspect, a commercially available polishing slurry can be obtained by converting a platinum group metal film having poor chemical reactivity into a compound having higher reactivity. By using it, the platinum group metal film can be easily and quickly removed.
【0014】請求項6記載の白金族系金属膜の研磨方法
は、請求項5において、白金族系金属膜の研磨が、白金
族系金属膜の研磨箇所を全て研磨し、研磨レートの異な
る金属が露出した時点で終了することを特徴とするもの
である。According to a sixth aspect of the present invention, in the method for polishing a platinum group metal film, the polishing of the platinum group metal film may be performed by polishing all the polished portions of the platinum group metal film, and the polishing rate may be different. Is terminated when the image is exposed.
【0015】請求項6記載の白金族系金属膜の研磨方法
によると、反応性の高い化合物に変換された白金族系金
属膜が全て研磨された時点で、研磨レートが遅い白金族
系金属が露出することになり、CMPは自然に終了す
る。According to the method for polishing a platinum group metal film according to claim 6, when the platinum group metal film converted into a highly reactive compound is completely polished, the platinum group metal having a low polishing rate is removed. Exposure will cause CMP to end spontaneously.
【0016】請求項7記載の白金族系金属膜の研磨方法
は、請求項5または請求項6において、研磨用スラリー
には、反応性の高い化合物に変換された白金族系金属膜
が可溶な溶媒を用いることを特徴とするものである。According to a seventh aspect of the present invention, in the polishing method for a platinum group metal film according to the fifth or sixth aspect, the platinum group metal film converted into a highly reactive compound is soluble in the polishing slurry. It is characterized by using a suitable solvent.
【0017】請求項7記載の白金族系金属膜の研磨方法
によると、白金族系金属膜をより反応性の高い化合物に
変換することで、特殊な研磨用スラリーを用いなくて
も、変換後の化合物が可溶な溶媒が用いられているよう
な現在市販されている研磨スラリーを用いることで、白
金族系金属膜を容易かつ迅速に除去できる。According to the method for polishing a platinum group metal film according to the present invention, the platinum group metal film is converted into a compound having a higher reactivity, so that after the conversion without using a special polishing slurry. By using a commercially available polishing slurry in which a solvent in which the compound is soluble is used, the platinum group metal film can be easily and quickly removed.
【0018】請求項8記載の半導体記憶装置のセル形成
方法は、導体部を有する基板上に層間絶縁膜を堆積し、
層間絶縁膜に導体部の少なくとも一部に到達する開口部
を形成し、開口部内および層間絶縁膜の上に白金族系金
属膜を堆積し、開口部内部以外の白金族系金属膜を反応
性の高い化合物に変換し、化学機械的研磨にて層間絶縁
膜が露出するまで反応性の高い化合物に変換した白金族
系金属膜を除去すると共に、開口部に白金族系金属膜を
残存させて下部電極を形成し、下部電極の上に誘電体膜
を堆積し、誘電体膜の上に上部電極膜を堆積するもので
ある。According to a eighth aspect of the present invention, in the method of forming a cell of a semiconductor memory device, an interlayer insulating film is deposited on a substrate having a conductor portion,
An opening reaching at least a part of the conductor is formed in the interlayer insulating film, a platinum group metal film is deposited in the opening and on the interlayer insulating film, and the platinum group metal film other than the inside of the opening is reactive. And remove the platinum group metal film converted to a highly reactive compound until the interlayer insulating film is exposed by chemical mechanical polishing, and leave the platinum group metal film in the opening. A lower electrode is formed, a dielectric film is deposited on the lower electrode, and an upper electrode film is deposited on the dielectric film.
【0019】請求項8記載の半導体記憶装置のセル形成
方法によると、白金族系金属膜を下部電極とするトレン
チ型セルが形成され、白金族系金属膜の微細パターンの
形成が可能であるので、高集積化に適した半導体記憶装
置のセルを形成できる。According to the method of forming a cell of a semiconductor memory device of the present invention, a trench type cell having a platinum group metal film as a lower electrode is formed, and a fine pattern of the platinum group metal film can be formed. Thus, a cell of a semiconductor memory device suitable for high integration can be formed.
【0020】請求項9記載の半導体記憶装置のセル形成
方法は、請求項8において、研磨用スラリーには、反応
性の高い化合物に変換された白金族系金属膜が可溶な溶
媒を用いることを特徴とするものである。According to a ninth aspect of the present invention, in the method of forming a cell for a semiconductor memory device according to the eighth aspect, a solvent in which a platinum group metal film converted into a highly reactive compound is soluble is used as the polishing slurry. It is characterized by the following.
【0021】請求項9記載の半導体記憶装置のセル形成
方法によると、白金族系金属膜をより反応性の高い化合
物に変換することで、特殊な研磨用スラリーを用いなく
ても、変換後の化合物が可溶な溶媒が用いられているよ
うな現在市販されている研磨スラリーを用いることで、
白金族系金属膜を容易かつ迅速に除去できる。According to the method for forming a cell of a semiconductor memory device according to the ninth aspect, the platinum group metal film is converted into a compound having a higher reactivity, so that the converted metal can be used without using a special polishing slurry. By using currently commercially available polishing slurries in which a solvent in which the compound is soluble is used,
The platinum group metal film can be easily and quickly removed.
【0022】[0022]
【発明の実施の形態】この発明の白金族系金属膜の研磨
方法と半導体記憶装置のセル形成方法を図1ないし図3
を参照しながら説明する。1 to 3 show a method of polishing a platinum group metal film and a method of forming a cell of a semiconductor memory device according to the present invention.
This will be described with reference to FIG.
【0023】図1(a)〜(d),図2(a)〜(c)
は、白金族系金属膜で構成される下部電極を有するトレ
ンチ型セルの形成工程を示す断面図である。FIGS. 1 (a) to 1 (d) and FIGS. 2 (a) to 2 (c)
FIG. 4 is a cross-sectional view showing a step of forming a trench cell having a lower electrode composed of a platinum group metal film.
【0024】まず、図1(a)に示す工程で、シリコン
基板(図示せず)上に熱酸化によりシリコン酸化膜から
なる第1層間絶縁膜11を700nmの厚さに形成した
後、所望の位置に径が約0.16μmのコンタクトホー
ルを形成する。そして、CVD法により、コンタクトホ
ール内および第1層間絶縁膜11の上に厚みが約1μm
のポリシリコン膜を堆積し、リン拡散を行って低抵抗化
する。その後、CMP法を用いて、第1層間絶縁膜11
の表面が露出するまで余分な部分のポリシリコンを除去
し、基板の上面全体を平坦化する。その結果、コンタク
トホール内にのみポリシリコンが埋め込まれてポリシリ
コン配線13が形成される。First, in the step shown in FIG. 1A, a first interlayer insulating film 11 made of a silicon oxide film is formed on a silicon substrate (not shown) to a thickness of 700 nm by thermal oxidation. A contact hole having a diameter of about 0.16 μm is formed at the position. Then, a thickness of about 1 μm is formed in the contact hole and on the first interlayer insulating film 11 by the CVD method.
Is deposited, and phosphorus is diffused to lower the resistance. After that, the first interlayer insulating film 11 is formed by using the CMP method.
Unnecessary portions of the polysilicon are removed until the surface of the substrate is exposed, and the entire upper surface of the substrate is planarized. As a result, the polysilicon is buried only in the contact hole, and the polysilicon wiring 13 is formed.
【0025】次に、基板上に、厚みが約1μmのシリコ
ン酸化膜からなる第2層間絶縁膜12を堆積し図1
(b)に示す工程で、、第2層間絶縁膜12に、例えば
円柱状のパターンを有する開口部14(径が約0.28
μm)を従来の酸化膜用のドライエッチング技術を使用
して形成する。そのとき、開口部14の底面のいずれか
の部位にポリシリコン配線13が露出しているように開
口部14を形成する。Next, a second interlayer insulating film 12 made of a silicon oxide film having a thickness of about 1 μm is deposited on the substrate, and FIG.
In the step shown in FIG. 2B, an opening 14 (for example, having a diameter of about 0.28) having a columnar pattern is formed in the second interlayer insulating film 12.
μm) is formed using a conventional dry etching technique for an oxide film. At this time, the opening 14 is formed such that the polysilicon wiring 13 is exposed at any part of the bottom surface of the opening 14.
【0026】次に、図1(c)に示す工程で、開口部1
4内および第2層間絶縁膜12上に密着層兼バリアメタ
ル層としてTiN/Ti膜15を堆積する。このとき、
TiN膜の厚みは約20nmであり、Ti膜の厚みは約
10nmである。さらに、これに連続してTiN/Ti
膜15の上に、白金族系金属膜であるRu膜16をスパ
ッタ法あるいはCVD法により30nmの厚みで堆積す
る。Next, in the step shown in FIG.
A TiN / Ti film 15 is deposited as an adhesion layer and a barrier metal layer in the inside 4 and on the second interlayer insulating film 12. At this time,
The thickness of the TiN film is about 20 nm, and the thickness of the Ti film is about 10 nm. Further, in succession, TiN / Ti
On the film 15, a Ru film 16, which is a platinum group metal film, is deposited to a thickness of 30 nm by sputtering or CVD.
【0027】次に、図1(d)に示す工程で、開口部1
4内以外の研磨する部分のRu膜16の表面を、塩素ガ
スにより塩素化し、RuClx(ハロゲン化白金族系金
属膜)17に変換する。Next, in the step shown in FIG.
The surface of the Ru film 16 other than the portion to be polished is chlorinated by chlorine gas to be converted into RuClx (a halogenated platinum group metal film) 17.
【0028】さらに、図2(a)に示す工程で、開口部
14内以外のTiN/Ti膜15やRuClx17を除
去するため、CMP法による平坦化を行う。Further, in the step shown in FIG. 2A, planarization is performed by a CMP method in order to remove the TiN / Ti film 15 and the RuClx 17 other than in the opening 14.
【0029】図3は、この工程で使用されるCMPに使
用される研磨機の構造の例を示す斜視図である。CMP
研磨機は、中心軸の回りに回転する円盤状のプラテン3
1(定盤)と、該プラテン31を中心部で支持するプラ
テン軸32と、プラテン31上に貼り付けられた独立気
泡型ウレタン樹脂や不織布等からなる研磨パッド33
と、ウェハ36が装着された円板状のキャリア34と、
該キャリア34を中心部で支持するキャリア軸35と、
スラリー状の研磨液38を供給するための研磨液供給装
置37とを備えている。ここで、プラテン軸32および
キャリア軸35は、いずれもサーボモータ等により強制
的に回転され、かつその回転速度が互いに独立に可変に
制御されるものである。FIG. 3 is a perspective view showing an example of the structure of a polishing machine used for the CMP used in this step. CMP
The polishing machine is a disk-shaped platen 3 that rotates around a central axis.
1 (platen), a platen shaft 32 supporting the platen 31 at the center, and a polishing pad 33 made of a closed-cell urethane resin or a non-woven fabric adhered on the platen 31
A disc-shaped carrier 34 on which a wafer 36 is mounted;
A carrier shaft 35 that supports the carrier 34 at a central portion;
A polishing liquid supply device 37 for supplying a slurry-like polishing liquid 38; Here, both the platen shaft 32 and the carrier shaft 35 are forcibly rotated by a servomotor or the like, and their rotation speeds are variably controlled independently of each other.
【0030】このCMP法による研磨の結果、図2
(a)に示すように、第2層間絶縁膜12上のRuCl
x膜17およびTiN/Ti膜15が除去されて、開口
部14内のみにRu膜16およびTiN/Ti膜15が
残存し、下部電極18が形成される。As a result of the polishing by the CMP method, FIG.
As shown in FIG. 3A, RuCl on the second interlayer insulating film 12 is formed.
The x film 17 and the TiN / Ti film 15 are removed, the Ru film 16 and the TiN / Ti film 15 remain only in the opening 14, and the lower electrode 18 is formed.
【0031】次に、図2(b)に示す工程で、下部電極
18の上に、高誘電率の誘電体薄膜として厚みが約20
nmの(Ba0.5 ,Sr0.5 )TiO3 膜19をMOC
VD法により堆積した。Next, in the step shown in FIG. 2B, a high dielectric constant dielectric thin film having a thickness of about 20
nm of (Ba0.5, Sr0.5) a TiO 3 film 19 MOC
It was deposited by the VD method.
【0032】次に、図2(c)に示す工程で、(Ba0.
5 ,Sr0.5 )TiO3 膜19の上に、上部電極膜であ
るRu膜20を、開口部14内がすべて埋められるよう
にスパッタあるいはCVD法により堆積した。Next, in the step shown in FIG.
5, on the Sr0.5) TiO 3 film 19, the Ru film 20 as an upper electrode film, the opening 14 is deposited by sputtering or CVD to be buried all.
【0033】上記第1層間絶縁膜11に埋め込まれたポ
リシリコン配線13をシリコン基板のソース領域に接続
される容量蓄積部コンタクトとし、開口部14内に埋め
込まれた下部電極18を容量蓄積電極とし、(Ba0.5
,Sr0.5 )TiO3 膜19を容量絶縁膜とし、Ru
膜20をプレート電極とすることで、DRAMのセルと
なるキャパシタが形成される。なお、本実施形態の製造
工程で形成されるセルは、DRAMのメモリセルに限定
されるものではなく、不揮発性メモリのセルにも応用が
可能である。The polysilicon wiring 13 buried in the first interlayer insulating film 11 is used as a capacity storage contact connected to the source region of the silicon substrate, and the lower electrode 18 buried in the opening 14 is used as a capacity storage electrode. , (Ba0.5
, Sr0.5) TiO 3 film 19 as a capacitance insulating film, and Ru
By using the film 20 as a plate electrode, a capacitor serving as a DRAM cell is formed. The cells formed in the manufacturing process of the present embodiment are not limited to DRAM memory cells, but can be applied to nonvolatile memory cells.
【0034】以上の工程によって形成される半導体記憶
装置のセルは、容量絶縁膜として酸化性の強い高誘電体
膜((Ba0.5 ,Sr0.5 )TiO3 膜)19を用いな
がら、下部電極18および上部電極20を耐酸化性の大
きい白金族系金属(Ru)で構成しているので、容量絶
縁膜の疲労劣化に起因する書き換え特性等の悪化を防止
することができる。[0034] The cell of the semiconductor memory device formed by the above steps, oxidizing a strong high dielectric film as a capacitor insulating film ((Ba0.5, Sr0.5) TiO 3 film) while using the 19, the lower electrode Since the 18 and the upper electrode 20 are made of a platinum group metal (Ru) having high oxidation resistance, it is possible to prevent deterioration of the rewriting characteristics and the like due to fatigue deterioration of the capacitor insulating film.
【0035】特に、本実施の形態の形成方法によると、
CMP法を用いて、白金族系金属(Ru)からなる下部
電極18を開口部14内に埋め込んで、さらにその上に
酸化性の強い高誘電体膜(Ba0.5 ,Sr0.5 )TiO
3 膜19と、上部電極を構成する白金系金属膜であるR
u膜20を堆積しているので、ドライエッチングによる
微細パターンの形成が困難な白金系金属を下部電極膜と
して用いながら、微細化に適したトレンチ型セルを形成
することができる。In particular, according to the forming method of this embodiment,
A lower electrode 18 made of a platinum group metal (Ru) is buried in the opening 14 by a CMP method, and a highly oxidizable high dielectric film (Ba0.5, Sr0.5) TiO is further formed thereon.
3 film 19 and R which is a platinum-based metal film constituting the upper electrode.
Since the u film 20 is deposited, a trench cell suitable for miniaturization can be formed while using a platinum-based metal, which is difficult to form a fine pattern by dry etching, as the lower electrode film.
【0036】その場合、CMP法を用いて、化学反応性
に乏しい白金族系金属膜であるRu膜16を研磨するた
めに、塩素ガス雰囲気中で高温に加熱することでRuC
lx17に変換するので、Ru膜16の表面付近の領域
が塩素化される。そして、この塩素化された領域は研磨
用スラリーによってCMP法で容易に除去される。この
時、塩素化は開口部14以外に堆積している膜厚分と
し、開口部14内部のRu膜16は化学変化を受けない
ようにしておく。RuClx17は塩酸に可溶であるた
め、市販されている塩酸を含む研磨用スラリーによっ
て、量産工程に適合した短時間(例えば1分間)でトレ
ンチ型セルを形成することができる。In this case, in order to polish the Ru film 16, which is a platinum group metal film having poor chemical reactivity, using a CMP method, the RuC is heated to a high temperature in a chlorine gas atmosphere.
Since it is converted to 1 × 17, the region near the surface of the Ru film 16 is chlorinated. The chlorinated region is easily removed by the CMP method using the polishing slurry. At this time, the chlorination is performed by a thickness corresponding to the thickness of the film deposited on the portion other than the opening 14 so that the Ru film 16 in the opening 14 is not subjected to a chemical change. Since RuClx17 is soluble in hydrochloric acid, a trench cell can be formed using a commercially available polishing slurry containing hydrochloric acid in a short time (for example, one minute) suitable for a mass production process.
【0037】なお、本実施の形態では、白金族系金属膜
の研磨箇所をハロゲン化してハロゲン化金属としたが、
これに限るものではなく、例えば硫化して硫化金属とし
たり、酸化して酸化金属としてもよい。In this embodiment, the polished portion of the platinum group metal film is halogenated to form a metal halide.
The present invention is not limited to this, and for example, it may be sulfided to metal sulfide or oxidized to metal oxide.
【0038】また、シリコン基板上に配線としてポリシ
リコン配線3を形成しているが、TiN配線やW配線な
どの他の導体材料により構成される配線を形成してもよ
い。Although the polysilicon wiring 3 is formed as a wiring on the silicon substrate, a wiring made of another conductive material such as a TiN wiring or a W wiring may be formed.
【0039】また、セルの容量絶縁膜を高誘電体膜であ
るBST膜により構成したが、これに限定されるもので
はない。Further, the capacitor insulating film of the cell is constituted by a BST film which is a high dielectric film, but is not limited to this.
【0040】さらに、第2層間絶縁膜12に形成した開
口部14を円柱状としたが、これに限定されるものでは
なく、各種パターンの開口部を設けて、各種パターンの
下部電極を形成することができる。Further, although the opening 14 formed in the second interlayer insulating film 12 is formed in a columnar shape, the present invention is not limited to this, and openings of various patterns are provided to form lower electrodes of various patterns. be able to.
【0041】次に、前記図1(c)(d),図2(a)
に示す工程における表面処理方法と研磨方法の具体的な
実施例について説明する。Next, FIG. 1 (c) (d), FIG. 2 (a)
Specific examples of the surface treatment method and the polishing method in the steps shown in (1) will be described.
【0042】実施例1 Cl2 雰囲気中で500℃以上に30分加熱すること
で、開口部内部以外のRu膜16を塩化し、RuClx
17とする。この時、開口部内部のRu表面はSiO2
などの保護膜を選択的に堆積し保護することで、塩化反
応が起こらないようにしておくのが望ましい。Example 1 By heating in a Cl 2 atmosphere to 500 ° C. or more for 30 minutes, the Ru film 16 other than the inside of the opening was salified, and RuClx
17 is assumed. At this time, the Ru surface inside the opening is SiO 2
It is desirable to selectively deposit and protect such a protective film as to prevent a chloride reaction from occurring.
【0043】例えば、Ru膜16上にCVD−SiO2
膜を開口部内部が埋まる膜厚以上で形成した後、CVD
−SiO2 膜をエッチバックして開口部内部に保護膜と
なるCVD−SiO2 膜を形成する。このCVD−Si
O2 膜を保護膜として、Ru膜16を塩化した後、CV
D−SiO2 膜を選択的に除去する。For example, CVD-SiO 2 is formed on the Ru film 16.
After forming a film with a thickness not less than the thickness that fills the inside of the opening,
-SiO 2 film is etched back to form a CVD-SiO 2 film serving as a protective film inside the opening. This CVD-Si
After salifying the Ru film 16 using the O 2 film as a protective film, the CV
The D-SiO 2 film is selectively removed.
【0044】その後、RuClx17およびTiN/T
i膜15のCMPを、RuClxが可溶な塩酸溶媒を用
いた市販されているスラリーで1分間行うことにより、
第2層間絶縁膜12上のRuClx膜17およびTiN
/Ti膜15が除去されて、ホール内のみにRu膜16
およびTiN/Ti膜15が残存し、下部電極18が形
成される。Thereafter, RuClx17 and TiN / T
By performing CMP of the i-film 15 with a commercially available slurry using a hydrochloric acid solvent in which RuClx is soluble, for 1 minute,
RuClx film 17 on second interlayer insulating film 12 and TiN
/ Ti film 15 is removed, and Ru film 16 is formed only in the holes.
The TiN / Ti film 15 remains, and the lower electrode 18 is formed.
【0045】下部電極が形成された後、開口部内部のR
u表面の保護のために堆積した保護膜は除去する。After the lower electrode is formed, R
The protective film deposited for protection of the u surface is removed.
【0046】実施例2 H2 S雰囲気中で800℃以上に45分加熱すること
で、開口部内部以外のRu膜16を硫化し、RuSとす
る。この時、開口部内部のRu表面はSiO2 などの保
護膜を実施例1のような方法で選択的に堆積し保護する
ことで、硫化反応が起こらないようにしておくのが望ま
しい。Example 2 By heating in an H 2 S atmosphere at a temperature of 800 ° C. or more for 45 minutes, the Ru film 16 other than the inside of the opening is sulfided to obtain RuS. At this time, it is desirable to prevent a sulfurization reaction from occurring by selectively depositing and protecting a protective film such as SiO 2 on the Ru surface inside the opening by the method as in the first embodiment.
【0047】その後、RuSxおよびTiN/Ti膜1
5のCMPを、RuSxが可溶な塩酸溶媒を用いた市販
されているスラリーで1分間行うことにより、第2層間
絶縁膜12上のRuSx膜およびTiN/Ti膜15が
除去されて、ホール内のみにRu膜16およびTiN/
Ti膜15が残存し、下部電極18が形成された。Thereafter, RuSx and TiN / Ti film 1
5 is performed for 1 minute with a commercially available slurry using a hydrochloric acid solvent in which RuSx is soluble, whereby the RuSx film and the TiN / Ti film 15 on the second interlayer insulating film 12 are removed, and the inside of the hole is removed. Only the Ru film 16 and TiN /
The Ti film 15 remained, and the lower electrode 18 was formed.
【0048】下部電極が形成された後、開口部内部のR
u表面の保護のために堆積した保護膜は除去する。After the lower electrode is formed, R
The protective film deposited for protection of the u surface is removed.
【0049】[0049]
【発明の効果】請求項1〜4記載の白金族系金属膜の研
磨方法によると、被加工物に設けた白金族系金属膜の研
磨箇所を、反応性の高い化合物(ハロゲン化金属、硫化
金属、酸化金属)に変換することで、研磨し易くなり、
市販されている研磨用スラリーを用いてCMP法による
平坦化を短時間で容易に行うことができる。According to the method for polishing a platinum group metal film according to any one of the first to fourth aspects, the polishing portion of the platinum group metal film provided on the workpiece is treated with a highly reactive compound (metal halide, sulfide). Metal, metal oxide), it becomes easier to polish,
Using a commercially available polishing slurry, planarization by the CMP method can be easily performed in a short time.
【0050】請求項5記載の白金族系金属膜の研磨方法
によると、化学反応性が乏しい白金族系金属膜を、より
反応性の高い化合物に変換させたことで、市販の研磨用
スラリーを用いて、白金族系金属膜を容易かつ迅速に除
去できる。According to the method for polishing a platinum group metal film according to claim 5, a commercially available polishing slurry can be obtained by converting a platinum group metal film having poor chemical reactivity into a compound having higher reactivity. By using it, the platinum group metal film can be easily and quickly removed.
【0051】請求項6記載の白金族系金属膜の研磨方法
によると、反応性の高い化合物に変換された白金族系金
属膜が全て研磨された時点で、研磨レートが遅い白金族
系金属が露出することになり、CMPは自然に終了す
る。According to the method for polishing a platinum group metal film according to the sixth aspect, when the platinum group metal film converted into a highly reactive compound is completely polished, the platinum group metal having a low polishing rate is removed. Exposure will cause CMP to end spontaneously.
【0052】請求項7記載の白金族系金属膜の研磨方法
によると、白金族系金属膜をより反応性の高い化合物に
変換することで、特殊な研磨用スラリーを用いなくて
も、変換後の化合物が可溶な溶媒が用いられているよう
な現在市販されている研磨スラリーを用いることで、白
金族系金属膜を容易かつ迅速に除去できる。According to the method for polishing a platinum group metal film according to claim 7, the platinum group metal film is converted into a compound having a higher reactivity, so that the post-conversion can be performed without using a special polishing slurry. By using a commercially available polishing slurry in which a solvent in which the compound is soluble is used, the platinum group metal film can be easily and quickly removed.
【0053】請求項8記載の半導体記憶装置のセル形成
方法によると、白金族系金属膜を下部電極とするトレン
チ型セルが形成され、白金族系金属膜の微細パターンの
形成が可能であるので、高集積化に適した半導体記憶装
置のセルを形成できる。According to the method for forming a cell of a semiconductor memory device of the present invention, a trench type cell having a platinum group metal film as a lower electrode is formed, and a fine pattern of the platinum group metal film can be formed. Thus, a cell of a semiconductor memory device suitable for high integration can be formed.
【0054】請求項9記載の半導体記憶装置のセル形成
方法によると、白金族系金属膜をより反応性の高い化合
物に変換することで、特殊な研磨用スラリーを用いなく
ても、変換後の化合物が可溶な溶媒が用いられているよ
うな現在市販されている研磨スラリーを用いることで、
白金族系金属膜を容易かつ迅速に除去できる。According to the method for forming a cell of a semiconductor memory device according to the ninth aspect, the platinum group metal film is converted into a compound having a higher reactivity, so that the converted metal can be used without using a special polishing slurry. By using currently commercially available polishing slurries in which a solvent in which the compound is soluble is used,
The platinum group metal film can be easily and quickly removed.
【図1】この発明の実施の形態における白金族系金属膜
により構成される下部電極を有するトレンチ型セルを形
成する工程を示す断面図である。FIG. 1 is a cross-sectional view showing a step of forming a trench cell having a lower electrode composed of a platinum group metal film according to an embodiment of the present invention.
【図2】この発明の実施の形態における白金族系金属膜
により構成される下部電極を有するトレンチ型セルを形
成する工程を示す断面図である。FIG. 2 is a cross-sectional view showing a step of forming a trench cell having a lower electrode composed of a platinum group metal film according to the embodiment of the present invention.
【図3】この発明の実施の形態におけるCMP工程で使
用するCMP用研磨機の構造を示す斜視図である。FIG. 3 is a perspective view showing a structure of a CMP polishing machine used in a CMP step according to the embodiment of the present invention.
【図4】従来の白金族系金属膜で構成される下部電極を
有するスタック型セルを形成する工程を示す断面図であ
る。FIG. 4 is a cross-sectional view showing a step of forming a stacked cell having a lower electrode composed of a conventional platinum group metal film.
11 第1層間絶縁膜 12 第2層間絶縁膜 13 ポリシリコン配線 14 開口部 15 TiN/Ti膜 16 Ru膜(白金族系金属膜) 17 RuClx膜(ハロゲン化白金族系金属膜) 18 下部電極 19 (Ba0.5 ,Sr0.5 )TiO3 膜(誘電体膜) 20 Ru膜(上部電極膜) 31 プラテン 32 プラテン軸 33 研磨パッド 34 キャリア 35 キャリア軸 36 ウエハ 37 研磨液供給装置 38 研磨液REFERENCE SIGNS LIST 11 first interlayer insulating film 12 second interlayer insulating film 13 polysilicon wiring 14 opening 15 TiN / Ti film 16 Ru film (platinum group metal film) 17 RuClx film (halogenated platinum group metal film) 18 lower electrode 19 (Ba0.5, Sr0.5) TiO 3 film (dielectric film) 20 Ru film (upper electrode film) 31 the platen 32 platen shaft 33 the polishing pad 34 the carrier 35 carrier shaft 36 wafer 37 polishing liquid supply device 38 polishing solution
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 27/108 H01L 27/10 651 21/8242 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 H01L 27/10 651 21/8242
Claims (9)
箇所を反応性の高い化合物に変換し、化学機械的研磨法
により研磨することを特徴とする白金族系金属膜の研磨
方法。1. A method for polishing a platinum group metal film, comprising: converting a portion to be polished of a platinum group metal film provided on a workpiece to a highly reactive compound; and polishing the compound by a chemical mechanical polishing method. .
箇所をハロゲン化してハロゲン化金属に変換し、化学機
械的研磨法により研磨することを特徴とする白金族系金
属膜の研磨方法。2. A polishing method for a platinum-group-based metal film, wherein a portion to be polished of the platinum-group-based metal film provided on a workpiece is halogenated to be converted into a metal halide and polished by a chemical mechanical polishing method. Method.
箇所を硫化して硫化金属に変換し、化学機械的研磨法に
より研磨することを特徴とする白金族系金属膜の研磨方
法。3. A method for polishing a platinum group metal film, comprising: sulphidizing a polished portion of a platinum group metal film provided on a workpiece to convert it to a metal sulfide; and polishing by a chemical mechanical polishing method. .
箇所を酸化して酸化金属に変換し、化学機械的研磨法に
より研磨することを特徴とする白金族系金属膜の研磨方
法。4. A method for polishing a platinum group metal film, comprising: oxidizing a portion to be polished of a platinum group metal film provided on a workpiece, converting the polished portion into a metal oxide, and polishing by a chemical mechanical polishing method. .
金属膜の研磨箇所との間に供給し、前記研磨パッドと被
加工物との間に圧力を印加しながら、前記研磨パッドと
前記被加工物とを相対的に回転させて、前記白金族系金
属膜の研磨箇所を研磨することを特徴とする請求項1記
載の白金族系金属膜の研磨方法。5. A polishing slurry is supplied between a polishing pad and a portion to be polished of a platinum group metal film, and a pressure is applied between the polishing pad and a workpiece while the polishing pad and the workpiece are being applied. 2. The method for polishing a platinum group metal film according to claim 1, wherein the polishing portion of the platinum group metal film is polished by relatively rotating a workpiece.
膜の研磨箇所を全て研磨し、研磨レートの異なる金属が
露出した時点で終了することを特徴とする請求項5記載
の白金族系金属膜の研磨方法。6. The platinum-based metal film according to claim 5, wherein the polishing of the platinum-based metal film is completed by polishing all the polished portions of the platinum-based metal film and exposing metals having different polishing rates. A method for polishing a group III metal film.
物に変換された白金族系金属膜が可溶な溶媒を用いるこ
とを特徴とする請求項5または請求項6記載の白金族系
金属膜の研磨方法。7. The platinum group metal according to claim 5, wherein a solvent in which the platinum group metal film converted into a highly reactive compound is soluble is used for the polishing slurry. Polishing method of the film.
積する工程と、 前記層間絶縁膜に前記導体部の少なくとも一部に到達す
る開口部を形成する工程と、 前記開口部内および前記層間絶縁膜の上に白金族系金属
膜を堆積する工程と、 開口部内部以外の白金族系金属膜を反応性の高い化合物
に変換する工程と、 化学機械的研磨にて前記層間絶縁膜が露出するまで前記
反応性の高い化合物に変換した白金族系金属膜を除去す
ると共に、前記開口部に前記白金族系金属膜を残存させ
て下部電極を形成する工程と、 前記下部電極の上に誘電体膜を堆積する工程と、 前記誘電体膜の上に上部電極膜を堆積する工程とを含む
半導体記憶装置のセル形成方法。8. A step of depositing an interlayer insulating film on a substrate having a conductor portion, a step of forming an opening in the interlayer insulating film to reach at least a part of the conductor portion, A step of depositing a platinum group metal film on the insulating film, a step of converting the platinum group metal film other than the inside of the opening to a highly reactive compound, and exposing the interlayer insulating film by chemical mechanical polishing. Removing the platinum-group-based metal film converted to the highly reactive compound until forming a lower electrode by leaving the platinum-group-based metal film in the opening, and forming a dielectric on the lower electrode. A cell forming method for a semiconductor memory device, comprising: depositing a body film; and depositing an upper electrode film on the dielectric film.
物に変換された白金族系金属膜が可溶な溶媒を用いるこ
とを特徴とする請求項8記載の半導体記憶装置のセル形
成方法。9. The method according to claim 8, wherein a solvent in which the platinum group metal film converted into a highly reactive compound is soluble is used as the polishing slurry.
Priority Applications (1)
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JP10332548A JP2000164545A (en) | 1998-11-24 | 1998-11-24 | Polishing method of platinum metal film and cell forming method of semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10332548A JP2000164545A (en) | 1998-11-24 | 1998-11-24 | Polishing method of platinum metal film and cell forming method of semiconductor storage device |
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Publication Number | Publication Date |
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JP2000164545A true JP2000164545A (en) | 2000-06-16 |
Family
ID=18256159
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JP10332548A Pending JP2000164545A (en) | 1998-11-24 | 1998-11-24 | Polishing method of platinum metal film and cell forming method of semiconductor storage device |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001217403A (en) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
JP2004514266A (en) * | 1999-12-14 | 2004-05-13 | ロデール ホールディングス インコーポレイテッド | Polishing composition for precious metals |
KR100445067B1 (en) * | 2001-12-31 | 2004-08-21 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
JP2006519490A (en) * | 2003-02-27 | 2006-08-24 | キャボット マイクロエレクトロニクス コーポレイション | CMP method for precious metals |
US7189616B2 (en) | 2001-02-09 | 2007-03-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same |
-
1998
- 1998-11-24 JP JP10332548A patent/JP2000164545A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004514266A (en) * | 1999-12-14 | 2004-05-13 | ロデール ホールディングス インコーポレイテッド | Polishing composition for precious metals |
JP2001217403A (en) * | 2000-02-04 | 2001-08-10 | Hitachi Ltd | Semiconductor integrated circuit device and method of manufacturing the same |
US7189616B2 (en) | 2001-02-09 | 2007-03-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same |
US7285462B2 (en) | 2001-02-09 | 2007-10-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same |
KR100445067B1 (en) * | 2001-12-31 | 2004-08-21 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
JP2006519490A (en) * | 2003-02-27 | 2006-08-24 | キャボット マイクロエレクトロニクス コーポレイション | CMP method for precious metals |
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