JP2000151735A - Phase detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of the phase detection circuit by converting a phase modulated signal into a rectangular signal by shaping its waveform and holding a signal corresponding to the logical value of the rectangular signal by a capture signal having a reference phase for a carrier signal as a demodulated data signal. SOLUTION: A receiving circuit 1 receives a signal transmitted from a card of an electronic money system and sends a BPSK modulation signal obtained by advancing or delaying the phase of the received signal by 180 deg. to a waveform shaping circuit 2. The circuit 2 shapes the waveform of the received signal as a binary rectangular signal by level discrimination and sends the waveform shaped signal to the data terminal D of a D flip flop(DFF) circuit 3. A capture signal generation circuit 4 sends a capture signal generated from the carrier signal to the clock terminal of the DFF circuit 3. The DFF circuit 3 stores the logical value of the rectangular signal on the data terminal D in each reception of the capture signal and outputs the stored value to an output terminal Q as demodulated data. Thus a modulated signal can be demodulated only by the digital processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation circuit for detecting a phase-modulated signal, and more particularly, to a technique for promoting digitization.

[0002]

2. Description of the Related Art A conventional general phase detection circuit is almost entirely constituted by an analog circuit, so that the circuit becomes large and the output waveform contains many high-frequency components.
A retrofitting circuit such as a comparator and the like was required.

For this reason, a phase-modulated signal is converted into a rectangular signal, a phase difference from a reference rectangular signal is detected using an exclusive OR gate, and a voltage corresponding to the phase difference is A / D converted. At the same time, a phase detection circuit that eliminates uncertainty in relation to a comparison value with a rectangular signal having a phase difference of 90 ° is proposed for a phenomenon in which the same voltage output is generated at a phase difference of 180 °. (See Japanese Utility Model Application Laid-Open No. 4-92816).

[0004]

In the phase detection circuit of the above system, digitization is promoted to some extent. However, after the digitized phase difference signal is converted into an analog voltage, it is converted into a digital signal again. However, there are still many analog processed parts, such as using an analog voltage as a comparison judgment for removing the uncertain difference, which hinders miniaturization.

The present invention has been made in view of such a conventional problem, and has as its object to provide a compact and simplified phase detection circuit which promotes digitization as much as possible. I do.

[0006]

According to a first aspect of the present invention, there is provided a waveform shaping circuit for shaping a waveform of a phase-modulated signal into a rectangular signal converted into binary logic, and a carrier wave of the phase-modulated signal. A capture signal generation circuit that generates a capture signal having a reference phase with respect to a signal, and a capture signal output from the capture signal generation circuit, which outputs a signal corresponding to a logical value of the rectangular signal at the time of the capture signal output. And a data acquisition circuit for holding and outputting the held signal as a demodulated data signal.

According to the first aspect of the present invention, the phase-modulated signal is waveform-shaped into a rectangular signal converted into binary logic by the waveform shaping circuit, and the data capture circuit captures the signal output from the capture signal generation circuit. According to the signal, a signal corresponding to the logical value of the rectangular signal is held until the next acquisition signal output, and the held signal is output as a demodulated data signal.

[0008] In this way, the modulation signal can be demodulated only by digital processing, and thus the data acquisition circuit can be incorporated in a PLD or the like, and the miniaturization is promoted.

Further, the invention according to claim 2 is characterized in that the data acquisition circuit is a flip-flop circuit that operates by inputting the acquisition signal and a rectangular signal.

According to the second aspect of the present invention, the flip-flop circuit constituting the data capturing circuit outputs and holds a signal corresponding to the logical value of the rectangular signal every time the capturing signal is input at a constant period, When the phase changes, the logical value of the rectangular signal at the time of input of the capture signal changes, so that a signal corresponding to the changed logical value is held and a demodulated data signal corresponding to the phase modulation is output.

The invention according to claim 3 is characterized in that the data acquisition circuit is a sample and hold circuit that samples and holds a rectangular signal by the acquisition signal.

According to the third aspect of the present invention, the sample-and-hold circuit constituting the data acquisition circuit samples and holds the rectangular signal every time the acquisition signal is input at a constant period, thereby responding to the logical value of the rectangular signal. When the output of the signal is held and the phase of the rectangular signal changes, the logical value of the rectangular signal sampled and held when the capture signal is input changes.
A signal corresponding to the changed logical value is output and held, whereby a demodulated data signal corresponding to the phase modulation is output.

According to a fourth aspect of the present invention, in the data acquisition circuit, the A / D converter converts a logical value of a rectangular signal into bit pattern data, and latches the converted bit pattern data by the capture signal. And a latch circuit that performs the operation.

According to the fourth aspect of the present invention, the A / D converter inputs a rectangular signal digitized as a binary signal as an analog signal and performs A / D conversion to convert the logical value of the rectangular signal into a bit pattern. The demodulated data signal is converted into data, and the converted bit pattern data is latched when the capture signal is input, whereby a demodulated data signal having logical value data corresponding to the phase modulation is output.

According to a fifth aspect of the present invention, the acquisition signal generation circuit generates and outputs a plurality of acquisition signals having different reference phases, and the data acquisition circuit generates a rectangular signal based on each acquisition signal. A demodulated data signal is output as a combination of a plurality of signals held according to a logical value.

According to the fifth aspect of the present invention, the data acquisition circuit receives a plurality of acquisition signals having different reference phases from the acquisition signal generation circuit, and holds the plurality of acquisition signals according to the logical value of the rectangular signal. Are output as demodulated data signals. Thereby, the multi-level phase modulation signal can be demodulated as a combination signal of a plurality of binary data.

[0017]

Embodiments of the present invention will be described below. FIG. 1 shows the configuration of the first embodiment. For example, in an electronic money system, a phase modulation signal transmitted from a card on which information is recorded is received by a receiving circuit 1, and the received phase modulation signal is input to a waveform shaping circuit 2.

The waveform shaping circuit 2 shapes the waveform of the phase modulated signal into a rectangular signal which has been level-discriminated and converted into binary values of logical values "0" and "1", and converts the rectangular signal into a D signal as a data acquisition circuit. The data is output to the data terminal of the flip-flop circuit 3.

On the other hand, the carrier signal of the phase-modulated signal received by the receiving circuit 1 is input to a capture signal generating circuit 4,
The acquisition signal generation circuit 4 generates an acquisition signal having a reference phase with respect to the carrier signal. That is, the capture signal is output at regular intervals as a pulse signal having the same frequency as the carrier signal, and the logic value of the rectangular signal at the time of the capture signal output changes according to a change in phase. A reference phase for the carrier signal is set. Such a capture signal can be generated by shifting the phase of the carrier signal reproduced from the phase modulation signal by a phase shift circuit. Then, the capture signal generated by the capture signal generation circuit 4 is output to the clock terminal of the D flip-flop circuit 3.

Each time the capture signal is input to the clock terminal, the D flip-flop circuit 3 outputs a signal corresponding to the logical value of the rectangular signal input to the data terminal at the time of input of the capture signal, to the next capture signal input. Keep outputting until time.

Here, the waveform shaping circuit 2, D flip-flop circuit 3, and capture signal generation circuit 4 constitute a phase detection circuit according to the present invention. The acquisition signal generation circuit 4 is configured to input a carrier signal of the phase-modulated signal to form an acquisition signal, and to input another external signal having the same frequency as the carrier signal to form an acquisition signal. It may be.

A series of operations of the phase detection circuit having such a configuration will be described with reference to FIG. 2 showing signal waveforms of respective parts. The phase modulation signal a input to the waveform shaping circuit 2 is a signal that is BPSK-modulated by advancing or delaying the phase by 180 °. The phase-modulated signal “a” is waveform-shaped by the waveform shaping circuit 2 to obtain a binarized rectangular signal “b”, and the capture signal generation circuit 4 captures the carrier signal of the phase-modulated signal “a” with a reference phase. A signal c is generated.

When the logical value of the rectangular signal b at the time of output of the capture signal c is "1", the output of the D flip-flop circuit 3, that is, the demodulated data signal d becomes "1", and the phase modulation signal a As long as the phase does not change, the same state is maintained and the demodulated data signal d is continuously held at "1". When the phase of the phase modulation signal a is advanced by 180 °, the logical value of the rectangular signal b at the time of output of the capture signal c becomes “0”, the output of the D flip-flop circuit 3 is inverted, and the demodulated data signal d becomes “0”. Is held. From this state, the phase modulation signal a
Is delayed by 180 °, the phase is returned to the initial phase, so that the demodulated data signal d is again held at “1”. Thus, demodulated data corresponding to the phase modulation is output. As described above, the detection value at the position where the phase difference is 180 ° has the opposite logic of the signal, and there is no identical value.

FIG. 3 shows the configuration of a phase detection circuit according to the second embodiment, and FIG. 4 shows signal waveforms at various parts of the circuit. This device performs phase detection on a phase modulated signal e that has been QPSK-modulated by advancing or delaying the phase by 90 °, and as a capture signal generation circuit, the reference phase of the phase modulated signal with respect to the carrier signal is mutual. To 9
A capture signal generation circuit 1 that generates a capture signal h and a capture signal j (a phase of which is delayed by 90 ° from h) shifted by 0 °.
4A and a capture signal generation circuit 14B, a D flip-flop circuit 13A that inputs the capture signals h and j to each clock terminal, and inputs a rectangular signal f obtained by shaping the waveform of the phase modulation signal e to each data terminal. And a D flip-flop circuit 13B.

Then, the D flip-flop circuit 1
A demodulated data signal is obtained by a combination of the signal g output from 3A and the signal i output from the D flip-flop circuit 13B.

More specifically, in FIG.
The logical values of the rectangular signal f at the time of output are both “1”, and the signals g,
When the phase of the phase modulation signal e is advanced by 90 ° from the initial state in which both i are “1”, the logic value of the rectangular signal f at the time of output of the capture signal h remains “1” and the signal g becomes “1”. Although it is held at "1", the logical value of the rectangular signal f at the time of output of the capture signal i changes to "0", and the signal i switches to "0". Next, when the phase of the phase modulation signal e is further advanced by 180 ° (advanced by 270 ° or delayed by 90 ° from the initial state), the logical value of the rectangular signal f at the time of output of the capture signal h changes to “0”. As a result, the signal g switches to "0", the logical value of the rectangular signal f at the time of output of the capture signal j becomes "1", and the signal i switches to "1". Further, when the phase of the phase modulation signal e is delayed by 90 ° (shifted by 180 ° from the initial state), the logic value of the rectangular signal f at the time of output of the capture signal h remains “0” and the signal g becomes “0”. And the captured signal j
The logical value of the rectangular signal f at the time of output becomes “0”, and the signal i switches to “0”.

Thus, the signal g is the phase modulated signal e
Is “1” when the phase is advanced by 90 ° with respect to the initial state, and is “0” when the phase is shifted 180 ° from the initial state and when the phase is delayed by 90 °. "1" in the state and the state where the phase is delayed by 90 °
And becomes “0” when the phase is advanced by 90 ° and when the phase is shifted by 180 °, so that these two signals g and i
, A demodulated data signal having 2-bit 4-valued information can be obtained.

FIG. 5 shows a configuration of a phase detection circuit according to the third embodiment. The data acquisition circuit is constituted by a sample-and-hold circuit 21 instead of the D flip-flop circuit of the first embodiment. It was done.

That is, when the capture signal is input from the capture signal generation circuit 4, the sample and hold circuit 21 samples and holds the instantaneous value of the rectangular signal input from the waveform shaping circuit 2 at the time of input of the capture signal. Since the output value is held as a demodulated data signal until the next capture signal is input, it has the same function as the first embodiment using the D flip-flop circuit.

FIG. 6 shows a configuration of a phase detection circuit according to a fourth embodiment, in which a data acquisition circuit is replaced with a waveform shaping circuit 1.
A / D converter 31 for converting the logical values "1" and "0" of the rectangular signal into bit pattern data by inputting the rectangular signal from the analog signal as an analog signal and performing A / D conversion; The latch circuit 32 latches the converted bit pattern data when a capture signal is input from the circuit 4 and outputs the latched bit pattern data as a demodulated data signal. Even in this manner, a demodulated data signal having logical value data corresponding to the phase modulation can be output.

In the second embodiment, instead of the D flip-flop circuits in the second embodiment, the sample and hold circuits, A / D converters, and latch circuits used in the third and fourth embodiments are used. Of course, it can be configured.

As described in the above embodiments, according to the present invention, digital processing can be promoted as much as possible by converting all rectangular signals, captured signals, and demodulated data signals into digitized signals. Since a data acquisition circuit that directly detects and demodulates phase modulation or a part of the data acquisition circuit can be constituted only by a circuit having no analog section such as a D flip-flop circuit, a sample hold circuit, and a latch circuit, the PLD
Etc., and the entire circuit can be reduced in size.

Further, since the circuit scale can be reduced in this way, it becomes possible to correct a communication error by using a plurality of phase detection circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms of respective units according to the first embodiment.

FIG. 3 is a circuit diagram showing a configuration according to a second embodiment of the present invention.

FIG. 4 is a diagram showing signal waveforms of respective units according to the second embodiment.

FIG. 5 is a circuit diagram showing a configuration according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration according to a fourth embodiment of the present invention.

[Explanation of symbols]

 2 Waveform shaping circuit 3 D flip-flop circuit 4 Capture signal generation circuit 13A D flip-flop circuit 13B D flip-flop circuit 14A Capture signal generation circuit 14B Capture signal generation circuit

Claims (5)

[Claims] 1. A waveform shaping circuit for shaping a waveform of a phase-modulated signal into a rectangular signal converted into binary logic, and a capture signal having a reference phase with respect to a carrier signal of the phase-modulated signal. A capture signal generation circuit, and a capture signal output from the capture signal generation circuit;
A data acquisition circuit for holding a signal corresponding to the logical value of the rectangular signal at the time of output of the acquisition signal, and outputting the held signal as a demodulated data signal. . 2. The phase detection circuit according to claim 1, wherein said data acquisition circuit is a flip-flop circuit that operates by inputting said acquisition signal and a rectangular signal. 3. The phase detection circuit according to claim 1, wherein the data acquisition circuit is a sample-and-hold circuit that samples and holds a rectangular signal based on the acquisition signal. 4. The data capturing circuit includes an A / D converter that converts a logical value of a rectangular signal into bit pattern data, and a latch circuit that latches the converted bit pattern data using the capturing signal. The phase detection circuit according to claim 1, wherein: 5. The capture signal generation circuit generates and outputs a plurality of capture signals having different reference phases, and the data capture circuit is held by each capture signal according to a logical value of a rectangular signal. The phase detection circuit according to any one of claims 1 to 4, wherein the demodulation data signal is output as a combination of a plurality of signals.