JP2000151569A - Data synchronous device, method therefore and noncontact ic card having data synchronous device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable data synchronization for sure waveform shape without being influenced by a jitter or a glitch with a simple structure by monitoring a position where an edge signal exists in accordance with a second timing signal and outputting a preset signal when the position is in a period of a first timing signal or a period of a neighborhood of the signal. SOLUTION: A start detection part 102 detects a first edge signal from the edge detection part 101 to be outputted after an input signal is supplied and generates a start signal for starting count operation of a counter 104 based on the signal. A synchronous deviation detection part 103 detects whether or not an edge of the input signal exists in a period in which the input signal is sampled when a count value of the counter 104 is a specified value. When it exists, it is regarded that data synchronous deviation occurs, a synchronous deviation detection signal is outputted, this signal is transmitted to the counter 104 and the count value of the counter 104 is preset to a specified value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data synchronization device for shaping a digital signal waveform, a data synchronization method, and a contactless IC card having the data synchronization device.
The present invention relates to a data synchronizer, a data synchronization method, and a non-contact IC card having a data synchronizer that can reliably perform waveform shaping with a simple configuration.

[0002]

2. Description of the Related Art In recent years, as a data carrier for recognizing a moving object such as a person, a car, or a luggage, a modulated signal spatially transmitted from a data transmitting / receiving device called a reader / writer is received, demodulated, decoded, and decoded. RF, which is generally referred to as a non-contact IC card or an ID tag, which is configured to store necessary data or transmit data to a reader / writer according to a decoding result.
-ID (Radio Frequency Identification) is frequently used.

[0003] Here, the RF-ID will be outlined. FIG. 7 shows an example of the structure of transmission data transmitted between the reader / writer and the RF-ID. In FIG. 7, a 3-byte preamble (PREAMB) is provided at the head of the transmission data.
LE). Preamble (PREAMBL
The data of E) is mainly used for synchronization processing at the time of data demodulation in RF-ID. Preamble (PREAMB
Two bytes following (LE) are a sync code (SYNC). The sync code (SYNC) is used as a timing reference to detect data after the sync code (SYNC).

One byte following the sync code (SYNC) is length information (LENGTH). Length information (LEN
GTH) indicates the effective length of data (DATA) arranged following the length information (LENGTH). In the subsequent data (DATA), data for controlling communication between the reader / writer and the RF-ID, control data for the RF-ID itself, user data, and the like are distributed according to a predetermined rule. Two bytes following the data (DATA) are a check code (CRC) for the data (DATA). Among the data constituting the transmission data, data other than the preamble (PREAMBLE) is RF-I
This is significant data that must be accurately reproduced (demodulated) in D.

FIG. 6 shows an example of the configuration of a conventional battery-less RF-ID. Here, the RF-ID of FIG. 6 will be described separately for a receiving system and a transmitting system. First, the receiving system will be described. In FIG. 6, 60
Reference numeral 1 denotes a signal spatially transmitted from a reader / writer (a signal subjected to amplitude modulation by data to be transmitted.
It is called a carrier signal. ) Is a receiving element composed of a loop coil or the like for receiving).

[0006] 602 is an RF signal from the received carrier signal.
-A power generation unit that generates power for each circuit inside the ID. Reference numeral 603 denotes a clock generation unit that generates a clock signal from the received carrier signal. A demodulation unit 604 demodulates transmission data as shown in FIG. 7 included in the received carrier signal. Demodulated output signal 605 of demodulation section 604
Is a binary logic digital signal such as communication control data between a reader / writer and RF-ID, control data for RF-ID itself, or user data.

A digital signal processing unit 606 decodes and decodes significant data among the transmission data demodulated by the demodulation unit 604, and performs a process of responding to a request from a reader / writer based on the decoding result. It is. The digital signal processing unit 606 writes or reads out data necessary for determination processing, arithmetic processing, or these processings to / from the memory 609 via the memory write / read bus 608 depending on the result of the decoding. Perform processing and the like. Further, depending on the result of the decoding, a transmission process for encoding and preparing the transmission data format as shown in FIG. 7 described above in order to transmit data obtained as a result of the judgment process, the arithmetic process or the memory process to the reader / writer is also performed. . 6
A memory control signal 07 includes a write address, a read address, a memory enable signal, and the like for memory processing.

Next, an RF-ID transmission system will be described. As described above, the digital signal processing unit 606 performs transmission processing in accordance with the result of decoding or decoding of the received significant data, encodes data obtained as a result of determination processing, arithmetic processing, or memory processing, and processes transmission data. Format it. Reference numeral 610 denotes transmission data arranged in a transmission data format. A modulation unit 611 modulates the amplitude of a non-modulated carrier signal based on a clock signal with transmission data. The carrier signal generated by the modulation unit
1 and spatially transmitted to the reader / writer.

[0009] Regarding such RF-ID, main items required by the system user are as follows. 1. The time when the RF-ID is close to the reader / writer is as short as possible, and a lot of data is transmitted during that time. 2. Even if the RF-ID moves and approaches the reader / writer, stable communication is performed. 3. Cost is low. There are also disposable uses. 4. The mechanical strength is strong.

The following items can be mentioned as technical guidelines for satisfying these requirements. 1. Simple start-stop synchronization is not used in the communication procedure to increase the transfer rate. 2. Increases jitter resistance, fading resistance, and power supply voltage variability. 3. The circuit configuration is simplified and integrated into an IC. 4. Make the chip size of the IC as small as possible.

In accordance with the technical guidelines as described above, in the conventional RF-ID, measures are generally taken to stabilize the power generated by the power generator 602 or to improve the performance of the demodulator 604. Was. Further, in order to eliminate the PLL for generating the internal clock signal of the RF-1D, the frequency of the carrier signal is transmitted as a multiple of the data frequency, and the clock generation unit 603 directly generates the clock signal from the carrier signal. As a data synchronization method in the receiving system,
UART (Universal Asynchronous Receiver-Transmit)
It is also considered to perform waveform shaping using an algorithm such as ter).

[0012]

In the conventional RF-ID, various countermeasures have been taken to meet the demands of the system user, but there are still the following problems. Even if the digital signal has been subjected to any encoding, it undergoes some distortion when passed through an analog modulation / demodulation system, and only an approximate waveform can be reproduced. In order to minimize the amount of this distortion, measures such as stabilizing the power supply and improving the performance of the demodulation unit are taken as described above. However, in the batteryless RF-1D, not only data is carried on a carrier signal as in general wireless communication, but also the carrier signal is used as a power source. Therefore, the generated power is not independent of the communication conditions, and a stable power cannot be secured, so that an error occurs in the result of decoding and decoding in the digital signal processing unit 606. There is a point. In addition, there is also a problem that when it is attached to a moving body (including a case where it is held in a hand), it is affected by fading.

Further, as described above, in order to eliminate the PLL for generating the internal clock of the RF-1D, the frequency of the carrier signal is transmitted at a multiple of the data frequency, and the clock is directly generated from the received carrier signal. In this case, the fact that the clock signal is a multiple of the data frequency means that a clock signal synchronized with the data can be obtained by frequency division. Since the phase relationship between the transmitting side and the receiving side depends on the communication conditions, there is a problem that it does not actually work.

When establishing synchronous communication in RF-ID, it is conceivable to perform waveform shaping (data synchronization) using an algorithm such as the UART described above. Since data synchronization is based on the first edge of a level transition (hereinafter referred to as an edge) caused by data, the reliability of the first edge is important. However, unlike wired communication, RF-1D contains a lot of jitter (phase fluctuation of edges) and glitches (unnecessary pulse noise), so that erroneous discrimination between edges and noise is likely to occur. Therefore, RF-1
If this method is used in D, there is a problem that shaping errors are likely to occur frequently when communication conditions are severe.

Further, as a problem peculiar to RF-ID, R
There are three factors that make F-ID communication unstable, a vicious circle due to the synergistic effect of “external noise”, “offset drift”, and “power supply fluctuation”. The extraneous noise causes a change in the carrier signal, generates pulse noise in the demodulated signal, and causes the above-mentioned jitter and glitch in the decoded signal. The offset drift causes fluctuation in the detection output due to the influence of the temperature characteristics of the semiconductor in demodulation of the carrier signal and the like, and as a result, jitter occurs at the edge of the demodulation output signal 605. The power supply fluctuation is particularly problematic in a battery-less RF-ID that generates power from a carrier signal. The power supply generation unit 602 includes a stabilization circuit for a while. Due to external factors, stable power generation is not always performed during communication.

In addition, since the maximum supply power of the power generation unit 602 satisfies the required power but is not large, the generated power is affected by the transient of the digital signal processed by the digital signal processing unit 606. Easy to fluctuate. If a negative effect occurs in any one of these three factors, the following occurs: [● Jitter and glitch generation → ● Malfunction of digital circuit system (digital signal processing unit 606) → ● Transient generation in digital circuit system → ● Power generation unit Power supply fluctuation of 602 → Analog circuit system (demodulation unit 6
04) Malfunction: → jitter, glitch generation] occurs. This vicious cycle is largely related to the "maximum communication distance" which is the most important item of the performance index of the RF-ID, and the more the RF-ID is less resistant to the above three factors, the more the maximum is. There is a problem that the communication distance is reduced. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to achieve data synchronization for waveform shaping reliably with a simple configuration without being affected by jitter or glitches. An object, a data synchronization method, and a contactless IC card having a data synchronization device are provided.

[0017]

SUMMARY OF THE INVENTION The present invention provides a data synchronizer for shaping a waveform by synchronizing an input signal comprising a digital signal with a predetermined clock signal, and detects an edge of the input signal to output an edge signal. Edge detection means, of the edge signals, an edge signal which is output first when the input signal is input, and a start detection means for generating a start signal when the edge signal is detected; The count of a clock signal having a cycle of 1 / N (N is an integer) of the minimum cycle of the input signal is started to generate a count value, and a first timing signal is generated at a first predetermined value among the count values. A second timing signal is generated at a second predetermined value among the count values, and when a preset signal is received, the second timing signal is generated. A counter for setting a count value to a value at which the phase of the first timing signal shifts, sampling the input signal according to the first timing signal, and using the sampled signal as an output signal with data synchronization Sampling means for outputting, the second
The position where the edge signal exists is monitored in accordance with the timing signal of
And a preset signal generating means for outputting the preset signal during the period of the timing signal or the period near the first timing signal.

Further, in the data synchronizer of the present invention, the counter is a cyclic counter for generating a cyclic count value, and the counter of the count value for each period corresponding to a half cycle of the minimum cycle of the input signal. Generating a first predetermined value and said second predetermined value; In the data synchronization device of the present invention, the cyclic counter cyclically counts in a period corresponding to a minimum cycle of the input signal,
The second count value is generated one count after the first predetermined value among the count values. Further, in the data synchronizer of the present invention, when the cyclic counter receives the preset signal, the cyclic counter sets a count value to a first predetermined value among the count values.

Still further, the present invention is a data synchronization method for shaping a waveform by synchronizing an input signal composed of a digital signal with a predetermined clock signal, and detects an edge of the input signal and outputs an edge signal. A detecting step, of the edge signals, detecting an edge signal that is output first when the input signal is input, and detecting a start signal when the edge signal is detected. The count of a clock signal having a cycle of 1 / N (N is an integer) of the minimum cycle of the input signal is started to generate a count value, and a first timing signal is generated at a first predetermined value among these count values. A counting step of generating a second timing signal at a second predetermined value of the count values; A sampling step of sampling the input signal according to the first timing signal and outputting the sampled signal as a data-synchronized output signal; and determining a position where the edge signal exists according to the second timing signal. A preset signal generating step of outputting the preset signal when the position where the edge signal is present is a period of the first timing signal or a period near the first timing signal; A count value setting step of setting the count value of the counter to a value at which the phase of the first timing signal shifts.

Still further, according to the present invention, a modulated signal spatially transmitted from a data transmitting apparatus and modulated by a data signal is received, and a power source is generated from the received modulated signal by a built-in power source generating means. A clock signal is generated from the received modulated signal by the clock generation means, and a signal processing operation is activated by a power supply generated by the power generation section, and digital signal processing is performed using the clock signal generated by the clock generation means. And
In the non-contact IC card configured to obtain the data signal from the received modulation signal and perform predetermined data processing according to the data signal, the power generated by the power generation unit is supplied. Demodulating means for demodulating the data signal from the modulated signal and outputting the data signal; supplying power generated by the power generating section; supplying an output signal of the demodulating means; and outputting the output of the demodulating means by the clock signal. A signal is sampled and output during a predetermined sampling period, and when the edge of the output signal of the demodulation unit is in the sampling period or a period near the sampling period, the sampling phase is changed to thereby output the signal of the demodulation unit. Data synchronization means for performing data synchronization for the power supply unit when the power generated by the power generation unit is supplied. A digital signal processing means for receiving an output signal of the data synchronizing means, decoding the output signal of the data synchronizing means using the clock signal, and performing predetermined data processing according to the decoding result. is there.

In the contactless IC card according to the present invention, the data synchronization means detects an edge of an output signal of the demodulation means and outputs an edge signal. Start detection means for detecting an edge signal output first when an output signal of the demodulation means is input, and generating a start signal when the edge signal is detected; a minimum period of an output signal of the demodulation means by the start signal Count of a clock signal having a cycle of 1 / N (N is an integer) of the count value is generated, a first timing signal is generated at a first predetermined value of the count values, and Generating a second timing signal at a second predetermined value of the values, and receiving the preset signal to change the count value to the first timing signal; A counter for setting a phase shift value; a sampling means for sampling an output signal of the demodulation means in accordance with the first timing signal; and outputting the sampled signal as a data-synchronized output signal; Monitoring the position where the edge signal exists in response to the second timing signal, and determining that the position where the edge signal exists is a period of the first timing signal or a period near the first timing signal. It comprises a preset signal generating means for outputting a signal.

In the non-contact IC card according to the present invention, the counter is a cyclic counter for generating a cyclic count value, and the counter is counted every period corresponding to a half cycle of a minimum cycle of the output signal of the demodulating means. The first of the values
And the second predetermined value. Also,
In the non-contact IC card according to the present invention, the cyclic counter cyclically counts in a period corresponding to the minimum cycle of the output signal of the demodulating means, and after one count of the first predetermined value of the count values, The second predetermined value is generated. Further, in the contactless IC card according to the present invention, upon receipt of the preset signal, the cyclic counter sets the count value to a first predetermined value among the count values.

[0023]

Embodiments of the present invention will be described below in detail. In RF-ID communication, the data rate on the transmission side is managed with very high frequency accuracy.
As described above, this is affected by disturbance such as jitter and noise at the stage of passing through the transmission path and the demodulation circuit. However, since glitches due to jitter and noise do not change the fundamental data rate, the data rate that can be received on the receiving side fluctuates when viewed in a very narrow time range, but is somewhat wider Looking at the range, it has not changed. Assuming that there is no change in the data rate, it is possible to predict the next edge based on the data edge and the minimum cycle (change cycle) of this edge. The present invention utilizes the technique of predicting the edge of the data, and in sampling the input signal for data synchronization for the purpose of waveform shaping, sampling is performed while avoiding the edge of the data without fail. It is.

FIG. 1 shows the configuration of the data synchronization circuit 1 of the present invention. FIG. 2 is a waveform chart for explaining the operation of the data synchronization circuit of the present invention. In FIG. 1, an input signal which is a digital signal including jitter, glitch, and noise is input to the edge detection unit 101 and the latch circuit 105. The edge detection unit 101 detects an edge of the input signal (either a rising edge or a falling edge), and outputs an edge signal when the edge is detected.

The start detecting section 102 includes the edge detecting section 1
Among the edge signals output from 01, a first edge signal output after the input signal is supplied is detected, and a start signal for starting the counting operation of the counter 104 is generated based on the detected first edge signal. When the count value of the counter 104 is a predetermined value as described later, the synchronization shift detection unit 103 detects whether an edge of the input signal exists during a period of sampling the input signal based on the edge signal. , And outputs a synchronization shift detection signal on the assumption that a data synchronization shift has occurred. The out-of-synchronization detection signal is sent to the counter 104,
Is preset to a predetermined value.

The counter 104 counts a clock signal (not shown) having a period of 1 / N (N is an integer, in this example, 4) of a change period of the edge of the input signal (FIG. 2A) and circulates a count value. C0 to Cm (in this example, C0 to Cm
7) (FIG. 2B). Note that the count values C0 to C
The number of m is an integer multiple of N. The first predetermined values “Cl” and “C5” of these count values are defined as a period during which the input signal can be sampled.
Reference numeral 04 generates a sampling pulse (FIG. 2C) for sampling (latching) the input signal during the sampling enabled period.

Also, the first of the count values of the counter
Second predetermined value “C2” which is one count later than the predetermined value of “C2”
And "C6" are defined as a synchronization shift detection period for detecting the data synchronization shift, and generate a detection pulse (FIG. 2D) for detecting the data synchronization shift. Note that the synchronization shift detection period does not necessarily have to be a count value delayed by one count from the sampleable period, and may be a count value corresponding to the vicinity of the sampleable period. The latch circuit 105 latches an input signal by a sampling pulse and outputs the latched signal as an output signal with data synchronization.

If the above-mentioned synchronization error detection signal has not been generated, that is, if there is no edge in the sampling enabled period, the counter sets the count value to "C0" as shown in FIG. 2B.
, And continues to count at "C7", and accordingly, the sampling pulse of the input signal and the edge detection pulse are also kept generated at a constant phase. An edge exists in the sampling enabled period (for example, an edge exists in the first “1” period of the count value (FIG. 2B) (FIG. 2A))
In this case, as described above, a synchronization error detection signal is generated in a synchronization error detection period that is delayed by one count from the sampling enabled period or located near the sampling enabled period, and the counter 104 is forcibly set to a predetermined value. The counter is preset to a count value (“C5” in this example), and thereafter, the counter repeats the cycle with the preset count value “C5” as an initial value and continues counting.

FIG. 2E shows how the count value changes by presetting. The count value indicated by the broken line is before the preset, and the count value indicated by the solid line is after the preset. As the preset count value, a count value (in this example, “C5”) indicating the sampling available period is used. Accordingly, a sampling pulse (FIG. 2F) and a detection pulse (FIG. 2G) having a new phase shifted with respect to before the change are generated in accordance with the new count value changed by the preset. Note that the preset count value does not necessarily have to be a count value indicating a sampling enabled period.

As described above, the phase of the sampling pulse is shifted according to whether or not the edge of the input signal exists during the sampling enabled period. Since the signal portion is sampled (latched), the output signal of the latch circuit 105 is synchronized with the clock signal, and the jitter, glitch, and noise existing in a range other than the sampling period are eliminated.

FIG. 3 is a diagram showing a configuration of the data synchronizer 2 according to the embodiment of the present invention. In FIG. 3, an input signal which is a digital signal including jitter, glitch, and noise is supplied to an input buffer 201. D-type flip-flop (referred to as D-FF) 20 as an input buffer
Numeral 1 synchronizes the input signal with a clock CK2 having a frequency 128 times the data rate of the input signal. D-FF2
01, the jitter and glitch below the frequency of the clock signal CK2 pass through, but the D-FF 20
The purpose of 1 is merely to synchronize the input signal with the clock signal CK2, and there is no problem. The D-FF 201 may be omitted.

Two D-FFs 20 as edge detection units
2, 203 and AND gate 204 detect the rising edge of the input signal. The clock signal CK uses a frequency eight times as high as the data rate of the input signal, and the first D-FF 202 also has a function of removing glitches higher than the clock frequency. Edge detection is performed by the second D-FF 203 and the AND gate 204 connected thereto. AN
The D gate 204 has a rising edge, that is, the first D gate.
The output of the FF 202 is “1”, and the second D-FF 203
Outputs a pulse (edge signal) for one cycle of the clock signal.

The OR gate 206 and the D-FF 207, which are start detection units, detect the first edge of the edges of the input signal and output a start signal. When the edge signal is input to the OR gate 206, the output of the D-FF 207 is set to "1" and the reset signal (RESET)
Is maintained until is supplied.

A 3-bit counter 208 as counting means
In the initial state, a specific value (for example, “4”) corresponding to the phase of the rising edge of data is set. When a start signal is received from the D-FF 207 of the start detection unit, the count of the clock signal CK is counted. Start. The purpose is to temporarily synchronize the counter 27 at the first edge of the input signal. However, provisional synchronization may not be necessary depending on the application. The clock signal is eight times the input signal (=
3 bits), the counting cycle of the counter is 1
It matches the data cycle. Note that the counter 208 has a built-in decoder for generating an output signal corresponding to a specific count value.

An AND gate 205 serving as a synchronization shift detecting unit
Generates an out-of-synchronization detection signal when an edge signal is detected when the counter 208 has a predetermined value (for example, “2” or “6”). The counter 208 forcibly sets the count value to a predetermined value, for example, 5 in response to the synchronization shift detection signal, and corrects the count value of the counter 208. D-FF 209 which is an output buffer (latch circuit)
Sample (latch) the input signal when the counter 208 has a predetermined value (for example, “1” and “5”). In other periods, the latched data is held.

FIG. 4 is a waveform chart showing the operation timing of the main part of the embodiment of FIG. The received data (FIG. 4B), which is an input signal, includes a preamble section and a significant data section, and includes signal delay and noise. In the section A, the first rising edge is detected, and the start signal (FIG. 4D) is output from the D-FF 207. Based on this output, the counter 208 starts counting from the initial value “4”. Note that the rising edge of the received data (FIG. 4B) is delayed. In section B, since the count value has reached 5, the received data is sampled and D
-The output of the FF 209 changes (FIG. 4H). However, the first sampling output is meaningless as output data because the sampling phase may be shifted from the original.

In the section C, the second edge signal is detected. Since the count value at this time is "2", the synchronization error detection signal (output of the AND gate 205) becomes "1". The value of the counter 208 is changed to a predetermined value “5” (FIG. 4G). This operation resynchronizes the output phase of the counter 208 with the received data.

From section D onward, when the count value is "1" or "5", the received data is sampled and DF
The output of F209 changes. For example, the count value of the received data is “2”, “3”,
Many occurrences occur in portions corresponding to “6”, “7”, etc., and “1”
Alternatively, the position of "5" has the most stable data state, so that erroneous detection is reduced.

Although the embodiments of the present invention have been disclosed above, the present invention may have the following modifications. In the embodiment, an example in which a 3-bit counter is used is disclosed, but the number of bits (and a multiple of the clock signal) of the counter is arbitrary. In addition, the range of the count value for determining that the synchronization is lost when an edge signal is generated, that is, the configuration of the decoder of the counter 208 input to the AND gate 205 and the configuration of the decoder that generates the signal for sampling the received data are also arbitrary. Can be set to

When the configuration of the data synchronizing circuit 2 according to the embodiment of the present invention is adopted, based on the first edge signal among the edge signals detected by the edge detecting section composed of the D-FFs 202 and 203 and the AND gate 204. , OR gate 20
6. Since the start detection unit including the D-FF 207 generates a start signal and starts the operation of the 3-bit counter 208 by the start signal, rough data synchronization is achieved in the initial period of the input signal. In the entire data sequence of the subsequent input signal, the phase of the edge of the data is monitored by the count value for detecting the data synchronization deviation generated from the 3-bit counter 208, and the sampling phase of the input signal in the D-FF 209 is changed according to the monitoring result. As a result, the data synchronization state is always ensured, and jitter, glitch, noise, etc. are removed from the input signal containing jitter, glitch, noise, etc. without using a complicated circuit such as PLL, and the waveform is shaped. Completed data can be reproduced.

The data synchronizing circuit 2 according to the embodiment of the present invention having such a configuration, when a signal having a data structure composed of a preamble portion and significant data is supplied as an input signal, roughly synchronizes data in the preamble portion. Thereafter, since the data synchronization state is always ensured in the significant data portion, it is optimal for data synchronization of RF-ID transmission data, and can also be applied to data synchronization in a general data transmission system.

The RF-equipped with the data synchronization circuit 1 of the present invention
FIG. 5 shows the configuration of ID5. FIG. 5 shows only the receiving system. A feature of the RF-ID 5 in FIG. 5 is that a data synchronization unit 506 is provided between a demodulation unit 504 composed of an analog circuit and a digital signal processing unit 508 composed of a digital circuit. The data synchronization unit 506 corresponds to the synchronization data circuit 1 already described and shown in FIG.

In FIG. 5, reference numeral 501 denotes a receiving element including a loop coil for receiving a carrier signal spatially transmitted from a reader / writer. Reference numeral 502 denotes a power generation unit that generates power for each circuit inside the RF-ID from the received carrier signal. A clock generation unit 503 generates a clock signal from the received carrier signal.

Reference numeral 504 denotes a demodulation unit for demodulating transmission data as shown in FIG. 7 included in the received carrier signal. The demodulation output signal 505 of the demodulation unit 504 is a binary logic digital signal such as communication control data between the reader / writer and the RF-ID, control data of the RF-ID itself, or user data. The demodulation output signal 505 includes disturbance noise to the carrier signal on the transmission path, fluctuations in the power generated by the power generation unit 502, temperature characteristics of the semiconductor constituting the demodulation unit 504, or transients in the digital signal processing unit 508. Jitter, glitch,
It contains noise and the like.

Reference numeral 506 denotes a data synchronizing section for synchronizing the waveform of the demodulated output signal 505 of the demodulating section 504 containing jitter, glitch, noise and the like. The data synchronizing unit 506 has the same configuration as the data synchronizing circuit 1 shown in FIG. 1 described above, and includes the following units.

An edge detector for detecting an edge (either a rising edge or a falling edge) of the demodulation output signal 505 and outputting an edge signal. A start detection unit that detects an edge signal that is output first among edge signals output from the edge detection unit, and generates a start signal that starts a counting operation of the counter based on the detected first edge signal. When the count value of the counter is the second predetermined value, it is detected whether or not an edge of the demodulated output signal 505 exists during a period of sampling the demodulated output signal 505 based on the edge signal. A synchronization error detection unit that outputs a synchronization error detection signal assuming that the synchronization has occurred. A clock signal having a cycle of 1 / N (N is an integer) of a change cycle of the demodulation output signal 505 is counted to generate a cyclic count value,
A sampling pulse of the demodulated output signal 505 is generated at a first predetermined value among these count values, and data synchronization is performed at a second predetermined value that is one count later than the first predetermined value among the count values. A counter that generates a detection pulse for detecting a shift. A latch circuit that latches a demodulation output signal 505 by a sampling pulse and outputs the latched signal as an output signal 507 with data synchronization.

The specific configuration of the data synchronization section 504 is the same as that of the data synchronization circuit 2 of the embodiment shown in FIG. 3 already described. Data synchronization unit 506
Is the same as the operation of the data synchronization circuit 1 described with reference to FIG. 1. If no synchronization error detection signal is generated, that is, if no edge of the demodulation output signal 505 exists during the sampling period, the counter circulates. As a result, the sampling pulse of the input signal and the edge detection pulse are also kept generated at a constant phase. If an edge exists in the sampling period, a synchronization error detection signal is generated in a synchronization error detection period one count later than the sampling period, and the counter is forcibly preset to a predetermined count value by the synchronization error detection signal. Thereafter, the counter repeats the cycle with the preset count value as an initial value and continues counting.

As described above, the phase of the sampling pulse is shifted in accordance with whether or not the edge of the demodulation output signal 505 exists during the sampling period. Sampling (latching) the signal portion of
The output signal 507 of the latch circuit is synchronized with the clock signal, and jitter, glitch, and noise existing in a range other than the sampling period are eliminated.

A reference numeral 508 designates a decoder / decoder which decodes and decodes significant data of the output signal 507 which has been subjected to waveform shaping by the data synchronization section 506 and which has been subjected to data synchronization, and decodes the data based on the decoding result.
It is a digital signal processing unit that performs processing in response to a request from a writer. The digital signal processing unit 508 writes or reads out data necessary for judgment processing, arithmetic processing, or these processings to / from the memory 512 via the memory write / read bus 510 according to the result of the decoding. Perform processing and the like. Further, depending on the result of the decoding, a transmission process for encoding and preparing the transmission data format as shown in FIG. 7 described above in order to transmit data obtained as a result of the judgment process, the arithmetic process or the memory process to the reader / writer is also performed. . Reference numeral 509 denotes a memory control signal including a write address, a read address, a memory enable signal, and the like for memory processing.

The RF-ID 5 described above is an RF-ID
The carrier signal received by the receiving element 501 of the
4, demodulated output signal 505, disturbance noise on the transmission path, power fluctuations in power generation section 502, demodulation section 5
Even if jitter, glitch, noise, and the like are included due to the influence of the temperature characteristic of the data signal 04 or the transient in the digital signal processing unit 508, the data synchronization unit 506
In the above, the start detection unit generates a start signal based on the first edge signal of the edge signals detected by the edge detection unit, and starts the counting operation of the counter by this start signal. Rough data synchronization is achieved in an initial period corresponding to the preamble portion, and further, in the entire data sequence corresponding to significant data of the demodulated output signal 505, the count value for detecting data synchronization shift generated from the counter is used. The phase of the data edge is monitored, and the sampling result of the demodulated output signal 505 in the latch circuit is changed according to the monitoring result, whereby the data synchronization state is always ensured.

Therefore, in RF-ID5, P
Complete data that has been subjected to waveform shaping by removing jitter, glitches, noise, and the like without using a complicated circuit such as LL is supplied to the digital signal processing unit 508. Such an RF-ID 5 has a demodulated output signal 50 due to fluctuations in the power generated by the received carrier signal.
5 includes jitter, glitches or noise, a signal whose waveform has been shaped by the data synchronization unit 506 and whose data has been synchronized is supplied to the digital signal processing unit 606, so that decoding and decoding by the digital signal processing unit 606 are performed. Error does not occur in the result of.

In the RF-ID 5, the demodulated signal output 505 has a jitter,
Even when glitches or noises are included, complete data whose waveform has been shaped and data synchronized by the data synchronization unit 506 is supplied to the digital signal processing unit 606, so that decoding and decoding by the digital signal processing unit 606 can be performed. There is no error in the result.

In RF-ID5, RF-I
The demodulation unit 504, which is an analog circuit system, and the digital circuit system, even if any one of the three factors “external noise”, “offset drift”, and “power supply fluctuation” that make communication of D unstable becomes negative. Digital signal processing unit 5
08, the data synchronization unit 506 provided
Jitter, glitch or noise is removed from the signal transmitted from analog circuit to digital circuit.
Vicious cycle due to the synergistic effect of "external noise", "offset drift" and "power supply fluctuation", that is, [● generation of jitter and glitch → ● digital circuit system (digital signal processing unit 606)
Malfunction → ● Transient occurs in digital circuit →→
Even if power supply fluctuation of the power generation unit 602 → ● malfunction of the analog circuit system (demodulation unit 604) → ● generation of jitter and glitch] is likely to occur, the analog circuit system and the digital circuit system are cut off and a vicious cycle occurs. Can be suppressed.

The RF-ID 5 has three factors "external noise", "offset drift" and "power supply" which cause the above-described vicious cycle by providing the data synchronization section 506 between the analog circuit system and the digital circuit system. Since the tolerance of at least “external noise” and “power supply fluctuation” of the “fluctuation” is improved, the “maximum communication distance” that is the most important item of the RF-ID performance index can be improved.

The RF-ID 5 does not cause the above-described vicious cycle by providing the data synchronization unit 506 between the analog circuit system and the digital circuit system, so that the RF-ID 5 communicates with the transmission side (reader / writer). The phase relationship with the side (RF-ID5) is hardly influenced by the communication conditions, and even in the case of the RF-ID of the system in which the data is synchronized by the clock signal directly generated from the received carrier signal, the synchronization relationship between the transmission and reception is determined. Can be better established.

In the RF-ID 5, the demodulation unit 5
04, a data synchronization unit 506 performs rough data synchronization in an initial period corresponding to the preamble portion of the demodulation output signal 505, and further, a data sequence corresponding to significant data of the subsequent demodulation output signal 505. As a whole, the detection of the out-of-synchronization is monitored, and the demodulated output signal 505 is detected.
Since the sampling phase is corrected so that the edge of does not enter the sampling period and the data synchronization state is always ensured, molding errors do not frequently occur even when the communication conditions are severe.

[0057]

According to the present invention, there is provided a data synchronizer for shaping a waveform by synchronizing an input signal composed of a digital signal with a predetermined clock signal, wherein the edge detection means detects an edge of the input signal and outputs an edge signal. Start detection means for detecting an edge signal output first when the input signal is input, and generating a start signal when the edge signal is detected,
According to the start signal, the minimum period of the input signal is 1
/ N (where N is an integer) starts counting clock signals to generate count values, and generates a first timing signal at a first predetermined value among these count values;
In the second predetermined value of the count values, the second
A counter for setting the count value to a value by which the phase of the first timing signal shifts upon receiving a preset signal, sampling the input signal in accordance with the first timing signal, Sampling means for outputting a sampled signal as an output signal synchronized with the data, monitoring the position where the edge signal exists according to the second timing signal, and determining the position where the edge signal exists according to the first signal; Since the apparatus is provided with the preset signal generating means for outputting the preset signal during the period of the timing signal or the period near the first timing signal,

The start detecting means generates a start signal based on the first edge signal among the edge signals detected by the edge detecting means, and starts the operation of the counter by the start signal. The data synchronization is roughly achieved during the period of, and the phase of the edge of the data is monitored by the count value for detecting the data synchronization deviation generated from the counter in the entire data sequence of the subsequent input signal, and the input is performed according to the monitoring result. Since the sampling phase of the signal is changed, the data synchronization state is always ensured, and the jitter, glitch, noise, etc. can be obtained from the input signal containing jitter, glitch, noise, etc. without using a complicated circuit such as PLL. The removed and waveform-shaped data can be reproduced.

Further, in the data synchronizer of the present invention, the counter is a cyclic counter for generating a cyclic count value, whereby the count value of the input signal is calculated every period corresponding to a half cycle of the minimum cycle of the input signal. Since the first predetermined value and the second predetermined value are generated, the counter has a simple configuration as necessary.

In the data synchronizer according to the present invention, the cyclic counter cyclically counts in a period corresponding to a minimum cycle of the input signal, and counts one count of a first predetermined value among the count values. Since the second predetermined value is generated later, the number of counts of the counter can be minimized, and the configuration of the counter can be reduced in size.

In the data synchronizer according to the present invention, the cyclic counter sets the count value to the first predetermined value among the count values upon receiving the preset signal. When it is considered that a shift occurs, the sampling phase can be changed immediately, data synchronization with a fast response can be performed, the count number of the counter can be minimized, and the configuration of the counter can be reduced in size.

Furthermore, the present invention relates to a data synchronization method for shaping a waveform by synchronizing an input signal composed of a digital signal with a predetermined clock signal, wherein an edge of the input signal is detected and an edge signal is output. A detecting step, of the edge signals, detecting an edge signal that is output first when the input signal is input, and detecting a start signal when the edge signal is detected. The count of a clock signal having a cycle of 1 / N (N is an integer) of the minimum cycle of the input signal is started to generate a count value, and a first timing signal is generated at a first predetermined value among these count values. A counting step of generating a second timing signal at a second predetermined value of the count values; A sampling step of sampling the input signal according to the first timing signal and outputting the sampled signal as a data-synchronized output signal; and determining a position where the edge signal exists according to the second timing signal. A preset signal generating step of outputting the preset signal when the position where the edge signal is present is a period of the first timing signal or a period near the first timing signal; By providing a count value setting step of setting the count value of the counter to a value at which the phase of the first timing signal shifts,

The start detecting means generates a start signal based on the first edge signal among the edge signals detected by the edge detecting means, and the operation of the counter is started by this start signal. The data synchronization is roughly achieved during the period of, and the phase of the edge of the data is monitored by the count value for detecting the data synchronization deviation generated from the counter in the entire data sequence of the subsequent input signal, and the input is performed according to the monitoring result. Since the sampling phase of the signal is changed, the data synchronization state is always ensured, and the jitter, glitch, noise, etc. can be obtained from the input signal containing jitter, glitch, noise, etc. without using a complicated circuit such as PLL. It is possible to reproduce the complete data whose waveform has been removed and shaped.

Further, according to the present invention, a modulated signal spatially transmitted from a data transmitting apparatus and modulated by a data signal is received, and power is generated from the received modulated signal by a built-in power generating means. A clock signal is generated from the received modulated signal by the clock generation means, and a signal processing operation is activated by a power supply generated by the power generation section, and digital signal processing is performed using the clock signal generated by the clock generation means. And
In the non-contact IC card configured to obtain the data signal from the received modulation signal and perform predetermined data processing according to the data signal, the power generated by the power generation unit is supplied. Demodulating means for demodulating the data signal from the modulated signal and outputting the data signal; supplying power generated by the power generating section; supplying an output signal of the demodulating means; and outputting the output of the demodulating means by the clock signal. A signal is sampled and output during a predetermined sampling period, and when the edge of the output signal of the demodulation unit is in the sampling period or a period near the sampling period, the sampling phase is changed to thereby output the signal of the demodulation unit. Data synchronization means for performing data synchronization for the power supply unit when the power generated by the power generation unit is supplied. Output signal of the data synchronization means is supplied, the output signal of the data synchronization means is decoded using the clock signal, and digital signal processing means for performing predetermined data processing according to the decoding result is provided. By having done,

The demodulated output signal obtained by demodulation by the demodulation means includes:
Disturbance noise on the transmission path, power fluctuations in the power generation means,
Even if jitter, glitches, noise, etc. are included due to the influence of temperature characteristics of the demodulation means or transients in the digital signal processing means, the data synchronizing means does not perform the demodulation output signal in the initial period of the demodulation output signal. Rough data synchronization is achieved, and furthermore, the phase of the edge is monitored in the entire data sequence of the demodulated output signal,
Since the sampling phase of the demodulated output signal is changed according to the monitoring result, the data synchronization state is always ensured.

Therefore, in the non-contact IC card of the present invention, the data whose waveform has been removed by removing jitter, glitch, noise, etc. without using a complicated circuit such as PLL is supplied to the digital signal processing means, The malfunction of the signal processing means is reduced. As a result, "external noise" which is a problem in non-contact IC card communication
A vicious circle caused by a synergistic effect of “offset drift” and “power supply fluctuation” can be suppressed.

In the non-contact IC card according to the present invention, the data synchronization means detects an edge of an output signal of the demodulation means and outputs an edge signal. Start detection means for detecting an edge signal output first when an output signal of the demodulation means is input, and generating a start signal when the edge signal is detected; a minimum period of an output signal of the demodulation means by the start signal Count of a clock signal having a cycle of 1 / N (N is an integer) of the count value is generated, a first timing signal is generated at a first predetermined value of the count values, and Generating a second timing signal at a second predetermined value of the values, and receiving the preset signal to change the count value to the first timing signal; A counter for setting a phase shift value; a sampling means for sampling an output signal of the demodulation means in accordance with the first timing signal; and outputting the sampled signal as a data-synchronized output signal; Monitoring the position where the edge signal exists in response to the second timing signal, and determining that the position where the edge signal exists is a period of the first timing signal or a period near the first timing signal. By providing a preset signal generating means for outputting a signal,

The start detecting means generates a start signal based on the first edge signal among the edge signals detected by the edge detecting means, and starts the operation of the counter by the start signal. Rough data synchronization is achieved in the initial period corresponding to the preamble portion, and the phase of the data edge is monitored with the count value for detecting data synchronization deviation generated from the counter in the entire data string of the following significant data. Since the sampling phase of the demodulated output signal is changed according to the monitoring result, the data synchronization state is always secured, and a highly reliable signal obtained by removing jitter, glitch, noise, etc. from the demodulated output signal is sent to the digital signal processing means. And the malfunction of the digital signal processing means can be reduced. Since the malfunction of the digital signal processing means is reduced, the power supply fluctuation of the power generation means due to the transient is reduced.

In the contactless IC card according to the present invention, the counter is a cyclic counter for generating a cyclic count value, and the count value is calculated every period corresponding to a half cycle of the minimum cycle of the output signal of the demodulation means. Since the first predetermined value and the second predetermined value are generated, the count number of the counter can be minimized, the configuration of the counter can be reduced in size, and the circuit configuration suitable for IC integration It can be. In addition, since the circuit configuration is reduced in size, the power generated by the power generation means can be reduced, and power fluctuation of the power generation means can be reduced.

In the contactless IC card according to the present invention, the cyclic counter cyclically counts in a period corresponding to a minimum cycle of the output signal of the demodulation means, and counts the first predetermined value of the count values. After one count of the second
Since the predetermined value is generated, the count number of the counter can be minimized, and the configuration of the counter can be reduced in size. In addition, since the circuit configuration is reduced in size, the power generated by the power generation means can be reduced, and power fluctuation of the power generation means can be reduced.

In the contactless IC card according to the present invention, the cyclic counter sets the count value to the first predetermined value among the count values upon receiving the preset signal. When it is considered that a data synchronization deviation occurs, the sampling phase can be changed immediately, data synchronization with a fast response can be performed, the count number of the counter can be minimized, and the configuration of the counter can be reduced in size. In addition, since the circuit configuration is reduced in size, the power generated by the power generation means can be reduced, and power fluctuation of the power generation means can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data synchronizer of the present invention.

FIG. 2 is a waveform chart showing an operation of the data synchronizer of the present invention.

FIG. 3 is a circuit diagram showing a data synchronizer according to an embodiment of the present invention.

FIG. 4 is a waveform chart showing an operation of the data synchronizer according to the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a non-contact IC card of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional RF-ID.

FIG. 7 is a diagram illustrating an example of the structure of transmission data for interrogating an RF-ID reader / writer and RF-ID;

[Explanation of symbols]

101: Edge detection unit, 102: Start detection unit, 10
3: Synchronous shift detection unit, 104: counter, 105: latch circuit, 201, 202, 203, 207, 209 ... D
-FF, 204, 205 ... AND gate, 206 ... OR
Gate, 208: 3-bit counter, 501: receiving element, 502: power generation unit, 503: clock generation unit, 5
04 demodulation unit, 506 data synchronization unit, 508 digital signal processing unit, 512 memory

Claims (10)

[Claims] 1. A data synchronizer for shaping a waveform by synchronizing an input signal composed of a digital signal with a predetermined clock signal, edge detecting means for detecting an edge of the input signal and outputting an edge signal, A start detecting means for detecting an edge signal output first when the input signal is input, and generating a start signal when the edge signal is detected; and a minimum period of the input signal by the start signal. Of 1
/ N (where N is an integer) starts counting clock signals to generate count values, and generates a first timing signal at a first predetermined value among these count values;
In the second predetermined value of the count values, the second
A counter for setting the count value to a value by which the phase of the first timing signal shifts when a preset signal is received; and sampling the input signal in accordance with the first timing signal; Sampling means for outputting the sampled signal as an output signal synchronized with data; monitoring a position where the edge signal exists according to the second timing signal; A preset signal generating means for outputting the preset signal in a period of one timing signal or a period in the vicinity of the first timing signal. A data synchronizer that shapes the waveform by synchronizing. 2. The method according to claim 1, wherein the counter is a cyclic counter that generates a cyclic count value, and wherein the first of the count values corresponds to a period corresponding to a half cycle of a minimum cycle of the input signal.
2. The data synchronization apparatus according to claim 1, wherein the predetermined value and the second predetermined value are generated. 3. The cyclic counter cyclically counts during a period corresponding to a minimum cycle of the input signal, and the second counter counts one count of a first predetermined value among the count values.
3. The data synchronization apparatus according to claim 2, wherein a predetermined value is generated. 4. The cyclic counter, when receiving the preset signal, counts a count value of a first of the count values.
The data synchronization apparatus according to claim 3, wherein the data synchronization apparatus is set to a predetermined value. 5. A data synchronizer for shaping a waveform by synchronizing an input signal composed of a digital signal with a predetermined clock signal, comprising: an edge detection step of detecting an edge of the input signal and outputting an edge signal; A start detection step of detecting an edge signal that is output first when the input signal is input, and generating a start signal when the edge signal is detected;
/ N (where N is an integer) starts counting clock signals to generate a count value, and generates a first timing signal at a predetermined first count value among the count values. Counting a second timing signal at a second predetermined value among the values; sampling the input signal according to the first timing signal; and using the sampled signal as a data-synchronized output signal Outputting a sampling step, monitoring a position where the edge signal is present according to the second timing signal, and determining whether the position where the edge signal is present is in the period of the first timing signal or in the vicinity of the first timing signal. A preset signal generating step of outputting the preset signal during the period of receiving the preset signal. That the data synchronization method characterized by comprising the count value setting step of setting a value of phase shift of the counter the first timing signal, the count value of. 6. A modulated signal modulated by a data signal, which is spatially transmitted from a data transmitting apparatus, is received, power is generated from the received modulated signal by a built-in power generating means, and the power is generated by a built-in clock generating means. A clock signal is generated from the received modulation signal, a signal processing operation is activated by a power supply generated by the power generation unit, and digital signal processing is performed using the clock signal generated by the clock generation unit. A non-contact IC card configured to obtain the data signal from the modulated signal and perform predetermined data processing according to the data signal, wherein the power generated by the power generation unit is supplied, Demodulating means for demodulating the data signal from the signal and outputting the demodulated signal;
The output signal of the demodulation means is supplied, and the output signal of the demodulation means is sampled and output in a predetermined sampling period by the clock signal, and the edge of the output signal of the demodulation means is in the sampling period or a period near the sampling period. When the sampling phase is changed, the data synchronization means for performing data synchronization on the output signal of the demodulation means, and the power generated by the power generation unit are supplied,
Digital signal processing means for receiving an output signal of the data synchronization means, decoding the output signal of the data synchronization means using the clock signal, and performing predetermined data processing in accordance with the result of the decoding. Characteristic non-contact I
C card. 7. The data synchronizing means detects edge of an output signal of the demodulation means and outputs an edge signal, and an output signal of the demodulation means among the edge signals is inputted. A start signal detecting means for detecting a first output edge signal and generating a start signal upon detecting the edge signal; 1 / N (N is an integer) of a minimum cycle of an output signal of the demodulation means by the start signal; ) Starts counting the clock signal of the period, generates a count value, generates a first timing signal at a first predetermined value of the count values, and generates a second predetermined signal of the count value. A second timing signal is generated at a value, and when a preset signal is received, the count value is set to a value at which the phase of the first timing signal is shifted. Sampling means for sampling an output signal of the demodulation means in accordance with the first timing signal, and outputting the sampled signal as an output signal with data synchronization; and sampling means for responding to the second timing signal. A preset signal for monitoring the position where the edge signal exists, and outputting the preset signal when the position where the edge signal exists is a period of the first timing signal or a period near the first timing signal. 7. The non-contact IC card according to claim 6, comprising a generation unit. 8. The counter according to claim 1, wherein the counter is a cyclic counter that generates a cyclic count value. The counter includes a first predetermined value of the count value and a period corresponding to a half cycle of a minimum cycle of an output signal of the demodulation means. The non-contact IC card according to claim 7, wherein the second predetermined value is generated. 9. The cyclic counter cyclically counts in a period corresponding to a minimum cycle of an output signal of the demodulating means,
The non-contact IC card according to claim 8, wherein the second predetermined value is generated one count after the first predetermined value among the count values. 10. The non-contact IC card according to claim 9, wherein the cyclic counter sets the count value to a first predetermined value among the count values when receiving the preset signal.