JP2000151567A - Method and device for synchronization detection and method and device for phase synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable highly precise detection of phase relation even when there is a fluctuation in a power source voltage or a temperature and a form of circuit is different by using storage contents of a virtual storage element selected out of a first and a second virtual storage elements based on the degree of phase difference measured in accordance with the storage contents of the second virtual storage element. SOLUTION: All of five latch data QA1 to QE1 are used when a phase decision circuit 31 decides whether or not a phase difference between a clock CK and delay data DD1 is large. In a proceed state, a synchronous state and a delay state to follow the decision, an optimal combination of latch data of either three of QA1, QC1 and QE1 or three of QB1 to QD1 is selected in decision of the phase relation and used for decision of the phase relation. By decreasing the number of fixed delay circuits and that of D-FFs by two, four fixed delay circuits 22 to 25 become virtual delay elements for virtually detecting a mutual phase relation or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization method and apparatus, for example, synchronizing a phase of a received data sequence with a system clock in a communication device on the receiving side by changing a propagation delay time of the received data sequence. This can be applied to cases.

The present invention also relates to a synchronization detecting method which can be used in such a phase synchronization method.

Further, the present invention relates to a synchronization detecting device which can be used in such a phase synchronization device.

[0004]

2. Description of the Related Art As a conventional bit phase synchronization circuit, there is one described in Japanese Patent Application Laid-Open No. 4-293332.
FIG. 2 shows the principle of this bit phase synchronization circuit.

In FIG. 2, input data ID supplied to an input terminal 10A of a bit phase synchronization circuit 10 is supplied to a variable delay circuit 11, and an input clock CK is supplied from a clock input terminal 10B.

The variable delay circuit 11 changes the internal state of the input data ID supplied to the input terminal D in response to the control signal CS supplied to the control terminal and gives a different delay to the input data ID. This is a circuit that can be transmitted from the terminal Q as delay data DD.

The delay data DD is supplied to two fixed delay circuits 12
And 13, a fixed delay time DT3 is added cumulatively, so that there are three delays.

That is, the delay data DD is phase-divided into A without delay, B with delay DT3, and C with delay 2 × DT3. A delay signal (delay data DD) having each of the delay times A to C is output to one of three D-type flip-flops (D-FF) 14 to 16 for data latch.
It is supplied to the (data) input terminal.

The time chart is as shown in FIG. 3, for example.

Since the additional constant delay time provided by the fixed delay circuits 12 and 13 is DT3, FIG.
The phase difference (delay time difference) between the delayed signals A and B is DT3, and the phase difference between B and C is also DT3. Each of the data series # 0, $ 1, $ 2, ... of the delay data DD is "H"
Alternatively, it represents 1-bit data of "L" and has a relationship as shown in the drawing, for example, with respect to the timing ET of the rising edge of one pulse of the clock CK.

All three D-FFs 14 to 16 operate synchronously in response to the rising edge of the input clock pulse CK, and transfer the data supplied to their own D input terminals to their Q inputs.
Output from the output terminal.

In order to distinguish the Q output terminals of the three D-FFs 14, 15, and 16, respectively, QA, QB, and QC are used, and ♯0 = “L” (“0”) and ♯1 = “H”.
(“1”), ♯2 = “L” (“0”), since QA to QC are all “H” in the state of FIG. 3, the phase determination circuit 17 determines the clock CK and the delay data DD. It detects that the phase relationship is in a synchronized state. In the synchronous state, the phase determination circuit 17 instructs the control circuit 18 to maintain the current delay time, and the control circuit 18 causes the variable delay circuit 11 to maintain the current internal state. Therefore, the variable delay time given by the variable delay circuit 11 to the input data ID is maintained.

In the signal advance state, the delay signals A to C
Assuming that the parallel movement is performed in the direction (left direction) by the same amount and the timing ET is fixed, only the latch data QA indicates ♯2, that is, “L”, and QB and QC indicate
1, that is, a state indicating "H", and the phase determination circuit 1
7 detects a signal advance state.

In other words, the latch data QB and QB
A state where C is the same and only QA is different from these is a signal advance state.

When a signal advance state is detected, the phase determination circuit 1
7 instructs the control circuit 18 to increase the delay time,
The control circuit 18 changes the internal state of the variable delay circuit 11 with the control signal CS, and gives a longer delay time to the input data ID.

Since the state opposite to the signal advance state is the signal delay state, the phase determination circuit 17 detects the signal delay state when only QC is different from QA and QB, and via the control circuit 18 Thus, the variable delay time given to the input data ID is reduced.

By repeating such an operation, the data sequence B in which the delay data DD is added with an intermediate additional delay time is synchronized with the clock CK, and the data sequence of the B is synchronized with the clock CK. As the synchronized data SD, the output terminal 1 of the bit phase synchronization circuit 10
Sent from 0C.

[0018]

By the way, in the above-described bit phase synchronization circuit 10, the phase difference DT3 of the delay signals A, B, C is, by its nature, one bit of the input data (received data sequence) ID. There is no point unless the time width is sufficiently shorter than the minute time width BW.

When DT3 reaches, for example, more than half of the time width BW, the total phase difference between the delay signal with the smallest delay and the delay signal with the largest delay,
That is, since the phase difference 2 × DT3 between A and C is almost equal to or longer than the time width BW for one bit, even if the clock CK and the delay data DD are synchronized, three The polarities of the latch data QA, QB, and QC do not match, and it becomes impossible to detect the synchronization state.

Therefore, the phase difference DT3 is equal to the input data I
It can be seen that the upper limit is specified for the data rate of D.

On the other hand, as a hardware necessity, the phase difference DT3 must be sufficiently long so that the D-FFs 14 to 16 can normally perform the data latch operation even when the signal is delayed.

Generally, a state storage element such as a D-FF is
A time margin is required for the storage operation. When the D-FF samples the data supplied to the D input terminal by the edge operation, the setup time TS is set before the edge operation timing (corresponding to the ET), and the hold time TH is set thereafter. At least during this time (TS + TH), the data state must be stably held. If the data is not stable during this time, the normality of the latch operation of the D-FF is not guaranteed, and the possibility of occurrence of a bit error increases.

In FIG. 3, in order to detect a signal advance or a signal delay, A0 to A1 and A0 to A1 (or A2)
In the vicinity of the polarity reversal point between 1 and 2), the D-FF 14 ~
16 must perform a normal latch operation. The DT3 determines the time interval between the polarity inversion points.

Setup time TS and hold time TH
Is the margin time (TS + TH) obtained by combining DT3
If the length is longer than the above, all three D-FFs 14 to 16 simultaneously have no timing at which the normal operation is guaranteed. This means that there is no timing at which the detection of the signal advance and the signal delay is guaranteed to be performed normally.

In FIG. 3, for example, when the above-described signal delay case occurs, rising edge ET of clock CK becomes {1} for A and B, and {} for C.
This is the timing corresponding to 0.

In this case, the margin time (TS + T
Assuming that H) is longer than DT3, at least in the delay signals B and C, ♯
The timing relationship has a polarity inversion point between 0 and # 1. Therefore, the D-FF 15 changes “H” of $ 1 to “H”.
Is not guaranteed to be normally latched as D-FF1
No. 6 is not guaranteed to normally latch by setting "L" of $ 0 to "L". As a result, normal detection of the signal delay is not guaranteed.

In order to prevent this from happening, the fixed delay circuits 12 and 13 of the bit phase synchronization circuit 10 are usually designed such that DT3 is sufficiently longer than the margin time (TS + TH).

However, lengthening DT3 means that it becomes difficult to handle input data IDs having a high data rate.

Setup time TS, hold time TH
Although it is conceivable to reduce the length, TS and TH have hardware limitations and other specifications of the D-FF are involved, so there is a certain limit.

When the bit phase synchronization circuit 10 operates,
If there is a change in the power supply voltage, temperature, or the like, the current drive capability of the fixed delay circuits 12, 13 formed of gate ICs (integrated circuits) also changes, so that the additional delay time DT3 becomes unstable and may change. There is. This variation depends on the type of the gate IC of the fixed delay circuits 12 and 13 and the CMOS (Compleme).
ntary MOS) or TTL (Transistor Transist
or Logic).

[0031]

According to a first aspect of the present invention, a plurality of predetermined delay times are provided to the same received data sequence to provide a phase difference.
For each of the delay times, the data in the received data sequence is stored at the same timing, and the stored contents corresponding to each of the delay times are compared, whereby the received data sequence and the clock are referenced with respect to the phase of the clock on the receiving side. (1) a first virtual delay element that virtually adds the plurality of predetermined delay times for detecting the mutual phase relationship, wherein: A first virtual delay time corresponding to the plurality of delay times is given to the sequence, and (2) the received data is obtained by using a second virtual delay element for virtually measuring the degree of the phase difference. (3) a first virtual storage element for storing the received data sequence corresponding to the first virtual delay time; and Virtual delay time Correspondingly, a second virtual storage element for storing the received data sequence is provided, and (4)
Using the storage content of the virtual storage element selected from the first and second virtual storage elements based on the degree of the phase difference measured according to the storage content of the second virtual storage element, The method is characterized in that a relationship is detected.

Further, in the second invention, a plurality of predetermined delay times are given to the same received data sequence so as to have a phase difference, and the data in the received data sequence is converted for each delay time. By storing at the same timing, by comparing the stored contents corresponding to each delay time, in a synchronization detection device that detects the mutual phase relationship between the received data sequence and the clock based on the phase of the clock on the receiving side,
(1) A first virtual delay element that virtually provides the plurality of predetermined delay times for detecting the mutual phase relationship, wherein the first virtual delay element corresponds to the plurality of delay times to the received data sequence. (2) Using a second virtual delay element for virtually measuring the degree of the phase difference, superimposing a second virtual delay time on the received data sequence. (3) a first virtual storage element for storing the received data sequence corresponding to the first virtual delay time, and storing the received data sequence corresponding to the second virtual delay time And (4) the first and second virtual storage elements based on the degree of the phase difference measured according to the storage content of the second virtual storage element. Using the storage contents of the virtual storage element selected from the above, And executes the detection of the phase relation.

In a third aspect of the present invention, there is provided a phase synchronization method for relatively synchronizing a received data sequence and a clock on a receiving side by using a digital synchronization loop.
The method is characterized by using any one of the synchronization detection methods of (1) to (3).

According to a fourth aspect of the present invention, there is provided a phase synchronization apparatus for relatively synchronizing a received data sequence and a clock on a receiving side by using a digital synchronization loop.
6. A synchronization detecting device according to any one of (1) to (6).

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Embodiment Hereinafter, a synchronization detection method and apparatus and a phase synchronization method and apparatus according to the present invention will be described in which N = 1 (N is a natural number),
That is, the embodiment will be described by taking the case of 2N + 3 = 5 as an example.

(A-1) Configuration of the First Embodiment FIG. 1 shows a bit phase synchronization circuit 20 of the present embodiment. Such a bit phase locked loop circuit 20 having a kind of DPLL (Digital Locked Loop) configuration can be used, for example, as a part of a receiving unit of a communication device.

In FIG. 1, input data (received data sequence) I is input from input terminal 20A of bit phase synchronization circuit 20.
D1 is supplied, and the input clock CK is supplied from the clock input terminal 20B. The clock CK may be exactly the same clock as the clock CK of the bit phase synchronization circuit 10 described above.

The variable delay circuit 11 for giving a variable delay time to the input data ID1 is a circuit for changing or maintaining the variable delay time according to the received control signal CS. The circuit may be exactly the same as the variable delay circuit 11.

Therefore, the delay data DD1 output from the variable delay circuit 11 is a data sequence obtained by adding the variable delay time to the input data ID1.

In order to add an additional delay time to the delay data DD1, the present embodiment is provided with four fixed delay circuits 22 to 25 connected in series.

As the fixed delay circuits 22 to 25, any circuit can be used as long as it can provide a predetermined fixed delay time to the delay data DD1. Shall be used.
The fixed delay time given by each of the fixed delay circuits 22 to 25 is D
Let it be T1.

The delay data DD1 has an additional delay time DT1.
Are divided into five delayed signals A1 to E1 in the order of the shortest delay time, including those in which delay time is not added.

The delay signal A1 without additional delay is directly supplied to the D (data) input terminal of the D-FF 26 after being transmitted by the variable delay circuit 11. The delay signal B1 provided with the delay time DT1 by the fixed delay circuit 22 is supplied to a D input terminal of the D-FF 27. Fixed delay circuits 22 and 23
C1 to which a delay time is given by DT1 in D-FF2
8 D input terminal. Fixed delay circuits 22 to 24
Thus, D1 provided with a total delay time of 3 × DT1 is D
-It is supplied to the D input terminal of FF29. Finally, E1 provided with a delay time of 4 × DT1 in all the fixed delay circuits 22 to 25 is supplied to the D input terminal of the D-FF 30.

That is, the same delay data DD1 is subjected to five kinds of delays.

The D-FFs 26 to 30, which have been supplied with the signals A1 to E1 at the D input terminals, respectively, supply the supplied data at, for example, the rising edge of the same clock pulse of the input clock CK supplied to the C (clock) input terminal. Latch each Q
Change the state of the output terminal.

In order to distinguish the Q output terminals of the D-FFs 26 to 30, the Q output terminal of the D-FF 26 is QA1, the Q output terminal of the D-FF 27 is QB1, and the D-F
The Q output terminal of F28 is QC1, the Q output terminal of D-FF29 is QD1, and the Q output terminal of D-FF30 is QE.
Let it be 1.

If only the mutual phase relationship between the delay data DD1 and the clock CK, that is, the signal advance state, the synchronization state, and the signal delay state is detected with reference to the phase of the clock CK, as in the conventional bit phase synchronization circuit 10, It is sufficient to prepare three types of QA to QC.

The five types of latch data QA1 to QE1 prepared in this embodiment are supplied to the phase determination circuit 31 by the clock CK.
In determining the magnitude of the phase difference between the delay data DD1 and the delay data DD1, all five patterns are used. In the determination of the phase relationship between the advance state, the synchronization state, and the delay state following the determination, QA
1, three of QC1, QE1, or three of QB1 to QD1
One of the two optimal latch data combinations is selected and used for determining the phase relationship.

As in the conventional bit phase synchronization circuit 10 described above, at least two fixed delay circuits and three D-FFs
Can detect the mutual phase relationship between the phase advance state, the synchronization state, and the phase delay state. In the present embodiment, the number of fixed delay circuits and D-FFs is increased by two, and [4] With the fixed delay circuit, 5D-FF] configuration, all of the four fixed delay circuits 22 to 25 also serve as virtual delay elements for virtually detecting the mutual phase relationship, and virtually the degree of the phase difference , And also a storage element for actually detecting the mutual phase relationship.

As described above, in the present embodiment, the same circuit and the same delay time have the dual function and the dual meaning because the fixed delay circuit for judging the magnitude of the phase difference is usually used. And a D-FF, and a separate fixed delay circuit and a D-FF for determining the phase relationship are provided separately from each other. This is to make an efficient circuit.

In this sense, QA1 to QA1 of the present embodiment are used.
QE1 is completely different from QA to QC in the conventional bit phase synchronization circuit 10 described above.

The phase determination circuit 31 receiving the supply of QA1 to QE1 includes fixed delay circuits 22 to 25 and a D-FF 26
30 is a circuit for executing the operation of giving meanings as described above.

Fixed delay circuits 22 to 25, D-FFs 26 to
A phase relation detection unit 32 that detects the phase relation between the clock CK and the input data ID1 is configured by the part 30 and the part that performs the above functions in the phase determination circuit 31.

In addition to the above functions, the phase determination circuit 31 having the function of always selecting the C1 having an intermediate delay time as the synchronization data SD1 and transmitting it from the output terminal 20C.
Is the clock C according to the storage contents of the D-FFs 26 to 30.
The phase relationship between K and the delay data DD1 (that is, the input data ID1) is detected, and an instruction is given to the control circuit 18 based on the detection result.

The control circuit 18 is a circuit that changes or maintains the internal state of the variable delay circuit 11 by outputting a control signal CS1 based on an instruction from the phase determination circuit 31.

The control circuit 18 may be the same circuit as the control circuit 18 of the bit phase synchronization circuit 10.

Hereinafter, the operation of the first embodiment having the above configuration will be described. (A-2) Operation of First Embodiment First, the input data ID1 is given a variable delay time by the variable delay circuit 11, and becomes the delay data DD1.

Next, this delay data DD1 is applied to four fixed delay circuits 2 each of which applies a fixed delay time DT1.
The signals are phase-divided into five delay signals A1 to E1 in a delay time range of 0 to 4 × DT1 and a variation width DT1 by 2 to 25.

Each of the delay signals A1 to E1 is latched by D-FFs 26 to 30 which operate synchronously based on the clock CK, and is simultaneously supplied to the phase determination circuit 31 as QA1 to QE1.

DT1 is a time width BW of one bit of the input data ID1 according to the data rate of the input data ID1.
1 (FIG. 4), and D-FFs 26-3
This is set to be sufficiently longer than a margin time (TS + TH) obtained by adding the setup time TS and the hold time TH of 0.

However, DT1 changes even when the bit phase synchronization circuit 20 operates, if there is a change in power supply voltage, temperature, or the like.

DT1 is shortened by fluctuations in the power supply voltage, etc.
The D-FF2 not only becomes shorter than the margin time but also approaches the same value as the margin time.
The risk that data latch by 6 to 30 cannot be performed normally increases.

When the fluctuating DT1 approaches the same value but larger than the margin time, the delay signals A1 to E1 are stochastically set in the signal advance state or the signal delay state.
Is more likely to be within the margin time, and the possibility that the data latch operation of the D-FFs 26 to 30 cannot be performed normally increases.

When the bit phase synchronization circuit 20 operates, the input data ID1 and the clock CK are constantly synchronized with each other over a long period of time, so that the synchronization state is shown in FIG.

In FIG. 4, each of the data series of the delay data DD1 # 0, # 1, # 2,... Represents 1-bit data of "H" or "L" as in the case of FIG.

♯0 = “L” (“0”), ♯1 =
Assuming that “H” (“1”) and ♯2 = “L” (“0”), the polarity inversion points between the ♯0 and ♯1 of the delay signal A1 are AP1, A1
AP2 is the polarity inversion point between # 1 and # 2 of
The point of polarity inversion between # 1 and # 1 is BP1, and the point of polarity inversion between # 1 and # 2 of B1 is BP2. Similarly, the polarity inversion points CP1, CP2, DP1, DP2, EP
1. Determine EP2.

In the state shown in FIG. 4, since all of QA1 to QE1 are at "H", phase determination circuit 31
1 is detected as a small phase difference small state.

When the small phase difference state is detected, the phase determination circuit 31 determines the phase difference from the latch data QA1 to QE1 in order to reduce the risk that the data latch cannot be performed properly in the signal advance state or the signal delay state. Are selected, that is, the optimal latch data QA1, QC1, and QE1. Based on these, the clock CK and the input data ID1 are selected.
Is detected. A1 and C1 have a phase difference of 2 × DT1, and C1 and E1 also have a phase difference of 2 × DT1.

Optimum latch data QA1, QC1, QE
By selecting 1, the possibility that not only the synchronization state but also all the phase relationships can be normally detected increases.
That is, it is more likely that a signal advance state and a signal delay state can be normally detected.

Here, the detection of the magnitude of the phase difference and the detection of the phase relationship need not always be performed at the same frequency. This is because conditions such as the power supply voltage and the temperature that affect the value of DT1 generally have a much slower variation speed than the data rate of the input data ID1.

For example, if the phase relationship is detected at the rising edge of all clock pulses, the magnitude of the phase difference may be detected once every several hundred clock pulses, or the frequency can be set from outside. You may. The detection result of the magnitude of the phase difference once obtained is held until the next magnitude detection is performed, and during that period, for example, the selection of the optimal latch data QA1, QC1, and QE1 is continued.

The selected latch data QA1, QC1,
The detection of the phase relationship based on QE1 is performed using the clock pulse CK.
Is performed in accordance with the timing relationship between the rising edge ET and the polarity inversion point of the selected latch data.

For example, in the signal delay state, the polarity inversion point A
P1 and CP1 are to the left of ET, polarity inversion point EP1 is ET
, The polarities of QA1 and QC1 are both “H” (♯1), and only the polarity of QE1 is “L”.
(♯0).

Since the optimum latch data QA1, QC1, and QE1 having a large phase difference of 2 × DT1 are selected, the polarity inversion point AP which is a problem within the margin time is set.
1, CP1 and QE1 are less likely to be located, and more accurate data latching can be performed, thereby lowering the bit error rate and improving the reliability of the phase determination circuit 31 in detecting the phase relationship.

The control corresponding to the detected phase relationship is exactly the same as that of the conventional bit phase synchronization circuit 10, and the phase determination circuit 31 changes the variable delay time given by the variable delay circuit 11 via the control circuit 18, or It is performed by maintaining.

For example, when a signal delay state is detected, the variable delay circuit 11 is controlled so as to shorten the current variable delay time.

In other cases, for example, when a synchronization state is detected, the phase determination circuit 31 instructs the control circuit 18 to maintain the current delay time, and the control circuit 18 outputs the variable delay circuit 11 as in the conventional case. To keep the current internal state.

However, in the present embodiment in which the accuracy of the data latch and the accuracy of the phase relationship detection are improved, the ratio of the period during which the bit phase is synchronized is higher than that of the conventional bit phase synchronization circuit 10, and the reliability is improved. Is high.

In FIG. 5 showing a synchronization state different from that in FIG. 4, since the phase difference DT1 is large, the rising edge timing ET of the clock CK corresponds to A2 in A1.
("L"), $ 1 ("H") for B1 to D1, and $ 0 ("L") for E1.

Three latch data QB1 to QB in the middle part
Since only D1 has the same polarity “H”, the phase determination circuit 31 can detect that the state in FIG. 4 is a state with a large phase difference.

In the state where the phase difference is large, the possibility that the polarity inversion point of the latch data falls within the margin time range is originally low. However, if QA1 or QE1 having a large phase difference of the corresponding delay signal is selected, Since the total phase difference 4 × DT1 between the delay signal A1 with a small delay and the delay signal E1 with the longest delay is about the same as or greater than the time width BW1 for one bit, the synchronization state is synchronized. There is a problem that it cannot be detected as a state.

Therefore, when the phase determination circuit 31 detects a large phase difference, the phase determination circuit 31 selects one of QA1 to QE1 from QB1 to QD1.
One of the three is selected, and only these three are used for detecting the phase relationship.

If the detection of the magnitude of the phase difference and the detection of the phase relation are performed at the same frequency, as described above, the magnitude of the phase difference is detected first, and then the phase relation is detected. As such, there is no need to have two steps.
If all five of QA1 to QE1 have the same polarity, it is immediately recognized as a small phase difference synchronization state, and if only QB1 to QD1 have the same polarity, it is immediately recognized as a large phase difference synchronization state.

In the above description, the magnitude of the phase difference is determined in the synchronized state. However, the magnitude of the phase difference can be detected without the synchronized state.

For example, in the case of a signal delay state with a small phase difference,
In FIG. 4, ET is fixed, and A1 to E1 are signal delay directions DY.
And A1 to D1 are equal to 1 ("H").
Therefore, only E1 having the largest delay becomes ♯0 (“L”), so that the phase determination circuit 31 can detect a signal delay state with a small phase difference. In the signal advance state, the only difference is that only A1 with the least delay shows a different polarity.

Similarly, in the case of a signal delay state with a large phase difference, ET is fixed and A1 to E1 are translated in the signal delay direction DY by the same amount in FIG. At this time, B1 and C
1 indicates the same polarity “H” at ♯1. With reference to the QC1 corresponding to the delay signal C1 having just an intermediate delay, the QC
If only QB1 shows the same polarity as 1, it can be recognized as a signal delay state with a large phase difference, and if only QD1, it can be recognized as a signal advance state with a large phase difference.

That is, in the present embodiment, the phase determination circuit 31 always selects three latch data having an optimum phase difference from the five latch data QA1 to QE1, and determines the phase relationship based on the selected latch data. Can be detected.

(A-3) Effects of the First Embodiment As described above, according to the present embodiment, even if the power supply voltage fluctuates and the temperature fluctuates, even if the IC type such as CMOS or TTL is different. Since the detection of the phase relationship can always be automatically performed with the latch data having the optimum phase difference, the inconvenience due to the too short phase difference of the latch data used for detecting the phase relationship and the inconvenience due to the too long phase difference. Are eliminated, and highly accurate phase relationship detection and highly reliable bit phase synchronization can be performed.

The characteristics of the present embodiment are, as viewed from the other side, the relationship between the data rate of the input data ID1 and the delay time DT1 given by each of the fixed delay circuits 22 to 25, and the margin of the D-FFs 26 to 30. Meaning that the relationship between time and DT1 does not have to be designed so strictly,
Assuming the same specifications, it is possible to use a signal having a wide range of data rates, such as a signal having a data rate faster than that of the conventional input data ID, as input data ID1, and to increase the degree of freedom in circuit design.

(B) Second Embodiment Hereinafter, the synchronization detection method and apparatus and the phase synchronization method and apparatus according to the present invention will be described with N = 1 (N is a natural number),
That is, the second embodiment will be described with an example of 2N + 3 = 5.

The first embodiment adds an additional delay time DT1 to the input data ID1, whereas the embodiment adds an additional delay time to the clock CK.

(B-1) Configuration and Operation of the Second Embodiment FIG. 6 shows a bit phase synchronization circuit 40 according to this embodiment. Such a bit phase synchronization circuit 40, which is a kind of DPLL, can be used, for example, as a part of a receiving unit of a communication device, similarly to the bit phase synchronization circuit 20 of the first embodiment.

In FIG. 6, the parts denoted by reference numerals 11 and 18 are the same as the parts denoted by the same reference numerals in FIG.
The signals to which CK, CS, and DD1 are attached are the same as the signals with the same reference numerals in FIG. 1, and a detailed description thereof will be omitted.

In FIG. 6, fixed delay circuits 42 to
45 corresponds to the fixed delay circuits 22 to 25, and is a D-FF.
46 to 50 correspond to the D-FFs 26 to 30, the phase determination circuit 51 corresponds to the phase determination circuit 31, the phase relationship detection unit 52 corresponds to the phase relationship detection unit 32, and the input terminal 40A is connected to the input terminal 40A. It corresponds to the terminal 20A, the clock input terminal 40B corresponds to the clock input terminal 20B, and the output terminal 40C corresponds to the output terminal 20C.

However, in FIG. 6, the clock CK is not the delayed data DD1 but the five delayed signals A2 to E2.
The fixed delay circuits 42 to 45
Is used.

If the delay time given by each of the fixed delay circuits 42 to 45 is DT1, the delay signal E2 has no delay and D
2 is DT1 delay, C2 is 2 × DT1 delay, B2 is 3
The delay of × DT1 and A2 have a delay of 4 × DT1. The delay signals A2 to E2 have five D-FFs 46 to
It is supplied to 50 C input terminals.

The D input terminals of the D-FFs 46 to 50 have the delay data DD1 sent from the variable delay circuit 11 connected thereto.
Is supplied as is.

Therefore, the Q output terminals QA2 to QE2 of the D-FFs 46 to 50 change as shown in the time chart of FIG.

FIG. 7 corresponds to the synchronous state with a small phase difference referred to in the first embodiment.

In FIG. 7, the timing of the rising edge of the clock pulse of delay signal A2 is ET1, the timing of the rising edge of the clock pulse of delay signal B2 is ET2, and the timing of the rising edge of the clock pulse of delay signal C2 is ET3. And the timing of the rising edge of the clock pulse of the delay signal D2 is ET4
ET5 is the timing of the rising edge of the clock pulse of the delay signal E2.

Between ET1 and ET2, between ET2 and ET3,
The phase difference between T3 and ET4 and between ET4 and ET5 is DT1.

Then, D at C2 with just an intermediate delay
Q obtained by latching delayed data DD1 by FF 48
C2 is transmitted from the output terminal 40C as data SD2 synchronized with the clock CK.

The phase of the input data ID1 and the phase of the clock CK are relative to each other. The first embodiment in which an additional delay time is added to the delay data DD1 and the additional delay time in the clock CK are added. It is considered that there is no substantial difference in operation between the provided embodiments.

In at least the present embodiment, as in the first embodiment, the magnitude of the phase difference can be detected, the phase relationship can be detected, and the output data SD synchronized with the clock CK can be detected.
2 can be sent out constantly.

However, since the configuration is different, the operation and effect cannot be exactly the same. For example, depending on the internal configuration of the variable delay circuit 11 such as when the variable delay circuit 11 uses a CR, the delay data DD1 In this case, there is a possibility that the waveform is rounded. In this case, as in the first embodiment, the waveform is delayed by A1 supplied to the D-FF 26 without delay and by the fixed delay circuit (gate IC) 22 or the like. In addition, there is a possibility that a variation in phase difference other than DT1 occurs between B1 and the like supplied to the D-FF 27 and the like.

On the other hand, since the input clock CK is a signal originally generated and used in the communication device,
Usually, there is no problematic distortion or dullness in the waveform. Therefore, the fixed delay circuit (gate I
C) The clock CK is supplied from the D-FF 46 to
It is considered that there is a low possibility that a variation occurs between the timing supplied to the D-FF 50 and the timing supplied to the D-FF 50.

(B-2) Effects of the Second Embodiment According to the present embodiment, the same effects as those of the first embodiment can be realized with different configurations.

(C) Other Embodiments In the above description, the gate I in which fixed delay circuits are connected in series has been described.
Although the configuration is made by C, any configuration having a function of giving a plurality of delay times to the same data series may be used. For example, a passive element such as a delay line using L and C is used. Is also good.

When a passive element is used, it is considered that a gate IC provided at an output section in the preceding variable delay circuit 11 drives the passive element. As a result, the fixed delay time DT1 may also fluctuate. This driving capability also varies depending on the type of the gate IC.

In the configuration of the first embodiment, the variable delay circuit 11 on the input terminal 20A side is connected to the clock input terminal 2
It may be arranged on the 0B side to add a variable delay time to the clock CK. In this case, no variable delay time is given to the input data ID1.

Further, in the configuration of the second embodiment, the variable delay circuit 11 on the input terminal 40A side may be arranged on the clock input terminal 40B side so that a variable delay time is given to the clock CK. Also in this case, the input data ID
No variable delay time is given to 1.

In the first and second embodiments, the phase determination circuit automatically selects the optimal latch data. However, the operation of such a phase determination circuit is performed from outside the bit phase synchronization circuit. An input terminal which can be controlled may be provided in the phase determination circuit so that the phase-divided delay data or clock can be arbitrarily selected from outside.

In the first and second embodiments, N = 1, but N ≧ 2, that is, six or more fixed delay circuits,
A delay signal having seven or more D-FFs and having seven or more delay times may be handled.

In the first and second embodiments, N
= 1, that is, 2N + 3 = 5, all the latch data QA1 to QE1 (QA2 to QE2) are used for detecting the magnitude of the phase difference and for detecting the phase relationship. In the case of ≧ 2, there may be latch data used only for detecting either the magnitude of the phase difference (generally measuring the magnitude of the phase difference) or detecting the phase relationship.

Further, in the above description, the description has been made using the hardware circuit configuration. However, software performing the same operation may be used.

That is, according to the present invention, a plurality of predetermined delay times are added to the same received data sequence, and the data in the received data sequence is stored at the same timing for each of the delay times. By comparing stored contents corresponding to time, when detecting the mutual phase relationship between the received data sequence and the clock on the basis of the phase of the clock on the receiving side, and on the basis of the phase of the received data sequence, the clock The present invention can be widely applied to a synchronization detection method and apparatus, and a phase synchronization method and apparatus when detecting a mutual phase relationship between data and a received data sequence.

[0117]

As described above, according to the present invention, the first and second virtual storage elements are determined based on the degree of the phase difference measured according to the storage content of the second virtual storage element. Among them, the optimal virtual storage element can be selected, and therefore, by detecting the mutual phase relationship using the stored contents of the optimal virtual storage element, even if there is a fluctuation in power supply voltage or temperature, Even if the form of an IC or discrete circuit such as CMOS or TTL is different, highly accurate detection of the phase relationship can always be performed, and highly reliable bit phase synchronization can be achieved.

On the other hand, according to the present invention, the relationship between the data rate of the received data sequence and the first and second virtual delay times, and the first and second virtual delay times and the first and second virtual storages The relationship with the element characteristics does not need to be designed so strictly. Given the same specifications, it is possible to handle received data sequences with a wider range of data rates, such as those that are faster than conventional ones. , And in designing a phase synchronization system.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of a bit phase synchronization circuit according to a first embodiment.

FIG. 2 is a schematic diagram showing a configuration of a conventional bit phase synchronization circuit.

FIG. 3 is a time chart showing an operation of a conventional bit phase synchronization circuit.

FIG. 4 is a time chart illustrating an operation of the bit phase synchronization circuit according to the first embodiment.

FIG. 5 is a time chart illustrating an operation of the bit phase synchronization circuit according to the first embodiment.

FIG. 6 is a schematic diagram illustrating a configuration of a bit phase synchronization circuit according to a second embodiment.

FIG. 7 is a time chart illustrating an operation of the bit phase synchronization circuit according to the second embodiment.

[Explanation of symbols]

10, 20, 40: bit phase synchronization circuit, 11: variable delay circuit, 12, 13, 22 to 25, 42 to 45: fixed delay circuit, 17, 31, 51: phase determination circuit, 14 to 1
6, 26-30, 46-50 D-FF, 18 control circuit, 32, 52 phase relation detector, ID1 input data, DD1 delay data, CS control signal, CK clock, SD, SD1 , SD2 ... synchronous data, A to C, A
1 to E1, A2 to E2... Delayed signals.

Claims (8)

[Claims] A plurality of predetermined delay times are given to the same received data sequence to provide a phase difference, and the data in the received data sequence is stored at the same timing for each of the delay times. A synchronization detection method for detecting the mutual phase relationship between the received data sequence and the clock based on the phase of the clock on the receiving side by comparing the stored contents corresponding to the respective delay times, wherein the mutual phase relationship is virtually determined. A first virtual delay element for providing the plurality of predetermined delay times for detecting the delay time, providing a first virtual delay time corresponding to the plurality of delay times to the received data sequence, Using a second virtual delay element for measuring the degree of the phase difference, a second virtual delay time is superimposed on the received data sequence, and the second virtual delay element is provided in correspondence with the first virtual delay time. Said A first virtual storage element for storing the received data sequence and a second virtual storage element for storing the received data sequence corresponding to the second virtual delay time are provided. The detection of the mutual phase relationship is performed by using the storage content of the virtual storage element selected from the first and second virtual storage elements based on the degree of the phase difference measured according to the storage content of the storage element. A synchronization detection method, which is performed. 2. The synchronization detection method according to claim 1, wherein the mutual phase relationship includes a phase lead state, a synchronization state,
The three types of phase delay states are detected.
Is detected as a natural number in N stages, and a small state is also detected in N stages. As the first and second virtual delay times, a total of 2N +
Three kinds of the delay time are prepared, and a total of 2N +
Three storage elements are prepared, and three virtual elements selected from the 2N + 3 virtual storage elements based on the degree of the phase difference measured according to the storage content of the second virtual storage element. A synchronization detection method, wherein the mutual phase relationship is detected by using storage contents of a storage element. 3. The synchronization detection method according to claim 1, wherein a mutual phase relationship between the clock and the received data sequence is detected with reference to a phase of the received data sequence. 4. A method in which a plurality of predetermined delay times are given to the same received data sequence to have a phase difference, and the data in the received data sequence is stored at the same timing for each of the delay times. In a synchronization detecting device for detecting the mutual phase relationship between the received data sequence and the clock with reference to the phase of the clock on the receiving side by comparing the stored contents corresponding to the respective delay times, A first virtual delay element for providing the plurality of predetermined delay times for detecting the delay time, providing a first virtual delay time corresponding to the plurality of delay times to the received data sequence, Using a second virtual delay element for measuring the degree of the phase difference, a second virtual delay time is superimposed on the received data sequence, and the second virtual delay element is provided in correspondence with the first virtual delay time. Said A first virtual storage element for storing the received data sequence and a second virtual storage element for storing the received data sequence corresponding to the second virtual delay time are provided. The detection of the mutual phase relationship is performed by using the storage content of the virtual storage element selected from the first and second virtual storage elements based on the degree of the phase difference measured according to the storage content of the storage element. A synchronization detection device, which is executed. 5. The synchronization detection device according to claim 4, wherein the mutual phase relationship includes a phase lead state, a synchronization state,
The three types of phase delay states are detected.
Is detected as a natural number in N stages, and a small state is also detected in N stages. As the first and second virtual delay times, a total of 2N +
Three kinds of the delay time are prepared, and a total of 2N +
Three storage elements are prepared, and three virtual storage elements selected from the 2N + 3 virtual storage elements based on the degree of phase difference measured according to the storage content of the second virtual storage element A synchronous detection device, wherein the mutual phase relationship is detected by using stored contents of elements. 6. The synchronization detection device according to claim 4, wherein a mutual phase relationship between the clock and the reception data sequence is detected with reference to a phase of the reception data sequence. 7. A phase synchronization method for relatively synchronizing a received data sequence and a clock on a receiving side by using a digital synchronization loop, wherein the synchronization detection method according to claim 1 is used. Phase synchronization method. 8. A phase synchronization device for relatively synchronizing a received data sequence and a clock on a receiving side by using a digital synchronization loop, wherein the synchronization detection device according to claim 4 is used. Phase synchronizer.