JP2000148706A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To access an equipment to be accessed such as a memory, and an IO needed for a processor although the constitution is relatively simple. SOLUTION: This system is provided with CPUs 1 and 2, IO cards 7 and 8 that the CPUs 1 and 2 access, and ID issue parts 11 and 12 which send the IDs of the processors out when the IO cards 7 and 8 are accessed corresponding to the CPUs 1 and 2. An arrival ID is compared with the IDs set previously corresponding to the IO cards 7 and 8, and when they are matched with each other, an ID recognizing process part 13 or 14 allows the corresponding CPU to access the IO card 7 or 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, a multiprocessor system is configured as shown in FIG. CPU bus 50
0, CPUs 501 and 502, memories 503 and 50
4. The IO bus controller 505 is connected. I
The O bus controller 505 is also connected to the IO bus 506. IO cards 507 and 508 on which IO devices are mounted are connected to the IO bus 506.

In the system shown in FIG.
For example, as shown in FIG. 14, the address spaces 01 and 502 include memories 503 and 504 and an IO card 50.
7, 508 are assigned, and the CPU 501,
502 performs memory access and IO access. In the system, the multiprocessor OS
Are the memories 503 and 50 by the CPUs 501 and 502.
4. Access control to the IO cards 507 and 508 is performed. For example, the multiprocessor OS allows the CPU 507 to access the IO card 508 at a certain point in time, and the CPU 502
8 is controlled. Therefore, CPU5
01 and 502 could not independently perform memory access or IO access with the multiprocessor OS.

In the system shown in FIG. 13, a common resource such as a memory or an IO is individually assigned to each CPU, and a configuration called a multicomputer or a multidomain for executing independent OSs and programs is used. To make it possible, a system using a bus switching circuit 510 as shown in FIG. 15 has been considered. In the system shown in FIG.
The bus switching circuit 510 is provided between the I / O bus 512 and the I / O buses 513 and 514, and the path of the bus switching circuit 510 is set by the control logic circuit 520. Can be configured.

For example, as shown in FIG.
01 and the IO card 507 are connected, and the CPU 502 and the I / O card 507 are connected.
The bus switching circuit 51 is connected so that the O card 508 is connected.
By setting the route of 0, the configuration is such that the IO card 507 exists in the address space of the CPU 501 and the IO card 508 exists in the address space of the CPU 502.

Further, as shown in FIG.
By setting the path of the bus switching circuit 510 such that the I / O card 507 and the I / O card 507 and the I / O card 508 are connected, the I / O card 507 is placed in the address space of the CPU 501.
And the IO card 508 exist. Further, as shown in FIG.
By setting the path of the bus switching circuit 510 such that the I / O card 02 and the IO card 508 are connected,
In both the address space of the CPU 502 and the address space of the CPU 502.
The O card 508 can be configured to be present.

[0007]

However, according to the multiprocessor system having this configuration, the CPU bus,
When the number of IO buses and the like increases, there is a problem that the circuit scale of the bus switching circuit 510 becomes large and complicated. Also, CP
If the number of U buses, IO buses, and the like is fixed, there is a problem that the system cannot respond to the scale of the system.

The present invention has been made in order to solve the problems of the conventional multiprocessor system. The object of the present invention is to provide a processor having a relatively simple configuration and a processor independent of the multiprocessor OS. Is to provide a multiprocessor system capable of accessing an access target device such as a memory and an IO.

[0009]

According to a first aspect of the present invention, there is provided a multiprocessor system comprising: a plurality of multiprocessors; a device accessible by the plurality of processors;
Identification information sending means provided in the multiprocessor for sending identification information specifying the processor to the device; identification information holding means provided in the device for holding the identification information; and an access request from the processor Receiving the access request, comparing the identification information added to the access request with the identification information held in the identification information holding means, and permitting access when they match. And As a result, the processor can access a predetermined device using the identification information, and the device existing in the address space of each processor can be changed without control by the multiprocessor OS.

[0010] In a multiprocessor system according to a second aspect of the present invention, the device is an input / output card. As a result, the IOs existing in the address space of each processor are not controlled by the multiprocessor OS.
You can change the card.

[0011] In a multiprocessor system according to a third aspect of the present invention, the equipment is a memory. Thereby, the multiprocessor O
The memory existing in the address space of each processor can be changed without control by S and without changing the IO device.

In a multiprocessor system according to a fourth aspect of the present invention, a plurality of multiprocessors, a device accessible by the plurality of processors, and a processor provided in the multiprocessor and accessing the device when accessing the device. Packet sending means for sending a packet containing identification information and address and data to be specified; identification information holding means provided in the device for holding identification information; identification information contained in a packet coming from a processor side; Packet control means for comparing the identification information held in the information holding means and controlling the packet so as to permit access to the device by the address and data included in the packet when the identification information matches the identification information; It is characterized by. As a result, the processor can access a predetermined device using the packet, and the device existing in the address space of each processor can be changed without control by the multiprocessor OS.

[0013] In the multiprocessor system according to the fifth aspect of the present invention, there is provided a packet capturing means for capturing a packet including identification information of the own processor corresponding to the plurality of processors, and the packet control means accesses the device. The data obtained as a result is set in a packet having identification information of the corresponding processor, and is transferred to a bus of the processor. Thereby, it becomes possible for the processor to receive the result of accessing a predetermined device using the packet.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiprocessor system according to the present invention will be described below with reference to the accompanying drawings. In the respective drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 shows a first embodiment. For CPU bus 100, CPU1,
2, the memories 3, 4 and the IO bus controller 5 are connected. The IO bus controller 5 is also connected to the IO bus 6. IO cards 7 and 8 on which an IO device is mounted are connected to the IO bus 6 via an IO connector 300.

The CPUs 1 and 2 are provided with ID issuing units 11 and 12 as identification information sending means. The ID issuing units 11 and 12 are used when accessing a memory or an IO.
The ID (identification information) set in advance is stored in the CPU bus 100
Send to

The IO cards 7 and 8 are provided with ID recognition processing units 13 and 14 as access control means.
The D recognition processing units 13 and 14 compare the identification information set in advance with the identification information of the incoming processor, and when they match, permit the processor to access the IO card as the target device by the processor.

FIG. 2 shows the detailed configuration of the IO cards 7 and 8. Each of the IO cards 7 and 8 includes an IO control circuit 21, an address decoder 22, a comparator 23, and an ID designation register 24. Here, the address decoder 22, the comparator 23, and the ID designation register 24 correspond to the ID recognition processing unit 13.
Constituting (14). A data line D extends from the IO connector 300 to the IO control circuit 21, an address line A and a data line C extend from the IO connector 300 to the address decoder 22, and an IO connector 3 to the comparator 23.
A line 25 for sending an ID extends from 00, and a line 26 for setting an ID from the IO connector 300 extends to the ID designation register 24. Address decoder 22
To the IO control circuit 21 via the line SEL. The set ID is sent from the ID designation register 24 to the comparator 23.

In the multiprocessor system configured as described above, the operation is performed as follows. First, the ID designation register 2 of each of the IO cards 7 and 8
4 is set to the ID. This setting is, for example, O
S can be performed, or can be set by firmware. Further, a switch is provided on a board or the like of the IO card 7, 8 or an external switch is provided,
An ID can also be set in the D designation register 24.

As shown in FIG. 3, for example, as shown in FIG. 3, the ID set to “0” is unused and the ID set to “1” is identification information for permitting the use of the CPU 1.
Is “2” as identification information that allows the use of the CPU 2.
The ID issuing unit 11 of the CPU 1 sends out the ID “1”, and the ID issuing unit 12 of the CPU 2 sends out the ID “2”.

For example, the ID recognition processing unit 1 of the IO card 7
3 in the ID designation register 24 in the
It is assumed that “2” is set as the ID in the ID designation register 24 in the ID recognition processing unit 14 of the O card 8.
In such a case, the CPU 1 sends out the ID (“1”) to access, so that the IO bus controllers 5 and I
In the ID recognition processing unit 13 of the IO card 7 via the O bus 300, the ID is sent to the comparator 23 through the line 25.
“1” is sent out, and comparison with the ID set in the ID designation register 24 is performed.

Here, the ID designation register 24 stores the ID
Since “1” is set, the comparison result of the comparator 23 becomes coincident, and an enable signal is output to the address decoder 22. The address decoder 22 receiving the enable signal decodes an address coming from the line A,
When the address matches the address of the IO card 7, a selection signal is supplied to the IO control circuit 21 via the line SEL, and data is taken out from the IO control circuit 21 via the line D, or Data can be written via the line D.

On the other hand, the ID recognition processing unit 14 of the IO card 8
, The ID is sent to the comparator 23 through the line 25.
“1” is sent out and compared with the ID set in the ID designation register 24.
Is set to the ID "2", the comparison result of the comparator 23 becomes inconsistent, the enable signal is not supplied to the address decoder 22, and the access to the IO card 8 becomes impossible.

Further, since the CPU 2 sends the ID "2", the CPU 2 can access the IO card 8 and cannot access the IO card 7. Then, at an appropriate time, the ID set in the ID register 24 of each of the IO cards 7 and 8 is set.
By changing D, processing equivalent to the path change between the two CPUs 1 and 2 and the IO cards 7 and 8 is performed, and a multi-domain system can be flexibly configured in one system. Of course, the same ID can be set in the ID cards 7 and 8.

FIG. 4 shows a multiprocessor system according to a modification of the first embodiment. In this system, ID recognition processing units 17 and 18 are provided in IO slots 15 and 16 provided between the IO bus 6 and the IO connector 300. Each of the IO cards 7 and 8 has an ID
No recognition processing unit is provided.

FIG. 5 shows the detailed configuration of the ID recognition processing section 17 (18). ID recognition processing unit 17 (1
8) includes an address decoder 22, a comparator 23, and an ID designation register 24. IO card 7 (8)
Is provided with an IO control circuit 21. The line D reaches the IO control circuit 21 via the IO slot 15 (16) and the IO connector 300, and the output of the address decoder 22 is transmitted via the line SEL to the IO controller 300 via the IO connector 300.
The O control circuit 21 has been reached.

In the multiprocessor system having such a configuration, similarly to the multiprocessor system shown in FIG. 1, by changing the ID value as shown in FIG. CPUs 1, 2
A process equivalent to the path change between the I / O card and the IO card 7 (8) is performed, and a multi-domain system can be flexibly configured in one system.

FIG. 6 shows a second modification of the system of FIG. In this modification, ID recognition processing units 27 and 28 are provided in the memories 3 and 4 instead of the IO cards 7 and 8 in the embodiment shown in FIGS. As shown in detail in FIG. 7, the memory 3 (4) includes a memory unit 30 to which data is written and an ID recognition processing unit 27.
(28) is provided. In the ID recognition processing unit 27 (28),
As shown in FIG. 7, an address decoder 31, a comparator 32, and an ID designation register 33 are provided.

Further, as shown in FIG.
, An address line A and a data line C extend via a data line D and an address decoder 31.
A line 34 for sending an ID from the CPUs 1 and 2 extends to the comparator 32, and a line 35 for setting the ID extends to the ID designation register 3. An address line A and a control line C extend to the address decoder 31. The set ID is sent from the ID designation register 33 to the comparator 32.

Also in this system, for example, one of the IDs shown in FIG. 3 is set in the ID designation register 33 in advance. When the ID “1” is set in the ID designation register 33 and the ID (“1”) is transmitted from the CPU 1, the ID arriving at the comparator 32 matches, so that it is enabled for the address decoder 31. A signal is provided. The address decoder 31 decodes the address of the address line A, and supplies a control signal of the control line C to the memory unit 30 as a read / write signal to read or write data.
If the ID supplied to the comparator 32 does not match the ID output from the ID designation register 33, no active enable signal is supplied to the address decoder 31 and data is read from the memory unit 30. There is no transition to a state where writing is possible.

In such a system as well, by setting a required ID in the ID designation register 33, processing equivalent to a path change between the two CPUs 1 and 2 and the memories 3 and 4 is performed, and the system is flexible in one system. A multi-domain system can be configured.

Next, a second embodiment will be described. This embodiment is configured as shown in FIG. CP
A CPU port 110 is connected to the U bus 100, and an IO port 120 is connected to the IO bus 6 to which the IO cards 7 and 8 as target devices are connected. A packet control circuit 40 is provided between the CPU port 110 and the IO port 120.

The packet control circuit 40 includes an access table 41, a packet dividing unit 42, and a packet assembling unit 43.
Is provided. The access table 41 has an ID
Corresponding to the address and the address, information indicating an address in a packet transmitted from the CPUs 1 and 2 and information indicating a target device to which data is to be transmitted are stored. Using the information in the access table 41, the packet division unit 42 sends a selection signal to the corresponding target device via the line SEL, and sends out an address and data, or fetches data by giving an address. Make it possible. Packet assembler 43
Receives the data output from the IO cards 7 and 8 when the packet division unit 42 gives an address and allows the data to be fetched, and transmits the packets transmitted from the CPUs 1 and 2 which the packet division unit 42 has already received. ID within
Is added to the packet and transmitted to the CPU bus 100.

In the multiprocessor system configured as described above, the access table 41 is
In order to set a required combination between U1, 2 and IO cards 7, 8, CPUs 1, 2,
The address in the packet sent from the server and information indicating the target device to which the data is sent are stored. This storage can be performed by a method similar to the method of setting the ID in the ID designation register described above.

The CPUs 1 and 2 transmit packets as shown in FIG. 9 to the CPU bus 100 in order to access the IO cards 7 and 8. Here, the identification information ID, data, and address of the CPUs 1 and 2 already described are set in the packet. When the CPUs 1 and 2 read data, no data is set. CPUs 1 and 2
No address is set for the packet containing the data read by the.

Then, for example, the CPU 1
When the packet is transmitted to the PU bus 100 (packet transmitting means), the packet dividing unit 42 receives the packet, extracts the ID and address, and uses the information in the access table 41 to send the line to one of the corresponding IO cards 7 and 8. A selection signal is transmitted via the SEL, and an address and data are transmitted so that data writing is performed.

A packet containing no data is sent to the CPU
When it is detected that the data is to be read out, a selection signal is sent via the line SEL to give an address so that the data can be taken in. The packet assembling unit 43, when the packet dividing unit 42 gives an address and makes it possible to take in data, the IO card 7, 8
From the CPUs 1 and 2, which have already been received by the packet dividing unit 42, are packetized by adding the IDs.
Send to

By changing the information in the access table 41 also by such a multiprocessor system,
Processing equivalent to the path change between the two CPUs 1 and 2 and the IO cards 7 and 8 is performed, and a multi-domain system can be flexibly configured in one system. A memory may be provided instead of the IO cards 7 and 8, and a memory may be provided in addition to the IO card.

FIG. 10 shows a third example of the system shown in FIG.
Is shown. In this multiprocessor system, CPUs 1 and 1A are connected to a first group GR1.
And the ID issuing units 11 and 11A have the same I
D (first identification information). The CPUs 2, 2A, and 2B are included in a second group GR2, and the respective ID issuing units 12, 12A, and 12B transmit the same ID (identification information different from the first identification information). .

Each CPU of the first group GR1 has an ID
Since "1" is transmitted, the ID
The IO card 7 set to “1” can be accessed,
The IO card 8 with the ID “2” set in the D designation register 24 cannot be accessed. Conversely, the second group G
Since each CPU of R2 sends out the ID “2”, the IO card 8 can be accessed and the IO card 7 cannot be accessed. Then, the load monitoring device 50 receives the processed instruction from each CPU, and shifts the CPU of the group having the small processing instruction amount to the above group when the instruction amount processed in a certain group exceeds a predetermined amount. The ID issuing unit is controlled so that the CPUs of the two groups operate under an appropriate load.

Each CPU in each group constitutes a multiprocessor system by a multiprocessor OS. In general, a group having a large number of CPUs is associated with an IO or a memory having a large processing capacity. Further, by applying the configuration of the above modified example to the multiprocessor system according to the second embodiment shown in FIG. 8, a plurality of CPUs connected to the IO port are grouped, and the CPUs forming each group are When a packet including the same ID is transmitted, and conversely, when reading result data is transmitted to the CPUs in each group, data is set in the packet including the ID and transmitted to the CPU bus. To Also in this configuration, each CPU in each group configures a multiprocessor system with a multiprocessor OS, so that the CPU that has read can receive the packet.

FIG. 11 shows a fourth modification of the system shown in FIG. In this system, the CPU bus 10
0 is connected to a spare CPU 61 and a failure detection circuit 62, and the IO bus 6 is connected to a spare IO card 63. A predetermined ID different from those of the other IO cards 7 and 8 is set in the ID register 24 of the ID recognition processing unit 73 provided in the spare IO card 63.

The I provided in the spare CPU 61
FIG. 12 shows the configuration of the D issuing unit 71. The ID issuing section 71 is provided with ID set registers 72 to 74 and a selection circuit 76 for passing any one of the outputs of the ID set registers 72 to 74 with a selection signal coming from a line 75. The ID when the spare CPU 61 is in a spare state where the spare CPU 61 is not used is stored in the ID set register 72.
(For example, “0”) is set in the ID set register 73 when the CPU 1
The ID (for example, “1”) used by 1 is set, and the ID (for example, “2”) used by the spare CPU 61 at the time of the failure of the CPU 2 is set in the ID set register 74.

The failure detection circuit 62 makes an inquiry to the CPUs 1 and 2 during operation via the CPU bus 100 to monitor and detect a failure based on the presence or absence of a response. Card 7,
Inquiry during operation is made to 8, and a failure is monitored and detected based on the presence or absence of a response. The failure detection circuit 62 performs control such that the ID set register 73 is selected via the line 75 of the standby CPU 61 when the CPU 1 detects that the CPU 1 has a failure. Is controlled so that the ID set register 74 is selected via the line 75 of the above.

Further, the failure detection circuit 62
When the CPU detects that the IO card 8 is faulty, it notifies the corresponding CPU of the ID set in the ID designation register 24 of the spare IO card 63. The ID set in the ID designation register 24 of the IO card 63 is notified. The notified CPU uses the ID related to the notification to perform IO
To access.

As described above, even when the CPU or the IO card fails, the switching is appropriately performed, and the operation is continued without the system going down. The spare IO card 6
The operation of the system may be started without first setting the ID in the ID register 24 of the ID recognition processing unit 73 provided in 3. In this case, the failure detection circuit 62
When detecting that the IO card 7 has failed, the ID set in the IO card 7 is set in the ID designation register 24 of the spare IO card 63, and when detecting that the IO card 8 has failed, Spare IO card 63
The ID set in the IO card 8 is set in the ID designation register 24 of the. As a result, the CPU
The operation can be performed without changing D.

The configuration of the above modification is applied to the multiprocessor system according to the second embodiment shown in FIG. 8 so as to appropriately switch even when the CPU or the IO card fails due to this configuration. Is performed, and the operation is continued without the system going down.

[0047]

As described above, according to the multiprocessor system of the first aspect, the identification information is added when the processor accesses, so that the retained identification information and the identification of the arriving processor are added. Compare information,
If they match, the processor is allowed to access the device, and the processor can access a predetermined device using the identification information. The address space of each processor can be controlled without control by the multiprocessor OS. Can be changed.

According to the multiprocessor system of the present invention, since the device has an IO card and the access control means is provided on the IO card, the address of each processor can be controlled without the control of the multiprocessor OS. You can change the IO card that exists in the space.

According to the multiprocessor system of the present invention, since the device is a memory and the access control means is provided in the memory, the address space of each processor can be stored in the address space of each processor without control by the multiprocessor OS. The existing memory can be changed.

According to the multiprocessor system of the present invention, when a packet including identification information is transmitted from the processor and the identification information included in the packet arriving from the processor matches the identification information. Since the packet is controlled so that the device related to the match is accessed by the address and data included in the packet, the processor can access the predetermined target device using the packet, and the multiprocessor OS The devices existing in the address space of each processor can be changed without the control by.

According to the multiprocessor system of the present invention, a plurality of processors take in a packet containing identification information of the own processor, and the data obtained as a result of accessing the device is replaced with the identification information of the corresponding processor. Since a configuration is provided in which a packet is set and transferred to the processor bus, the result of the processor accessing a predetermined device can be received using the packet.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of a main part of the first embodiment shown in FIG. 1;

FIG. 3 is a diagram showing an example of an ID used in the multiprocessor system of the present invention.

FIG. 4 is a configuration diagram showing a first modification of the first embodiment;

FIG. 5 is a configuration diagram showing details of a main part of a first modified example in FIG. 4;

FIG. 6 is a configuration diagram showing a second modification of the first embodiment.

FIG. 7 is a configuration diagram showing details of a main part of a second modified example in FIG. 6;

FIG. 8 is a block diagram showing a multiprocessor system according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a packet used in the second embodiment of the present invention.

FIG. 10 is a configuration diagram showing a third modification of the first embodiment.

FIG. 11 is a configuration diagram showing a fourth modification of the first embodiment.

FIG. 12 is a configuration diagram showing details of a main part of a second modified example in FIG. 11;

FIG. 13 is a configuration diagram of a multiprocessor system according to a conventional example.

FIG. 14 is a diagram showing a memory space realized by a conventional system.

FIG. 15 is a configuration diagram of a multiprocessor system according to another conventional example.

FIG. 16 shows a CPU and an I realized by a conventional system.
The figure which shows the connection relationship with O.

FIG. 17 shows a CPU and an I realized by the conventional system.
The figure which shows the connection relationship with O.

FIG. 18 shows a CPU and an I realized by the conventional system.
The figure which shows the connection relationship with O.

[Explanation of symbols]

1, 2 CPU 3, 4 Memory 5 IO bus controller 6 IO bus 7, 8 IO card 11, 12 I
D issuing unit 13, 14, 17, 18 IO recognition processing unit 15, 16 IO slot 22 address decoder 23 comparator 24 ID designation register

Continued on the front page (72) Inventor Yohei Kamiyama 1 Toshiba-cho, Fuchu-shi, Tokyo F-term in Fuchu factory, Toshiba Corporation (reference) 5B045 BB02 BB12 DD06

Claims (5)

[Claims] A plurality of multiprocessors; a device accessible by the plurality of processors; an identification information transmitting unit provided in the multiprocessor and transmitting identification information for specifying the processor to the device; An identification information holding unit provided in the device and holding the identification information; and upon receiving an access request from the processor, identification information added to the access request and identification information held by the identification information holding unit. And compare
A multi-processor system comprising: access control means for permitting access when they match. 2. The multiprocessor system according to claim 1, wherein said device is an input / output card. 3. The multiprocessor system according to claim 1, wherein said device is a memory. 4. A plurality of multiprocessors, a device accessible by the plurality of processors, and a packet provided in the multiprocessor and including identification information, an address, and data for identifying the processor when accessing the device. Packet sending means for sending; identification information holding means provided in the device for holding identification information; identification information included in a packet arriving from the processor side and identification information held in the identification information holding means. A multiprocessor system comprising: a packet control unit that controls a packet so as to permit access to a device by an address and data included in the packet when the packet is compared and matched. 5. A packet capturing means for capturing a packet including identification information of its own processor corresponding to a plurality of processors, wherein the packet control means transmits data obtained as a result of accessing the device to identification information of the corresponding processor. 5. The multiprocessor system according to claim 4, wherein the packet is set in a packet having the following and transferred to a processor bus.