JP2000114727A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low cost multilayer printed wiring board which does not show the lowering of an insulation resistance between plated through-holes which is caused by an HAST test, a steam test, etc., and the fluctuation of the resistance of a plated through-hole chain which is caused by a heat-cycle test. SOLUTION: A board 30 made of glass-epoxy which has a Tg point of not lower than 190 deg.C and an increased cross-linking density is used. By this constitution, it is avoided that metal such as copper, etc., of which plated through-holes 36 are made is ionized and transferred (migrates) between the through-holes and an insulation resistance between the plated through-holes are lowered by an HAST test, a steam test, etc. Further, the fluctuation of the resistance of a plated through-hole chain which is caused by breakage of a plated through- hole chain or the plated through-hole which is caused by the thermal expansion and contraction at the time of a heat-cycle test can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer resin insulation layer and a conductor circuit alternately laminated on a substrate having a through hole and a conductor circuit formed thereon, and the conductor circuits of different layers are connected to each other by an interlayer resin insulation layer. The present invention relates to a build-up multilayer printed wiring board electrically connected to via holes provided in a multi-layer printed wiring board.

[0002]

2. Description of the Related Art In recent years, build-up multilayer printed wiring boards have been receiving attention due to demands for higher density multilayers. This multilayer wiring board is a multilayer wiring board in which conductive circuits and interlayer resin layers are alternately laminated on a core substrate, and the conductive circuits of each layer are connected by via holes. As a core substrate of such a build-up multilayer wiring board, an FR-4 grade glass epoxy substrate has been conventionally used.

However, in such FR-4 grade glass epoxy substrates, the insulation resistance between plated through-holes decreases in a HAST test or a steam test, or the resistance of a plated through-hole chain decreases in a heat cycle test. The problem of a large change occurred. That is, the reliability after long-term use was low. In order to solve such a problem, a core substrate using a BT (bismaleimide-triazine) resin has been proposed, but it has been expensive.

[0004]

SUMMARY OF THE INVENTION The present inventors have proposed a method of reducing the insulation resistance between through-holes and using a low-cost resin such as an epoxy resin instead of a high-priced resin such as a BT resin. We considered whether it was possible to suppress the fluctuation of the resistance value of the conductor circuit that connects between them, and came to discover an unexpected fact that such a problem is caused by the Tg point of the resin. The present invention provides a low-cost multilayer printed wiring board in which the insulation resistance between through-holes is reduced by a HAST test or a steam test, and the resistance value of a conductor circuit connecting between the through-holes is changed by a heat cycle test. suggest.

[0005]

According to the present invention, an interlayer resin insulating layer and a conductor circuit are alternately laminated on a substrate provided with a through hole and a conductor circuit. In a build-up multilayer wiring board electrically connected by via holes provided in an insulating layer, the substrate is a glass epoxy substrate using an epoxy resin having a Tg point of 190 ° C. or higher. It is a wiring board.

The present inventors have conducted intensive studies and have found that HAST
The reason why the insulation resistance value between through holes decreases in a test or a steam test is that a metal such as copper constituting the through holes is ionized and moves (migrate) between the through holes, thereby lowering the insulation resistance value. I knew it was because of it.

It has also been found that the resistance value of the conductor circuit connecting between the through holes varies in the heat cycle test because the conductor circuit or the plated through hole breaks due to thermal expansion and contraction.

It has been found that in order to reduce migration and thermal expansion / shrinkage, the crosslinking density of the epoxy resin should be increased to increase the Tg point. If the Tg point of the epoxy resin is 190 ° C. or higher, these problems can be suppressed.
As a result, the metal such as copper constituting the plated through-holes is ionized and moves (migrate) between the through-holes, so that the insulation resistance between the plated through-holes does not decrease in a HAST test, a steam test, or the like. In addition, resistance fluctuation caused by breakage of the conductor circuit or the plated through hole due to thermal expansion and contraction in the heat cycle test is eliminated. Further, the epoxy resin is lower in cost than the BT resin.

When the Tg point is 190 ° C. or higher (DMA method (temperature rise:
An existing substrate developed for a mass lamination type multilayer wiring board can be used as the glass epoxy substrate at 2 ° C./min)). For example, Mitsubishi Gas Chemical HL830
(Tg point 217 ° C) HL830FC (Tg point 212
° C) Hitachi Chemical MCL-E-679LD (Tg
Point 205-215 ° C) MCL-E-679F (Tg
Point 205-217 ° C) Matsushita Electric Works R-5715 (Tg
Point 190 ° C.).

[0010] A hole is formed in such a glass epoxy substrate or this copper clad laminate by laser or drill, and a through hole is formed by metallizing the inner wall surface by electroplating, electroless plating, sputtering, vapor deposition or the like. I do. This through hole can be filled with a filler. Also,
The metalized through-hole inner wall may be roughened. As the filler, various materials such as those composed of bisphenol F type epoxy resin and inorganic particles such as silica and alumina, and those composed of metal particles and resin can be used.

[0011] A conductor circuit is provided on the through-hole forming substrate thus formed. The conductor circuit is formed by an etching process. The surface of the conductive circuit is desirably subjected to a roughening treatment for improving the adhesion. Next, an interlayer resin insulating layer is provided.

As the insulating resin, a thermosetting resin, a thermoplastic resin, or a composite resin thereof is used. As the thermosetting resin, an epoxy resin, a phenol resin, a polyimide resin, or the like is used. Further, as the thermoplastic resin, as the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyether imide (PI ), Fluorine resin and the like can be used.

In the present invention, the resin insulating layer may be an adhesive for electroless plating. For example, a heat-resistant resin that is hardly soluble in an acid or an oxidizing agent contains particles that can be dissolved by the acid or the oxidizing agent, and the particles are dissolved by the acid or the oxidizing agent to roughen the surface of the insulating resin layer. can do. Examples of such heat-resistant resin particles include amino resins (melamine resins, urea resins,
Heat-resistant resin particles such as a guanamine resin), an epoxy resin (a bisphenol-type epoxy resin cured with an amine-based curing agent is optimal), and a bismaleimide-triazine resin can be used.

Further, such an adhesive for electroless plating includes:
In particular, hardened heat-resistant resin particles, inorganic particles, fibrous fillers, and the like can be included as necessary. Such heat-resistant resin particles include (1) heat-resistant resin powder having an average particle size of 10 μm or less, (2) aggregated particles obtained by aggregating heat-resistant resin powder having an average particle size of 2 μm or less, (3) average particle size. Is 2-10μ
a mixture of a heat-resistant resin powder having an average particle diameter of 2 μm or less and a mixture of a heat-resistant resin powder having an average particle diameter of 2 μm or less and (4) a heat-resistant resin powder having an average particle diameter of 2 μm or less. Pseudo particles having at least one of a resin powder and an inorganic powder adhered thereto, (5) a heat-resistant resin powder having an average particle diameter of more than 0.8 and less than 2.0 μm and a heat-resistant resin powder having an average particle diameter of 0.1 to 0.8 μm. It is preferable to use at least one kind of particles selected from the group consisting of a mixture and (6) a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because these particles form a more complicated roughened surface.

An opening can be formed in such an interlayer resin insulating layer by laser light, exposure, or development. Then
A catalyst for electroless plating such as a Pd catalyst is applied, the inside of the via hole opening is plated to provide a via hole, and a conductor circuit is provided on the surface of the insulating resin layer. An electroless plating film is formed on the inner wall of the opening and on the entire surface of the insulating resin layer. After a plating resist is provided, electroplating is performed, the plating resist is removed, and a conductive circuit is formed by etching.

[0016]

The present invention will be described below based on examples and comparative examples. First Example Production of Printed Wiring Board Preparation of Adhesive for Electroless Plating (1) 35 parts by weight of 25% by weight acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500)
Photosensitive monomer (Toa Gosei: Aronix M31
5) 3.15 parts by weight, 0.5 parts by weight of an antifoaming agent (S-65 manufactured by San Nopco) and 3.6 parts by weight of N-methylpyrrolidone (NMP) were mixed by stirring.

(2) 12 parts by weight of polyether sulfone (PES) and 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, trade name: Polymer Pole) having an average particle size of 1.0 μm and 7.2 parts by weight of an epoxy resin particle having an average particle size of 0.5 μm. After mixing 3.09 parts by weight, further NM
30 parts by weight of P was added and mixed by stirring with a bead mill.

(3) 2 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals: 2E4MZ-CN), a photoinitiator (manufactured by Ciba-Geigy:
2 parts by weight of Irgacure I-907), 0.2 parts by weight of a photosensitizer (DETX-S, manufactured by Nippon Kayaku), and 1.5 parts by weight of NMP were stirred and mixed. (4) The mixtures (1) to (3) were mixed to obtain an adhesive composition for electroless plating.

Preparation of resin filler (1) 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell: molecular weight: 310, trade name: YL983U) and SiO having a surface coated with a silane coupling agent having an average particle size of 1.6 μm ₂ spherical particles [Admatechs made: CRS 1101
-CE, where the maximum particle size is not more than the thickness (15 μm) of the inner layer copper pattern described later. 170 parts by weight, 1.5 parts by weight of a leveling agent (manufactured by San Nopco: trade name Perenol S4) are kneaded with a three-roll mill, and the viscosity of the mixture is adjusted to 23 ±
It was adjusted to 45,000 to 49,000 cps at 1 ° C.

(2) Imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN) 6.5 parts by weight. (3) The mixtures (1) and (2) were mixed to prepare a resin filler.

Preparation of Solder Resist A photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of epoxy groups of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was added to 4 parts by weight.
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained.

Production of Printed Wiring Board (1) A copper-clad laminate in which a 12 μm copper foil 32 is laminated on both sides of a substrate (Matsushita Electric R5715Tg: 190 ° C.) 30 made of glass epoxy resin having a thickness of 0.6 mm. 30A was used as a starting material (FIG. 1 (A)). This was etched to adjust the thickness to 5 μm (FIG. 1B).

(2) The copper-clad laminate 30A is covered with a carbon dioxide laser (Mitsubishi Electric ML605GTL) for 30 m.
J, a laser was irradiated under a pulse condition of 52 × 10 ^-6 seconds under a condition of 15 shots, and a through hole 16 having a diameter D: 100 μm was irradiated.
(FIG. 1 (C)). The through-hole 16 was not tapered.

Next, electroless plating and electrolytic plating are performed (FIG. 1 (D)), and a copper foil is etched in a pattern according to a conventional method to form an inner copper pattern (lower conductor) having a thickness of 15 μm on both surfaces of the substrate. Circuit) 34 and through hole 36
Was formed (FIG. 1E).

Next, a roughened surface 38 was provided on the surface of the inner layer copper pattern 34 and on the surface and the inner wall of the land 36A of the through hole 36, respectively, to manufacture a wiring board (FIG. 2).
(F)). After the above-described substrate 30 is washed with water and dried, the roughened surface 38 is sprayed with an etching solution on both surfaces of the substrate by spraying, so that the surface of the inner layer copper pattern 34 and the through hole 36 are formed.
By etching the surface of the land 36a and the inner wall. The etching solution is imidazole copper (I
I) A mixture of 10 parts by weight of a complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water was used.

(3) Next, a resin layer 40 was provided between the inner layer copper patterns 34 of the wiring board and in the through holes 36 (FIG. 2 (G)). The resin layer 40 is coated with the resin filler B prepared in advance on both surfaces of the wiring board by a roll coater, and filled between the inner layer copper patterns and in the through holes.
1 hour at 00 ° C, 3 hours at 120 ° C, 1 hour at 150 ° C, 180
The film was cured by heat treatment at 7 ° C. for 7 hours.

(4) One surface of the substrate 30 obtained in the process of (3) is
The belt sander was polished. In this polishing, using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.), the resin filler 40 was not left on the roughened surface 38 of the inner layer copper pattern 34 or the surface of the land 36a of the through hole 36 (FIG. 2 ( H)). Next, buffing was performed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.

In the obtained wiring board 30, the resin layer 40 is provided between the inner copper patterns 34, and the resin layer 40 is provided in the through holes 36. The roughened surface 38 of the inner layer copper pattern 34 and the roughened surface of the land 36a of the through hole 36 are removed, and both surfaces of the substrate are smoothed by a resin filler. The resin layer 40 has a roughened surface 387 on the side surface of the inner layer copper pattern 34 or a land portion 36 a of the through hole 36.
The resin layer is in close contact with the roughened surface of the inner wall of the through hole.

(5) Further, the exposed inner layer copper pattern 34 and the upper surface of the land 36a of the through hole 36 were roughened by the etching process (2) to form a roughened surface 42 having a depth of 3 μm (FIG. 2 (I)). )).

The roughened surface 42 is plated with tin and replaced with
An Sn layer (not shown) having a thickness of 3 μm was provided. The displacement plating is performed under the conditions of tin borofluoride 0.1 mol / L, thiourea 1.0 mol / L, temperature 50 ° C., pH = 1.2, and roughened surface is Cu—S
An n-substitution reaction was performed.

(6) The adhesive for electroless plating was applied to both surfaces of the obtained wiring board 30 using a roll coater. The adhesive was left standing for 20 minutes in a horizontal state, and then dried at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 35 μm (FIG. 2 (J)).

(7) Both surfaces of the obtained wiring substrate 30 were exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp and heated at 150 ° C. for 5 hours.

(8) The obtained substrate 30 was immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer 50. By this treatment, a roughened surface was formed on the surface of the adhesive layer 50. Then, the obtained substrate 30
Was immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (FIG. 2 (K)).

(9) Then, a thickness of 0.6
A μm electroless copper plating 44 was applied (FIG. 3 (L)).

(10) An etching resist (not shown) is provided and etched with an aqueous solution of sulfuric acid and hydrogen peroxide to form a via hole in the electroless copper plating 44 with a diameter of 50 μm.
(FIG. 3 (M)).

(11) Using the electroless copper plating 44 as a conformal mask, the adhesive layer 50 under the opening 44a is removed by a short pulse (10 ^-4 seconds) laser beam (Mitsubishi Electric ML605GTL) to remove the via. A hole opening 48 was provided (FIG. 3 (N)).

Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the wiring substrate 30, catalyst nuclei were attached to the surface of the electroless plating film 44 and the roughened surface of the via hole opening 48.

(12) The obtained substrate 30 was immersed in an electroless copper plating bath under the following conditions to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire substrate 30 (see FIG. )). Electroless plating solution; EDTA: 150 g / L Copper sulfate: 20 g / L HCHO: 30 mL / L NaOH: 40 g / L α, α'-bipyridyl: 80 mg / L PEG: 0.1 g / L None Electroplating conditions: 30 minutes at 70 ° C liquid temperature

(13) Next, a commercially available photosensitive dry film (not shown) was attached to the electroless copper plating film 52, and a mask film (not shown) on which a pattern was printed was placed. The substrate 30 was exposed at 100 mJ / cm ² , and then exposed to light at a rate of 0.1 mJ / cm ² .
Developing treatment was performed with 8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (FIG. 3 (P)).

(14) Next, the obtained substrate is subjected to electrolytic copper plating under the following conditions, and an electrolytic copper plating film 5 having a thickness of 15 μm is formed.
6 was formed (FIG. 4 (Q)). Electrolytic plating solution; Sulfuric acid: 180 g / L Copper sulfate: 80 g / L Additive: 1 mL / L (The additive is manufactured by Atotech Japan: trade name Capalaside G
L) Electroplating conditions; Current density: 1 A / dm ² hours: 30 minutes Temperature: room temperature

(15) After the plating resist 54 is peeled off with 5% KOH, it is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
Dissolve and remove the electroless plating film 52 under the plating resist,
The copper foil 32, the electroless plating 44, the electroless copper plating film 52, and the electrolytic copper plating film 56 have a thickness of 18 μm (10 μm
A conductor circuit 58 and via holes 60 each having a thickness of about 30 μm were obtained (FIG. 4 (R)). Here, the thickness is 10 μm to 30 μm.
By setting m, both fine pitch and connection reliability can be achieved.

Furthermore, the adhesive layer 5 for electroless plating between the conductor circuits 58 was immersed in chromic acid of 80 g / L at 70 ° C. for 3 minutes.
The surface of No. 0 was etched at 1 μm to remove the palladium catalyst on the surface.

(16) The same processing as in (5) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu-Ni-P was formed on the surfaces of the via holes 60 and the via holes 60, and the surfaces thereof were further substituted with Sn (see FIG. 4 (S)).

(17) By repeating the steps (6) to (16), an interlayer resin insulating layer 160 as an upper layer, a via hole 160 and a conductor circuit 158 are further formed. Further, the roughened layer 16 is formed on the surface of the via hole 160 and the conductive circuit 158.
2 to complete the multilayer printed wiring board (FIG. 3
(T)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.

(18) Then, solder bumps are formed on the above-mentioned multilayer printed wiring board. Substrate 3 obtained in (17) above
On both sides, the above-mentioned solder resist composition is applied in a thickness of 45 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact. Exposure to ultraviolet light of 1000 mJ / cm ² and DMTG development processing. And at 80 ° C for 1 hour,
Heat treatment under conditions of 100 ° C for 1 hour, 120 ° C for 1 hour, and 150 ° C for 3 hours, and a solder resist layer having an opening (opening diameter 200 μm) 71 in the solder pad portion (including the via hole and its land portion) (Thickness: 20 μm) 70 is formed (FIG. 5 (U)).

(19) Next, nickel chloride 2.31 × 10 ^-1 mol
/ L, sodium hypophosphite 2.8 × 10 ^-1 mol / l, sodium citrate 1.85 × 10 ^-1 mol / l, pH
= 4.5 of the substrate 30 in an electroless nickel plating solution.
By immersing for 5 minutes, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Further, the substrate was treated with 4.1 × 10 ^-2 mol / l of potassium gold cyanide and 1.87 mol of ammonium chloride.
× 10 ^-1 mol / l, sodium citrate 1.16 × 10 ^-1 mo
1 / l, sodium hypophosphite 1.7 × 10 ^-1 mol / l, immersed in electroless gold plating solution at 80 ° C. for 7 minutes and 20 seconds, and gold plating 0.03 μm thick on nickel plating layer By forming the layer 74, the solder pads 75 are formed in the via holes 160 and the conductor circuits 158.
(V)).

(22) Then, a solder paste is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U, 76D
To form a multilayer printed wiring board 10 (see FIG. 6).

Comparative Example As a starting material for the core substrate, R-1705 manufactured by Matsushita Electric Works, Ltd.
A multilayer printed wiring board was manufactured in the same manner as in the first embodiment using a double-sided copper-clad laminate having a grade of (FR-4 grade: Tg point: 165 ° C.). HAST and ST were applied to the multilayer printed wiring board of the example and the multilayer printed wiring board of the comparative example.
EAM and TS tests were performed.

Here, in the HAST test, the conditions were 130 ° C. and 85% R for 10 multilayer printed wiring boards.
h, at 1.3 atm, 1.8 V was applied.
After holding for 00 hours, the insulation resistance between the plated through holes was measured. On the other hand, in the STEAM test, the conditions were 121 ° C., 100% Rh, and 10 multilayer printed wiring boards.
After maintaining the state of 2.1 atm for 336 hours, the insulation resistance between the plated through holes was measured. On the other hand, in the TS test, 1
3 at -55 ° C for 0 multilayer printed wiring boards
Heating and cooling for 3 minutes at 125 ° C. for 3 minutes were repeated 1000 times, and the resistance change of the plated through-hole chain was measured. As shown in FIG. 1 (E '), a plated through-hole chain is formed by forming adjacent through-holes 36 into a conductor circuit 34 on the front side and a conductor circuit 34 on the back side of the core substrate.
And are electrically connected in a chain.

HAST STEAM TS Test Example 1 × 10 ⁸ Ω 1 × 10 ⁸ Ω 5% Resistance Change Comparative Example 1 × 10 ⁶ Ω 1 × 10 ⁶ Ω 10% Resistance Change As shown in the results, the multilayer of the comparative example is shown. In the case of a printed wiring board, the insulating property is significantly reduced.

In this embodiment, the reliability required for a multilayer printed wiring board was obtained by using Matsushita Electric Works R5715 (Tg: 190 ° C.) as the substrate 30. In the same manner as in this embodiment, the following HAS was used for the following glass epoxy substrates (1) to (4) having a Tg point of 190 ° C. or more.
When T, STEAM, and TS tests were performed, it was found that reliability equivalent to that of the example was obtained. From this result, it was found that the required reliability was obtained by using a glass epoxy substrate having a Tg of 190 ° C. or higher. (1) Mitsubishi Gas Chemical HL830 (Tg point 217 ° C) (2) Mitsubishi Gas Chemical HL830FC (Tg point 212
° C) (3) Hitachi Chemical MCL-E-679LD (Tg point 205-215 ° C) (4) Hitachi Chemical MCL-E-679F (Tg point 2
05-217 ° C)

[0052]

As described above, in the present invention, an inexpensive core material made of a glass epoxy substrate is used as a core substrate.
Sufficient performance can be obtained as insulation resistance between plated through holes and heat cycle characteristics.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D), FIG. 1 (E), and FIG. 1 (E ′) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

2 (F), 2 (G), 2 (H), 2
(I), FIG. 2 (J), and FIG. 2 (K) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

3 (L), 3 (M), 3 (N), 3
(O) and FIG. 3 (P) are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 (Q), FIG. 4 (R), FIG. 4 (S), FIG.
(T) is a manufacturing process diagram of the multilayer printed wiring board according to the first example of the present invention.

FIGS. 5 (U) and 5 (V) are cross-sectional views of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 30 core substrate 34 conductive circuit 36 through hole (plated through hole) 50 interlayer resin insulating layer 52 electroless plating layer 56 electrolytic plating layer 58 conductive circuit 60 via hole 150 interlayer resin insulating layer 158 conductive circuit

Claims (1)

[Claims] A via hole in which interlayer resin insulation layers and conductor circuits are alternately laminated on a substrate on which a through hole and a conductor circuit are formed, and conductor circuits of different layers are provided in the interlayer resin insulation layer. A multilayer printed wiring board, wherein the substrate is a glass epoxy board using an epoxy resin having a Tg point of 190 ° C. or higher.