JP2000106402A - Semiconductor nonvolatile memory storage and write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor non-volatile memory storage, having excellent surface efficiency, on which electric write-in operation can be performed only once, and to provide the write-in method of its program. SOLUTION: On a semiconductor non-volatile memory storage, the first element region 3a is formed in the region of the first well 2a provided on a semiconductor substrate 1 of a semiconductor non-volatile memory storage 15, and the second element region 3b is formed in the region of the second well 2b in such a manner that they are separated by a field oxide film 4. A memory transistor 16, to be used to write-in a program, is provided on the above-mentioned first element region 3a, an address transistor 17, which controls the write-in operation, is provided on the second element region 3b, and the source region 11b of the address transistor 17 and the drain region 10a of the memory transistor 16 are connected by a metal wiring 9c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device which can be electrically written only once, and more particularly to a nonvolatile semiconductor memory device which writes a program by destroying a transistor and a writing method thereof.

[0002]

2. Description of the Related Art In general, in a semiconductor integrated circuit, in order to improve the yield and stabilize the performance, it is necessary to correct the variation in the threshold voltage of the transistor and to correct or adjust the operation conditions.

In an electronic timepiece, a quartz oscillator is oscillated by an oscillation circuit provided in a composite circuit for a timepiece,
A clock signal serving as a reference for clocking is generated. However, when a tuning-fork type crystal oscillator is used, the frequency of the clock signal slightly varies due to a subtle difference in size due to the processing accuracy.

[0004] As described above, the finely-varied clock signal output from the oscillation circuit using the crystal oscillator is converted to a precision of ppm (parts per million:
Adjusting the digital frequency in a circuit to adjust to the accuracy of n) is called DF adjustment. Therefore, DF adjustment of a conventional timepiece will be described with reference to FIGS. First, the principle of the DF adjustment will be described with reference to the circuit diagrams of FIGS. 7 and 8 and the time chart of FIG.

FIG. 7 is a block circuit diagram showing a configuration of a conventional DF adjustment circuit. An oscillation circuit 23 using a crystal oscillator 18, a frequency dividing circuit 24, a DF adjustment timing circuit 25, and a DF adjustment circuit are shown in FIG. A data read circuit 26 and a plurality of D
An F adjustment terminal 27 and a plurality of AND circuits 28 are provided. The frequency dividing circuit 24 includes a plurality of flip-flop circuits (hereinafter abbreviated as “FF circuits”) 29a to 29e.

In the figure, solid arrows indicate the DF adjustment data read signal Sa, dashed arrows indicate the DF adjustment data signal Sb, and dashed-dotted arrows indicate the input and output directions of the DF adjustment timing signal Sc to each circuit. FIG. 8 shows a specific circuit diagram example of the DF adjustment data read circuit 26 in FIG. The DF adjustment data read circuit 26 includes a plurality of inverters 33 and the same number of NOR circuits 34.

Then, the power supply voltage VDD is input to each inverter 33 via each DF adjustment terminal 27, and the inverted output of each inverter 33 is input to one input terminal of each NOR circuit 34. The other input terminals of the circuits 34 are commonly connected to input the DF adjustment data read signal Sa, and the output terminal of each NOR circuit 34 is connected to the input side of each inverter 33. This NO
The output signal of the R circuit 34 becomes the DF adjustment data signal Sb.

FIG. 9 is a timing chart of the output signals of the first to fifth FF circuits 29a to 29e constituting the frequency dividing circuit 24 with respect to the DF adjustment data read signal Sa and the DF adjustment timing signal Sc shown in FIG. It is a chart. In FIG. 9, T1 is the timing at which the DF adjustment data read signal Sa changes to a high level “H”, and T2 is the timing
The timing at which the adjustment data read signal Sa becomes low level “L” is shown. Further, T3 indicates a timing when the DF adjustment timing signal Sc is set to the high level “H”.

In FIG. 7, the output signal of the oscillation circuit 23 is input to the first FF circuit 29a constituting the frequency dividing circuit 24, and the operation of the frequency dividing circuit 24 is started. In FIG. 9, T
When the timing becomes 1, the DF adjustment timing circuit 25
Receives the output signal of the frequency dividing circuit 24 and outputs the DF adjustment data read signal Sa, which is normally "L", as "H" for several milliseconds.

The DF adjustment data read signal Sa is "H"
, The DF adjustment data read circuit 2 shown in FIG.
6 are all "L". At this time, each DF depends on the power supply voltage VDD.
When the signal from the adjustment terminal 27 is “H”, each NOR
Although a potential inquiry occurs between the output of the circuit 34 and each DF adjustment terminal 27, the input signal of each inverter 33 and the output signal of each NOR circuit 34 become "H", and the output signal of each inverter 33 becomes "H". L ".

Here, the DF adjustment data read signal Sa
Becomes "L" at the timing of T2 in FIG. 9, the two input signals of the NOR circuits 34 in FIG.
The output signal of the R circuit 34 becomes "H".

However, a plurality of DF adjustment terminals 27
Is selectively disconnected, the output signal of the NOR circuit 34 connected to the disconnected DF adjustment terminal 27 and the DF
There is no potential inquiry between the terminal 27 and the adjustment terminal 27. Therefore, while the DF adjustment data read signal Sa is “H”, the output signal of the NOR circuit 34 is “L” and the output of the inverter 33 is “H”.

[0013] Even if the output of the DF adjustment data read signal Sa becomes "L" at the timing of T2 shown in FIG.
Since the input signal to the OR circuit 34 is only “L” and “H”, the output signal of the NOR circuit 34 is maintained at “L”. That is, when it is desired to maintain the output signal of the NOR circuit 34 at “L”, the desired NOR circuit 34
May be cut off the DF adjustment terminal 27 corresponding to. The output signal of each NOR circuit 34 of the DF adjustment data read circuit 26 becomes DF adjustment data Sb and is input to each AND circuit 28 shown in FIG.

The DF adjustment data read signal Sa is changed from "H" to "L" again at the timing of T2 shown in FIG.
The F adjustment timing circuit 25 then sets the DF adjustment timing signal Sc, which is normally "L", to "H" for a moment at the timing of T3 shown in FIG.
If the DF adjustment data Sb is “H”, the output signal of “8” becomes “H” only at the moment when the DF adjustment timing signal Sc becomes “H”.

At this time, the output signals of the FF circuits 29a to 29e constituting the frequency dividing circuit 24 are all "L".
An FF corresponding to the AND circuit 28 whose output signal becomes “H”
The output signal of only the circuit 29 becomes “H”, and the frequency dividing circuit 24
Works somewhat faster than it actually is. In this way, it is possible to adjust the digital frequency of the clock signal in a circuit.

Next, writing of DF adjustment data will be described with reference to FIG. FIG. 10 is a plan view schematically showing a conventional composite circuit for a timepiece. The composite circuit for watches
DF adjustment terminal 27 provided on composite circuit board 35, IC
36 and the crystal unit 18. In FIG.
The white circle 38 indicates a hole opened in the middle of the DF adjustment terminal 27 for cutting the DF adjustment terminal 27 by a cutting means such as a drill.

The determination of the DF adjustment data is made based on the data signal when the DF adjustment terminal 27 is connected and the data signal when the DF adjustment terminal 27 is disconnected, that is, the power supply voltage VDD from any one of the plurality of DF adjustment terminals 27 to the IC 36. It depends on whether the signal is input or not. Therefore, by cutting the DF adjusting terminal 27 shown in FIG. 10 by a cutting means such as a drill, the corresponding DF is adjusted.
The adjustment data Sb becomes “L” and the DF adjustment terminal 27
Is set to "H" by not cutting.

[0018]

As described above, in the composite clock circuit shown in FIG. 10, the DF adjustment terminals 27 are set by the number of DF adjustment data, and the DF adjustment terminals to which the program is to be written are to be set. DF adjustment is performed by cutting only 27 using a mechanical cutting means such as a drill. To implement this program writing method, dedicated input / output terminals must be provided on the IC 36 by the number of the DF adjustment terminals 27.

Each input / output terminal is 100 μm
^{Since the} IC 36 has an area of about ^{two, if} the number of input / output terminals provided on the IC 36 is equal to the number of the DF adjustment terminals 27, the area of the IC 36 becomes very large. As the area of the IC 36 increases, the ratio of the area occupied by the IC on the composite circuit board 35 increases, and at the same time, the area efficiency with respect to the wafer decreases and the number of chips that can be obtained from one wafer decreases. Further, since the program is written by a mechanical cutting means such as a drill, the processing time is long.

The present invention has been made in order to solve such a problem, and has excellent area efficiency and is suitable for performing DF adjustment of a clock signal in a clock composite circuit. It is an object of the present invention to provide a possible semiconductor nonvolatile memory device and a program writing method thereof.

[0021]

In order to achieve the above object, the present invention provides a semiconductor nonvolatile memory device having the following configuration.

That is, in the semiconductor nonvolatile memory device according to the present invention, a first well and a second well are provided on the same surface side of a semiconductor substrate, and separated by a field oxide film provided on the semiconductor substrate. A first element region is formed in the first well region, a second element region is formed in the second well region, and a memory transistor for program writing is provided in the first element region. An address transistor for controlling writing of the memory transistor is provided in the second element region, and a source region of the address transistor and a drain region of the memory transistor are connected by a metal wiring.

The surface impurity concentration of the first well is set to the second
It is better to make the concentration higher than the surface impurity concentration of the well. It is preferable that the channel area of the gate electrode of the memory transistor be smaller than the channel area of the gate electrode of the address transistor.

For this purpose, the channel width of the gate electrode of the upper memory transistor is made smaller than the channel width of the gate electrode of the address transistor, or the channel length of the gate electrode of the memory transistor is made shorter than the channel length of the gate electrode of the address transistor. It needs to be hidden.
In the memory transistor, the gate electrode and the source region may be connected by a metal wiring.

Further, a writing method of a semiconductor nonvolatile memory device according to the present invention is characterized in that a program is written only once by electrically destroying a memory transistor in the above-described semiconductor nonvolatile memory device. Therefore, when writing the program,
It is preferable that a current in a current region larger than the saturation current value but not causing the destruction of the transistor be supplied to the address transistor.

In addition, by applying the same voltage to the gate electrode of the memory transistor and the gate electrode of the address transistor at the same time in the semiconductor nonvolatile memory device to electrically destroy the memory transistor, the program is written only once. You may do so.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments of the present invention, a semiconductor non-volatile memory device is provided with a composite element of a memory transistor and an address transistor, both of which are N-type MOS transistors;
The writing method will be described.

[First Embodiment: FIGS. 1 to 3] FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor nonvolatile memory device according to the present invention. The structure of the nonvolatile memory device will be described.

The semiconductor nonvolatile memory device 15 shown in FIG.
Is a first P-type conductive type on the same surface side of the semiconductor substrate 1.
A well 2a and a second P well 2b are provided.
The first element region 3a and the second element region 3b are provided separately in the region of the P well 2a and the region of the second P well 2b by the field oxide film 4, respectively.

Then, the first and second element regions 3a, 3b
The gate oxide films 5a and 5b are formed respectively, and the first gate electrode 6a having a channel length of 1.2 μm and a channel width of 10 μm in the transistor region is formed on the gate oxide film 5a in the first element region 3a. Provided, the second element region 3b
A second gate electrode 6b having a channel length of 1.6 μm and a channel width of 40 μm in the transistor region is provided on the gate oxide film 5b.

Further, the drain regions 10a and 10b in which N-type impurities are diffused and the source region 11 are formed in the first and second element regions 3a and 3b on both sides of each of the gate electrodes 6a and 6b.
a and 11b are formed, and a memory transistor 16 for program writing is formed in the first element region 3a, and an address transistor 17 for controlling writing of the memory transistor 16 is formed in the second element region 3b.

On the semiconductor substrate 1 on which these are formed, an interlayer insulating film 7 is provided, in which the gate electrodes 6a and 6b of the memory transistor 16 and the address transistor 17, the drain regions 10a and 10b, and the source regions 11a and 1a are provided.
1b, contact holes 8 are formed, and metal wirings 9a, 9b, 9c, 9 are formed therein.
d, 9e are provided.

The semiconductor nonvolatile memory device 15
Are connected to the first element region 3a by the independent metal wiring 9c.
Drain region 10a of memory transistor 16 having first gate electrode 6a provided in
Is connected to the source region 11b of the address transistor 17 having the second gate electrode 6b provided at the second position. As described above, the memory transistor 16 and the address transistor 17, which are N-type MOS transistors, are formed on the other wells 2 a and 2 b provided in the same semiconductor substrate 1.
Are formed in series to form a semiconductor nonvolatile memory device 15.

The channel width and channel length of gate electrode 6a of memory transistor 16 are smaller than the channel width and channel length of gate electrode 6b of address transistor 17. In this manner, the channel area of the gate electrode 6a of the memory transistor 16 is made smaller than the channel area of the gate electrode 6b of the address transistor 17, thereby facilitating the destruction of the memory transistor 16.

FIG. 2 shows this semiconductor nonvolatile memory device 15.
1 shows characteristics of the memory transistor 16 and the address transistor 17 which constitute the semiconductor device. In the following description, the “gate electrode”, “drain region”, and “source region” described in FIG. 1 are simply referred to as “gate”, “drain”, and “source”, respectively. FIG. 2 shows the drain current with respect to the drain voltage of each of the memory transistors 16 and the address transistors 17 of the semiconductor nonvolatile memory device 15 having the structure shown in FIG. FIG. 4 is a diagram showing a change in.

In FIG. 2, the horizontal axis indicates the drain voltage of the transistor, and the vertical axis indicates the drain current. The solid line indicates the drain current of the memory transistor 16 with respect to the drain voltage, and the broken line indicates the drain current of the address transistor 17 with respect to the drain voltage. Further, the one-dot chain line in FIG. 2 indicates the level of the drain current that causes the memory transistor 16 to break down. A voltage of 3 V is applied to the gate electrodes 6a and 6b of the memory transistor 16 and the address transistor 17.

As shown in FIG. 2, when the drain current changes with respect to the drain voltage applied to the drain of the memory transistor 16, the drain current sharply increases when the drain voltage exceeds 8V. However, having a resistance in the region where the drain current exceeds 10mA (10- ² A), the drain voltage leading to total destruction can be confirmed to be about 9V.

On the other hand, looking at the change of the drain current with respect to the drain voltage applied to the drain of the address transistor 17, when the drain voltage exceeds 7 V, the drain current sharply increases, but the drain current increases by 100 mA.
It can be confirmed that it does not lead to destruction by a degree.

From this, the drain current was reduced to 100 mA.
Is set, a voltage of about 10 V is applied to the drain of the address transistor 17,
A current equal to or greater than the saturation current flows, and the address transistor 1
7 can be destroyed without destroying only the memory transistor 16.

As described above, when writing a program, the memory transistor 16 is destroyed by using the current in the current region that exceeds the saturation current but is in a stage before the transistor is destroyed, by using the address transistor 17. Therefore, it is not necessary to have a saturation current characteristic corresponding to the necessary drain current, and the channel area of the gate electrode does not need to be so large.

The DF adjustment of the timepiece is performed by applying a program voltage only once to the semiconductor nonvolatile memory device for about 100 msec as a write condition. In the semiconductor nonvolatile memory device 15 of this embodiment, it has been confirmed that the characteristics of the address transistor 17 after writing the program as described above have no particular problem including the deterioration characteristics.

Next, a method of controlling the semiconductor nonvolatile memory device described with reference to FIG. 1 will be described with reference to the circuit diagram of FIG. In the semiconductor nonvolatile memory device 15 according to this embodiment, the memory transistor 16 is turned on while the same voltage is applied to the gate of the memory transistor 16 and the gate of the address transistor 17 to turn on both transistors.
By applying a voltage necessary to destroy the memory transistor 16 to the drain of the address transistor 17 and electrically destroying the memory transistor 16, the program is written only once.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor device equipped with the semiconductor nonvolatile memory device 15 shown in FIG. In the figure, the semiconductor non-volatile memory device 15 is surrounded by a two-dot chain line. And 12 is a ground terminal, 21
Is a read-only terminal, 22 is an output terminal, 30 is a write-only terminal, 13 is a clock terminal, 14 is an AND circuit,
Reference numeral 9 denotes a data reading resistor, and reference numeral 20 denotes a reading transistor switch.

At the time of program writing, no voltage is applied to the read-only terminal 21, no clock signal is input to the clock terminal 13, and the read transistor switch 20 remains off. And a grounding terminal 1
2 is grounded, the same voltage Vg of about 3 V is applied to the gate G of the memory transistor 16 and the gate G of the address transistor 17, and both transistors are turned on. A voltage of about 10 V required for writing a program is applied.

At this time, since the address transistor 17 is in the ON state, the voltage applied to the drain D is applied from the source S to the drain D of the memory transistor 16 via the metal wiring 9c shown in FIG. A drain current of about 100 mA is supplied to the memory transistor 16 to electrically destroy the drain current and write a program. The drain of the destroyed memory transistor 16
A short circuit occurs between the sources.

The data reading resistor 19 includes an address transistor 17 and a reading transistor switch 20.
And the resistance value of the address transistor 17 and the read transistor switch 20 is changed to the resistance value of the memory transistor 16 after the destruction (the resistance value due to the short-circuit state). Is set to a resistance value larger than the resistance value obtained by adding about several Ω.

When confirming that the memory transistor 16 has been destroyed, the ground terminal 12 is left open, and a voltage of about 1.5 V, which is lower than that at the time of program writing, is applied to the gate G of the address transistor 17. The voltage VDD is applied to the read-only terminal 21.

The voltage applied to the gate G of the address transistor 17 is also applied to one input terminal of the AND circuit 14, and a clock signal is input from the clock terminal 13 and applied to the other input terminal. Therefore, the output of the AND circuit 14 becomes "H" only when the clock signal becomes "H", the read transistor switch 20 applied to the gate thereof is turned on, and the address transistor 17 is also turned on. .

As a result, the address transistor 17
And the data reading resistor 19 to which the voltage VSS (normally 0 V) is applied to one end, a potential inquiry occurs.
If the memory transistor 16 is not destroyed, the resistance value of the data reading resistor 19 becomes smaller than the sum of the resistance values of the address transistor 17, the reading transistor switch 20, and the memory transistor 16 in the ON state, and is read-only. The voltage VDD applied to the terminal 21 is not detected as a signal from the output terminal 22.

On the other hand, if the memory transistor 16 is broken, the resistance value of the data reading resistor 19 becomes the resistance value in the ON state of the address transistor 17 and the reading transistor switch 20, and the resistance value of the memory transistor 16 As a result, the voltage VDD applied to the read-only terminal 21 is detected from the output terminal 22 as a signal.

In this manner, the memory transistor 16 is controlled by the cycle of the clock signal input from the clock terminal 13.
Can be checked based on the detection voltage from the output terminal 22. Note that even when a large number of semiconductor nonvolatile memory devices 15 in which the memory transistor 16 and the address transistor 17 are formed in series are provided,
The terminals 12, 13, 21, 22, and 30 may be provided one by one in common.

Such a semiconductor nonvolatile memory device is shown in FIG.
The configuration of the DF adjustment circuit when the DF adjustment is performed by incorporating it into the IC 36 of the watch complex circuit as shown in FIG. 0 is different from that shown in FIG. 7 and FIG. Since the resistance value between the drain and the source greatly changes, it is easy to perform DF adjustment using the resistance value.

[Second Embodiment: FIGS. 4 to 6]
A second embodiment of the present invention will be described with reference to FIGS. 4 to 6. In FIGS. 4 and 6, the same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals.
Their description is omitted.

FIG. 4 is a schematic sectional view showing a second embodiment of the semiconductor nonvolatile memory device according to the present invention.
This semiconductor nonvolatile memory device 15 'is different from the semiconductor nonvolatile memory device 15 of the first embodiment shown in FIG. 1 in that a gate electrode 6a and a source region 11a of a memory transistor 16' are connected by a metal wiring 9d. It is only the connection point.

FIG. 5 shows that no gate voltage is applied to the memory transistor 16 'and the address transistor 1
FIG. 7 is a diagram showing a change in drain current with respect to the drain voltage of each transistor when a gate voltage is applied. The solid line indicates the drain current with respect to the drain voltage of the memory transistor, the broken line indicates the drain current with respect to the drain voltage of the address transistor, and the dashed line indicates the level of the drain current at which the memory transistor is destroyed.

In this case, since the memory transistor is in the off state, the drain current hardly flows until the drain voltage becomes about 8 V, and when a higher drain voltage is applied, the drain current sharply flows. At first, when the drain voltage becomes about 9 V, a drain current of about 100 mA flows, leading to breakdown. The address transistor is
Even if a drain current of about 100 mA, which exceeds the saturation current value, flows for a short time, it will not be destroyed.

Therefore, according to the semiconductor nonvolatile memory device 15 'of this embodiment, the address transistor 1
7, a voltage of about 10 V required for destruction of the memory transistor 16 'is applied to the drain of the address transistor 17 for 100 m while a constant voltage is applied to the gate electrode 6b.
By applying the voltage only for a short time of about sec and destroying the memory transistor 16 ', a program can be written.

FIG. 6 is a circuit diagram similar to FIG. 3, showing the structure of a semiconductor device equipped with the semiconductor nonvolatile memory device 15 'of the second embodiment. In this case, the memory transistor 16 'of the semiconductor nonvolatile memory device 15'
Has a gate G and a source S connected to each other by a metal wiring 9d.
The only difference from the first embodiment described with reference to FIG. 3 is that no voltage is applied to the memory transistor 16 'and the memory transistor 16' is turned off.

The method of writing the program and the method of checking the write result are the same as those in the first embodiment, so that the description will be omitted.

When checking whether the memory transistor 16 'has been destroyed after writing the program, the voltage VDD applied to the read-only terminal 21 is applied to the gate G of the memory transistor 16'. Since the voltage is applied through the switch 20, if the memory transistor 16 'is not broken, it is turned on.

When the first P well 2a provided with the memory transistor 16 'provided on the semiconductor substrate 1 shown in FIG. 4 and the second P well 2b provided with the address transistor 17 have the same surface impurity concentration, Before the destruction, the resistance value of the memory transistor 16 ′ is several KΩ in the on state,
After destruction, it shows a value of about several ohms.
The resistance value in the ON state of the memory transistor 6 '
It can be controlled by changing the surface impurity concentration of the first P well 2a provided with 6 '.

If the surface impurity concentration of the first P well 2a in which the memory transistor 16 'is provided is higher than the surface impurity concentration of the second P well 2b in which the address transistor 17 is provided, it is possible to prevent the memory transistor 16' from being destroyed. In the ON state, the resistance value in the ON state increases, and the difference between the resistance values before and after writing of the program can be further increased.

As a result, the address transistor 1
7. Since the sum of the resistance values of the read transistor switch 20 and the memory transistor 16 'is significantly different before and after the program is written, the signal detection as to whether or not the program is written is more reliable. This is the same in the case of the first embodiment.

In each of the above embodiments, the N-type MO
Although the description has been given of the semiconductor nonvolatile memory device provided with the composite element of the memory transistor and the address transistor, which are the S transistors, it is needless to say that the memory transistor and the address transistor may be configured by P-type MOS transistors.

[0065]

As described above, the semiconductor non-volatile memory device according to the present invention breaks down the memory transistor without causing the size of the address transistor to be too large, and destroys the memory transistor by flowing a current enough to cause the breakdown. It is possible to do.

As a result, by replacing the DF adjustment wiring in the timepiece with the memory transistor in this semiconductor nonvolatile memory device, it is not necessary to provide input / output terminals by the number of memory elements. The superiority in area is much higher than that.

Furthermore, since the program can be written electrically, the processing time for writing can be greatly reduced as compared with the writing by a mechanical cutting means using a conventional drill or the like. .

[Brief description of the drawings]

FIG. 1 shows a first example of a semiconductor nonvolatile memory device according to the present invention.
It is a typical sectional view showing the structure of the embodiment.

FIG. 2 is a diagram showing a relationship between a drain voltage and a drain current for a memory transistor and an address transistor included in the semiconductor nonvolatile memory device shown in FIG. 1;

FIG. 3 is a circuit configuration diagram schematically showing a control method of the semiconductor nonvolatile memory device shown in FIG. 1;

FIG. 4 shows a second example of the semiconductor nonvolatile memory device according to the present invention.
It is a typical sectional view showing the structure of the embodiment.

5 is a diagram showing a relationship between a drain voltage and a drain current for a memory transistor and an address transistor included in the semiconductor nonvolatile memory device shown in FIG. 4;

FIG. 6 is a circuit configuration diagram schematically showing a control method of the semiconductor nonvolatile memory device shown in FIG. 1;

FIG. 7 is a block circuit diagram showing an example of a DF adjustment circuit in a conventional timepiece.

8 is a DF adjustment data read circuit 26 in FIG.
FIG. 3 is a circuit diagram showing a specific example of the embodiment.

9 is a time chart showing output signals from FF circuits constituting a frequency dividing circuit for a DF adjustment data read signal and a DF adjustment timing signal in the DF adjustment circuit shown in FIG. 7;

FIG. 10 is a schematic plan view showing an example of a conventional composite circuit for a timepiece.

[Explanation of symbols]

 1: semiconductor substrate 2a: first P well 2b: second P well 3a: first element region 3b: second element region 4: field oxide film 5a, 5b: gate oxide film 6a: first gate Electrode 6b: second gate electrode 7: interlayer insulating film 8: contact hole 9a, 9b, 9c, 9d, 9e: metal wiring 10a, 10b: drain region 11a, 11b: source region 12: ground terminal 13: clock terminal 15, 15 ': semiconductor nonvolatile storage device 16, 16': memory transistor 17: address transistor 18: crystal oscillator 30: write-only terminal 19: data read-out resistor 20: read-out transistor switch 21: read-only terminal 22: Output terminal 25: DF adjustment timing circuit 26: DF adjustment data read circuit 27: DF adjustment Child 33: Inverter 34: NOR circuit

Claims (9)

[Claims] A first well and a second well are provided on the same surface side of a semiconductor substrate, and separated by a field oxide film provided on the semiconductor substrate, and a first well and a second well are formed in a region of the first well. A second element region is formed in the region of the second well, and a memory transistor for program writing is provided in the first element region.
An address transistor for controlling writing of the memory transistor is provided in the second element region, and a source region of the address transistor and a drain region of the memory transistor are connected by a metal wiring. Storage device. 2. The semiconductor nonvolatile memory device according to claim 1, wherein a surface impurity concentration of said first well is higher than a surface impurity concentration of said second well. 3. The semiconductor nonvolatile memory device according to claim 1, wherein a channel area of a gate electrode of said memory transistor is smaller than a channel area of a gate electrode of said address transistor. 4. The semiconductor nonvolatile memory device according to claim 3, wherein a channel width of a gate electrode of said memory transistor is smaller than a channel width of a gate electrode of said address transistor. 5. The semiconductor nonvolatile memory device according to claim 3, wherein a channel length of a gate electrode of said memory transistor is shorter than a channel length of a gate electrode of said address transistor. 6. The memory transistor according to claim 1, wherein the gate electrode and the source region are connected by a metal wiring.
6. The nonvolatile semiconductor memory device according to claim 1. 7. The semiconductor nonvolatile memory according to claim 1, wherein the memory transistor in the semiconductor nonvolatile memory device according to claim 1 is electrically destroyed so that a program is written only once. Writing method for a volatile storage device. 8. The writing method for a semiconductor nonvolatile memory device according to claim 7, wherein a current of a current range larger than a saturation current value but not destroying the transistor is supplied to the address transistor at the time of program writing. A writing method for a semiconductor nonvolatile memory device. 9. The semiconductor non-volatile memory device according to claim 1, wherein the same voltage is simultaneously applied to a gate electrode of the memory transistor and a gate electrode of the address transistor so that the memory transistor is activated. A writing method for a semiconductor non-volatile memory device, wherein writing of a program is performed only once by being electrically destroyed.