JP2000100194A - Control circuit of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a contact level from floating after a fuse has been blown by connecting a switch mechanism or a fuse mechanism to one portion of a control signal line and at the same time further connecting one terminal part of a MOS transistor in OFF state to one portion of the control signal line. SOLUTION: A precharge circuit 11 and an equalization circuit 12 that are composed of PMOS transistors Q3, Q4, and Q5 are provided, where a plurality of memory cells MC connect a word line WL to each digit line DL. When a fuse F1 at an address An corresponding to a fault is blown, a precharge signal PB and an input gate Nn of the precharge equalization circuits 11 and 12 are broken, an input gate Nn is fixed to VCC by the sub threshold leak of the PMOS transistor Q1 being turned off even in the standby, regardless of the level of the precharge signal PB and the precharge equalization circuits 11 and 12 are deactivated, and no leakage current flows via abnormal short- circuiting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a semiconductor device, and more particularly to a control circuit for a semiconductor device for preventing a floating state of an end of a control signal line in the control circuit. Things.

[0002]

2. Description of the Related Art Conventionally, regarding a control signal line in a control circuit of a semiconductor device, if at least one end of the signal line is open for some reason,
The potential of the terminal becomes unstable and often becomes a floating state. As a result, a calculation result in a predetermined control circuit fluctuates or an erroneous control signal is output in many cases. Various methods have been proposed to prevent the occurrence of a condition.

An example of a conventional method for preventing the occurrence of a floating state and fixing the end voltage of a control signal line to a predetermined potential will be described with reference to FIG. That is, FIG. 2 shows an example of the configuration of a digit line of a static RAM including a memory circuit 10 having a conventional high resistance load type memory cell MC. In other words, each digit line DL is connected to a plurality of memory cells MC each having a word line WL as a gate of a transfer transistor, and a precharge circuit 11 and an equalize circuit 12 composed of PMOS transistors Q3, Q4, and Q5 are connected to each digit line DL. Is provided.

Each precharge / equalize circuit 11, 1
2 is a plurality of signals (m) of the same address An.
Digit lines DLn1 to DLnm and connected to the gate Nn of each precharge / equalize circuit via a fuse F1. The gate contact Nn of each precharge / equalize circuit is connected to VCC via a resistor R1.
It is connected to the.

The resistance element R1 provided here is used to reduce standby and operating currents.
In order to minimize the influence of the precharge signal PB on the transition, it is necessary to have a high resistance of several hundred GΩ to several TΩ, and is generally formed of a high resistance polysilicon layer for a memory cell. The operation of the above conventional example will be described below.

That is, at the time of non-selection (standby), the precharge signal PB is at "L" level. Normally, the fuses F1, F2,... Are not blown, so that the input gates Nn, N (n +
1) also goes to the "L" level, the precharge / equalize circuit is activated, and each digit line DL is equalized by the PMOS transistor Q5 and precharged to the VCC level via the PMOS transistors Q3 and Q4.

In the above configuration, for example, one G line is connected to one side of the digit line DLn1 due to dust or the like during diffusion.
If there is an abnormal short circuit to ND, digit line DL
The memory cell on n1 malfunctions. In order to remedy this digit operation failure, a method of replacing with a column-based redundancy circuit (redundancy circuit) is adopted.

However, as described above, at the time of standby, the PMOS transistors Q3 and Q4 are ON, so that GND is connected via the PMOS transistors Q3 and Q4 and the digit line DLn1 to GND via an abnormal short circuit. Leak current flows, and as a result, an ISB (standby current) failure occurs.

In order to remedy this ISB defect, the fuse F1 of the defective address An is blown. By doing so, the precharge signal PB and the input gate Nn of the precharge equalizing circuit are cut off, and the input gate Nn is connected to the VCC (H) by the high resistance R1 regardless of the level of the precharge signal PB, that is, even in the standby state.
Level), the precharge / equalize circuit is inactivated, the leak current through the abnormal short circuit described above is eliminated, and the ISB defect is relieved.

Therefore, if the resistor R1 is not provided, the contact Nn after the fuse is cut off may be in a floating state and may be at the "L" level. As a result, there is a possibility that an ISB failure may occur. On the other hand, a resistor for fixing the contact Nn to the “H” level to prevent the floating after the fuse is blown is used to keep the standby current and the operating current small,
Considering the effect of B on the transition, it is necessary to have a high resistance of several hundred GΩ to several TΩ, and it is necessary to use a high resistance polysilicon layer.

[0011]

However, instead of the high resistance type, for example, all the elements constituting the semiconductor device are
If it is a MOS transistor, or if all elements are C
S having MOS type memory cell (Full CMOS)
In a RAM, a high-resistance polysilicon layer for a memory cell cannot be used.

In other words, the use of the high-resistance polysilicon layer to form a high resistance requires a manufacturing step, that is, an additional PR. Alternatively, in order to form this high resistance by another wiring or a MOS transistor which is turned ON as is well known, a huge element area, for example, 1TΩ
PMOS transistor W = 2 μm with ON resistance element
There is a drawback that 600 mm ² is required when formed in series.

Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art and to effectively prevent a floating state of a terminal in which at least one terminal is open in a control circuit of a semiconductor device. And a control circuit for the semiconductor device. Another object of the present invention is to prevent the floating of the contact level after the fuse is blown in order to cut the current leak path at the time of redundancy replacement without using the high-resistance polysilicon layer for the memory cell, and to guarantee the level. It is intended to provide a control circuit of a semiconductor device capable of performing the following.

[0014]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, as a first aspect of the present invention, M
In a semiconductor control circuit composed of OS transistors, a switch mechanism or a fuse mechanism is connected to a part of a control signal line, and one of MOS transistors in an OFF state is connected to a part of the control signal line. A second embodiment according to the present invention is a control circuit of a semiconductor device to which a terminal portion is further connected. In a memory circuit including only MOS transistors, at least a pair of digit lines are individually connected to each other. A plurality of memory cells connected to the word line are connected in parallel, and the pair of digit lines is provided with a precharge circuit for precharging at least the pair of digit lines,
The precharge circuit is connected to a precharge signal line via fuse means, and furthermore, a MOS transistor in an OFF state is connected to a connection between the fuse means and the precharge circuit. It is a control circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In other words, the control circuit for a semiconductor device according to the present invention employs the above-described technical configuration, and therefore, a high-resistance poly-silicon device used in a control circuit for a conventional semiconductor device is used. A silicon layer is not used, and an inactive state, that is, an off-state MOS transistor is used as a high-resistance element. A sub-threshold leak of the off-state MOS transistor causes a switch to be opened or a fuse to be cut. The configuration is such that the potential level of the terminal portion or the contact portion of the control signal line is guaranteed, and occurrence of a floating state is prevented.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a control circuit of a semiconductor device according to the present invention. That is, FIG. 1 is a block diagram showing a configuration of a specific example of a control circuit 1 of a semiconductor device according to the present invention. In the figure, in a semiconductor control circuit 2 composed of MOS transistors, an open state is shown. A switch mechanism or a fuse mechanism 4 is connected to an end P of a certain control signal line 3, and an O is connected to the end P of the control signal line 3.
The control circuit 1 of the semiconductor device in which one terminal of the MOS transistor 5 in the FF state is further connected is shown.

In the control circuit 2 of the semiconductor device 1 according to the present invention, the MOS in the OFF state provided at the end P of the control signal line 3 in the open state.
The transistor 5 (Q2) has the switch mechanism 4
In the case of F or when the fuse mechanism F1 is cut, it is desirable to have a function of preventing the end P of the control signal line 3 from floating.

Further, in the present invention, an odd number of inverters I1 to I3 are arranged in series on the control signal line 3 in the control circuit 2 of the semiconductor device 1. In the present invention, the number of the inverters is not limited to an odd number, but may be an even number.
In the control signal line 3 of the control circuit 2 of the semiconductor device 1 according to the present invention, it is desirable that a latch circuit 6 is arranged in parallel with at least the first-stage inverter I1.

On the other hand, in the control signal line 3 of the control circuit 2 of the semiconductor device 1, at least the capacitor 7 (Q4) composed of a MOS transistor for fixing the signal line 3 near the ground potential and the signal 7 A capacitor 8 (Q) composed of a MOS transistor for fixing the line 3 near the drive power supply voltage
It is also desirable that 3) be provided. Further, in the control circuit 2 of the semiconductor device 1 according to the present invention, the one control signal line 3 is a digit line connected to a group of memory cells MC in the memory circuit 10 as shown in FIG. It may be connected to a precharge circuit 11 for precharging the DL.

Preferably, the memory circuit 10 of the semiconductor device 1 includes a redundant memory circuit (not shown). Hereinafter, the first specific example according to the present invention will be described in more detail with reference to FIG. The control circuit 2 of the semiconductor device shown in FIG. 1 is a general enable circuit 2 that switches the level of an output (node N3) by, for example, cutting or non-cutting of a fuse F1.

A fuse F1 is provided between the contact N1 and VCC, and a gate is connected between GND and GND.
That is, the NMOS transistor Q2 that is turned off is provided. The output signal N2 of the inverter I1 having the contact N1 as an input includes a PMOS transistor Q1 whose gate is connected to VCC, that is, an OFF transistor, and is further provided between the contact N1 and GND. Connected to the gates of the NMOS transistors Q5 and Q6.

On the other hand, the contact N2 is the input signal of the inverter I2, and the output signal of the inverter I2 is the input signal of the inverter I3 which outputs the contact N3. At the time of steep power-on when the fuse F1 is blown,
The level of the contacts N1 and N2 is set to the "L" level,
In order to attain the “H” level, the gates of the NMOS transistor Q4 and the PMOS transistor Q3 are provided at the contacts N1 and N2 as capacitors, respectively.

When the fuse F1 is not blown, the contact N1 is raised to the level of VCC via the fuse, and the contact N3 outputs the "L" level. On the other hand, when the fuse F1 is cut, the contact N1 is turned off.
The voltage is lowered to the level of GND by the sub-threshold leak of the MOS transistor Q2. The contact N2
Is raised to VCC level by the sub-threshold leakage of the PMOS transistor turned off. Contact N
When 2 goes to the "H" level, the transistors Q5 and Q6 are turned on, and the "L" level at the contact N1 is latched. Therefore, the contact N3 outputs an “H” level.

That is, the control circuit 2 of the semiconductor device according to the present invention, for example, outputs its output N3 to an arbitrary NAND
A predetermined selection operation can be executed by inputting the data to an appropriate selection circuit via a gate circuit. As described above, in this specific example, the PMOS transistor and the NM which are turned off without using the high resistance poly layer are used.
Using the sub-threshold leak of the OS transistor, the level after fuse cutting can be determined. In addition, the current flowing through the transistors Q1 and Q2 at the time of non-cutting is very small because it is a sub-threshold leak, and does not affect the standby and operating currents.

Next, a second specific example of the control circuit of the semiconductor device according to the present invention will be described in detail with reference to FIG. That is, a second specific example of the control circuit 2 of the semiconductor device 1 according to the present invention is similar to the control circuit 2 shown in FIG.
1 shows an example in which the present invention is applied to a memory circuit 10.

That is, as a second specific example of the control circuit 2 of the semiconductor device according to the present invention, in the memory circuit 10 composed of only MOS transistors, at least one pair of digit lines DL A plurality of memory cells MC connected to the line WL are connected in parallel, and the pair of digit lines DL is provided with a precharge circuit 11 for precharging at least the pair of digit lines DL, The precharge circuit 11 is connected to the precharge signal line PB via the fuse means F1.
Is connected to the connection P between the fuse means F1 and the precharge circuit 11.
The control circuit 2 of the semiconductor device 1 to which the S transistor 5, that is, Q1 is connected is shown.

It is desirable that an equalizing circuit 12 for equalizing the potential between the pair of digit lines DL is further provided between the pair of digit lines DL in this specific example. Further, the MOS transistor 5 in the OFF state according to the present invention needs to exhibit a high resistance value.

Further, in the control circuit 2 of the semiconductor device according to the present embodiment, the MOS transistor 5 in the OFF state includes at least the precharge circuit 11 arranged on the pair of digit lines DL. MO to configure
An S transistor, for example, a MOS transistor having the same conductivity as Q3, Q4 and the like is desirable. In the present invention, the MOS transistor used is:
An N-channel type MOS transistor may be used.
A N-channel MOS transistor may be used. However, when the conductivity of the substrate is P-type when an N-channel MOS transistor is used, each NMO
Since it is necessary to form an N-type diffusion layer separately for the S transistor, the use area is increased, but the PR is not increased.

Hereinafter, a second specific example according to the present invention will be described in more detail. That is, a case where the control circuit 2 of the semiconductor device according to the present invention is used for controlling a digit line of a static RAM having FULL CMOS type memory cells will be described as an example. As shown in FIG. 3, a plurality of memory cells MC each having a word line WL as a gate of a transfer transistor are connected to each digit line DL, and a precharge circuit 11 composed of PMOS transistors Q3, Q4, Q5 is provided. And an equalizing circuit 12.

Each of the precharge / equalize circuits 1
The precharge signal PB for controlling the first and the second 12 is a plurality of (m) digit lines DLn1 to DLn of the same address An.
It branches every m and is connected to the gate Nn of each of the precharge / equalize circuits 11 and 12 via the fuse F1. Then, the respective precharge / equalize circuits 1
The gate contacts Nn, N (n + 1),... Of P1, P12 whose gates are connected to VCC and which are OFF
It is connected to VCC via MOS transistors Q1 and Q2.

In this configuration, at the time of non-selection (standby), the precharge signal PB is at "L" level. Since the fuses F1, F2,... Are not blown, the input gates Nn, N (n + 1) of the precharge / equalize circuits 11, 12 are also at the "L" level, and the precharge / equalize circuits 11, 12 are activated. And
Each digit line DL is equalized by a PMOS transistor Q5, and V is supplied to the digit line DL via PMOS transistors Q3 and Q4.
It is precharged to the level of CC.

At this time, if there is an abnormal short circuit to GND on one side of the digit line DLn1 due to dust or the like during diffusion, the memory cell on the digit line DLn1 is
Operational failure will result. In order to remedy this digit operation defect, a method of replacing with column-based redundancy is adopted.

However, as described above, since the PMOS transistors Q3 and Q4 are ON during standby, a leakage current flows from VCC to GND via the PMOS transistors Q3 and Q4, the digit line DLn1, and an abnormal short circuit. And ISB (standby current) failure. To remedy this ISB defect, the fuse F1 of the defective address An is cut. By doing so, the precharge signal PB and the input gates Nn of the precharge equalizing circuits 11 and 12 are cut off, and the input gate Nn is turned off regardless of the level of the precharge signal PB, that is, even in the standby state. VC due to sub-threshold leak
It is fixed at C (H level), the precharge / equalize circuit is inactivated, the leak current through the abnormal short circuit is eliminated, and the ISB defect is relieved.

The sub-threshold leakage of the turned off PMOS transistor is as follows when the element region W = 50 μm.
At 106 μm ² , it can be set to about several hundred fA to several tens pA, and there is almost no influence on the standby current, the operating current, and the transition of the precharge signal PB.

[0035]

As described above, the control circuit of the semiconductor device according to the present invention employs the above-described configuration, and therefore does not use the high-resistance polysilicon layer for the memory cell, and does not require the redundancy replacement. It is possible to easily obtain a control circuit of a semiconductor device capable of preventing the floating of the level of the contact after the fuse is cut in order to cut the current leak path and guaranteeing the level.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a specific example of a control circuit of a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional control circuit of a semiconductor device.

FIG. 3 is a circuit diagram showing a configuration of another specific example of the control circuit of the semiconductor device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Control circuit 3 ... Control signal line 4 ... Switch mechanism and fuse mechanism 5 ... High resistance MOS transistor 6 ... Latch circuit 7,8 ... Capacitance 10 ... Memory circuit 11 ... Precharge circuit 12 ... Equalizer circuit

Claims (12)

[Claims] In a semiconductor control circuit composed of MOS transistors, a switch mechanism or a fuse mechanism is connected to a part of a control signal line, and a part of the control signal line is in an OFF state. A control circuit for a semiconductor device, wherein one terminal of a MOS transistor is further connected. 2. The MOS transistor in an OFF state provided on a part of the control signal line is connected to an end of the control signal line when the switch mechanism is OFF or when the fuse mechanism is cut off. 2. The control circuit according to claim 1, wherein the control circuit has a function of preventing a part from floating. 3. The control of the semiconductor device according to claim 1, wherein an odd number of inverters are arranged in series on the control signal line in the control circuit of the semiconductor device. circuit. 4. The control signal line of the control circuit of the semiconductor device, wherein a latch circuit is provided in parallel with at least the first-stage inverter. A control circuit for the semiconductor device according to any one of the above. 5. The control signal line of the control circuit of the semiconductor device, wherein at least a capacitor made up of a MOS transistor for fixing the control signal line near the ground potential and the control signal line near the drive power supply voltage. MO for fixing to
5. The control circuit for a semiconductor device according to claim 1, further comprising a capacitor comprising an S transistor. 6. The control signal line according to claim 1, wherein the one control signal line is connected to a precharge circuit for precharging a digit line connected to a memory cell group in the memory circuit. 6. The control circuit for a semiconductor device according to any one of 5. 7. The control circuit according to claim 6, wherein the memory circuit of the semiconductor device includes a redundant memory circuit unit. 8. In a memory circuit including only MOS transistors, a plurality of memory cells connected to individual word lines are connected in parallel to at least one pair of digit lines, and Digit wire has
A precharge circuit for precharging at least the pair of digit lines is provided. The precharge circuit is connected to a precharge signal line via fuse means, and further includes the fuse means and the precharge circuit. A MOS transistor in an OFF state is connected to a connection portion of the semiconductor device. 9. The control circuit for a semiconductor device according to claim 8, further comprising an equalizing circuit provided between said pair of digit lines for equalizing a potential between said pair of digit lines. 10. The MOS transistor in the OFF state shows a high resistance value.
Or a control circuit for a semiconductor device according to item 9. 11. The MOS transistor in the OFF state is a MOS transistor having at least the same conductivity as a MOS transistor included in the precharge circuit disposed on at least the pair of digit lines. 11. The control circuit for a semiconductor device according to any one of 8 to 10. 12. The semiconductor device according to claim 11, wherein said MOS transistor is one of an N-channel MOS transistor and a P-channel MOS transistor. Control circuit.