JP2000099390A - Cpu and memory control system provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the drop of an access speed when a write access follows a read access in the access of a high speed CPU to a low speed device and to prevent data collision between both the accesses. SOLUTION: An inverted output of a NAND gate 12 while the periods of H levels of a read access signal RD and a write access signal WT are overlapped sets a JK flip-flop (JK-FF) 14. When a counter 15 is reset by a signal RW*, it counts the number of clocks of a clock CLK. A memory management unit 11 extracts delay value (the number of clocks) corresponding to the address of data to be written with the next write access from registers IDL1 to IDLn. When the delay value coincides with count value, a comparator 16 resets the JK-FF 14. An inverted output of the JK-FF 14 delays an access control signal NXTACS instructing the next access in an AND gate 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a high-speed CPU suitable for accessing a low-speed device and a memory control system having the same.

[0002]

2. Description of the Related Art Generally, circuits such as an I / O and a memory are provided as peripheral circuits of a CPU (Central Processing Unit), and data is exchanged between these and the CPU. With the recent increase in the speed of CPUs, high-speed operation of peripheral circuits is also desired.
May not correspond to the operation speed of the CPU. For example, in the case of I / O, since ICs that operate at high speed are generally not commercially available, an ASIC (Application Specific Integration) is required to obtain a desired IC.
ted Circuit), etc.
It is necessary to use an O board, and there is a disadvantage that cost and development time are increased.

In addition, some memory ICs have a low operation speed, such as a flash ROM. EEPROM (Elect
A flash ROM, which is a kind of rically erasable and programmable ROM, can erase data electrically collectively or in units of tens of kilobytes, but generally has a lower operation speed than SRAM or DRAM.

[0004] Here, as shown in FIG.
The operation of a configuration in which a low-speed device 52 such as the above-mentioned I / O or flash ROM is directly connected to 51 will be described.

As shown in FIG. 7, in a read access, a CE ^* (chip enable) terminal ( ^* indicates low active) and an output enable terminal O
Access to the low-speed device 52 is possible while the E ^* (output enable) terminals (not shown) are both at L level. The period from when the address signal is output to when both the CE ^* terminal and the OE ^* terminal go to the H level is an access period t _ACN .

The low-speed device 52 has a slow response,
Data is output to the CPU bus (data bus) 53 some time after the E ^* terminal and the OE ^* terminal both become L level, and the output disable period after the CE ^* terminal and the OE ^* terminal both become H level. The output is made high impedance at the end of t _OZ . Therefore, READY
^It is necessary to delay the read processing of the CPU 51 by changing the logical level of the terminal to the L level at the timing shown. Then, the CPU 51 takes in the data on the CPU bus 53 during a period in which the read data in the access period t _ACN is valid.

However, when the write access continues thereafter, if the output disable period t _OZ is prolonged, the write data is output from the CPU 51 to the CPU bus 53 even though the read data exists on the CPU bus 53. You. For this reason, when the two data collide with each other on the CPU bus 53 and the two data have different polarities, a short circuit occurs and the CPU 51 is damaged.

As described above, it is difficult to directly connect the low-speed device 52 to the high-speed CPU 51.
The access of the CPU 51 is controlled using the following interface circuit.

In this example, as shown in FIG. 8, a flash ROM 54 is used as the low-speed device 52. As described above, the flash ROM 54 electrically collects data by a chip or stores several tens of Kbytes in one chip.
It can be erased as a unit.

A buffer 55 for bidirectional data transfer is provided between the CPU 51 and the flash ROM 54. The buffer 55 is connected to the C
It is connected to the PU 51 and to the flash ROM 54 via the low-speed bus 56. This buffer 55
The direction of data transfer is switched by the PU 51, and the output is controlled by the control circuit 57. The time required for the output of the buffer 55 to become high impedance is sufficiently shorter than that of the flash ROM 54.

The control circuit 57 performs weight control of the CPU 51, operation control of the flash ROM 54, and the like. Also,
The CPU 51 is directly connected to a high-speed memory 58 such as an SRAM via a CPU bus 53.

The operation of the system configured as described above will be described.

As shown in FIG. 9, at the time of read access, the flash ROM 54 stores the CE ^* terminal and the OE ^*
The read data is output to the low-speed bus 56 some time after the terminals have both become L level. The buffer 55 outputs an output control signal BCON ^* output from the control circuit 57 at L level.
At the time of the level, the read data is transferred to the CPU bus 53. Since this read data passes through the buffer 55, it is transferred to the CPU bus 53 with a slight delay. Then, the CPU 51 sets the buffer 55 in the access period t _ACN .
During the period during _which the read data is valid in the access period t _ACNN to which the delay time t _BF due to
3. Take the data in 3.

In the initial stage of the write access following the read access, the output of the flash ROM 54 has not been set to the high impedance yet, so that the read data is output to the low-speed bus 56 although it is uncertain. Then, the CPU 51 transfers the write data to the CPU bus 5.
3, the data transfer by the buffer 55 is stopped because the output control signal BCON ^* is at the H level. Thereafter, when the output control signal BCON ^* changes to the L level, the buffer 55 transfers the write data from the CPU bus 53 to the low-speed bus 56. The access period t _{ACNN at} this time is a value obtained by adding the delay time t _BF by the buffer and the period t _OZN from the start of the output of the write address until the output of the flash ROM 54 becomes high impedance to the access period t _ACN .

As described above, by controlling the read access and the write access to the flash ROM 54 via the buffer 55, it is possible to prevent a collision between the two data on the bus.

[0016]

However, in the above configuration, the read data and the write data are stored in the buffer 55.
, A delay (delay time t _BF ) occurs in the data transfer, and there is a disadvantage that access is delayed. In addition, when a read access is performed in the page mode in which the flash ROM 54 is continuously accessed, a delay is caused by the buffer 55 for each read access, so that the delay is accumulated and the access becomes very slow.

A low-speed device (flash ROM)
Are provided, a buffer 55 is provided for each low-speed device.
Must be provided, and the circuit configuration must be complicated. For this reason, the number of components increases, which leads to an increase in system cost and an increase in the mounting area of each component.

The present invention has been made in view of the above circumstances, and has as its object to provide a configuration in which a CPU and a low-speed device can be directly connected without causing data collision and a reduction in access speed. I have.

[0019]

In order to solve the above-mentioned problems, a CPU according to the present invention sets an access specified value that specifies an access space of a low-speed device for each low-speed device, and sets the CPU to the low-speed device. Access space defining means for setting a delay value indicating a time for delaying the write access together with the access specified value when performing a write access subsequent to a read access; When the CPU recognizes that the access is an access, delay control means for delaying write access based on the delay value corresponding to the address space to be accessed is provided. The access space defining means may use a circuit having a function of defining an access space, such as a memory management unit which is often provided in the CPU in recent years.

In the above configuration, when the CPU recognizes the write access following the read access (in terms of hardware) at the time of transition from the read access to the write access, the delay value corresponding to the accessed address space becomes:
It is extracted from the access space defining means by the delay control means. Then, the write access is delayed based on the delay value. Thus, when write access continues after read access, data collision between the two accesses can be prevented. Further, since it is not necessary to provide an interface circuit for delaying the write access between the CPU and the low-speed device, the number of components can be reduced.

According to another aspect of the present invention, there is provided a memory control system comprising: the CPU according to claim 1;
A semiconductor memory circuit that operates in a page mode that can be accessed continuously is provided as the low-speed device.

In this configuration, since the above-described access is applied to the semiconductor memory circuit that can operate in the page mode, the access speed can be further increased when the read access is continuously performed in the page mode. . Specifically, in each read access except the last read access, the write access does not continue, so that the read data is normally transferred to and from the CPU, and only the last read access is performed using the CPU of claim 1. The same access as is performed. Therefore, only the delay in the final read access occurs, and the increase in the access time in the entire read access is greatly suppressed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 3, the memory control system according to this embodiment has a CPU 1, a flash ROM 2
And a high-speed memory 3. The CPU 1 is connected to a flash ROM via a CPU bus 4 as a data bus.
2. It is directly connected to the high-speed memory 3 and the like.

Flash ROM 2 as low-speed device
Is an RO that can electrically erase data as described above.
M, which is generally slower in operation speed than SRAM or DRAM. The flash ROM 2 can operate in a so-called page mode in which data is read and written continuously (at high speed) in response to continuous access. On the other hand, the high-speed memory 3 is an SRAM,
The memory is composed of a DRAM or the like, and is capable of high-speed operation that does not hinder access speed even when directly connected to the high-speed CPU 1.

The low-speed device referred to here is a CP.
This is a device with a low access speed that cannot respond to U1 access. Although not shown, the present memory control system includes an I / O as a low-speed device, and this I / O is also connected to the CPU 1 via the CPU bus 5.

As shown in FIG. 1, the CPU 1 incorporates a memory management unit (hereinafter, referred to as MMU) 11 and an access control circuit including the MMU 11.

A general MMU is provided for managing (selecting) a large memory space by expanding the address space when a memory space larger than the address space (access space) of the CPU is required. ing. The address space is expanded by supplementing an upper address that is insufficient for specifying the address of the large-capacity memory with an output of a register or the like.

More specifically, for example, the memory space is divided into several segments, and a register of the number of bits allocated to the upper address of the segment is arranged in the I / O space corresponding to each segment. Is switched based on the I / O instruction of the CPU to switch the address of the extended address. There is also a method of associating both addresses in a table format in order to convert a logical address (virtual address) of the CPU into an extended physical address. In this manner, the MMU can define a memory space for each I / O space.

The MMU 11 used in the present embodiment also has the above-described functions. For example, pages P _{1 to} P _n for defining a logical address and a corresponding physical address for each memory segment in a memory space. It has. MMU1 as access space defining means
1 includes registers IDL _{1 to} I L in each of pages P _{1 to} P _n.
DL _n is added. Register IDL _{1 to} IDL _n
Sets a delay value representing a time for delaying the write access when the CPU 1 performs a write access following a read access to the flash ROM 2, for example, as a clock number corresponding to the delay time. Therefore, when the same kind of access (read access or write access) continues, it is not necessary to delay the write access.
The number of clocks set to DL _i (i = 1 to n) is zero.

In the present embodiment, it is only necessary that a delay value (the number of clocks of a clock CLK described later) can be associated with a logical address. A configuration other than the unit having the above function may be used. For example, MM
If you do not require U11, as shown in FIG. 2, now each a pair of registers IDL ₁ ~IDL _n, register SPC ₁ to S defining a logical address (address space)
Even _if PCn is provided in CPU 1, the same effect as the above configuration can be obtained.

However, in recent years, a high-speed CP with a built-in MMU
U has become widespread, and by using such an MMU as described above, the object of the present invention can be easily achieved without major changes.

The access control circuit includes a NAND gate 12, an inverter 13, a JK flip-flop 14, a counter 15, a comparator 16, and an AND gate 17 in addition to the MMU 11. The logic circuit section 18 composed of these logic circuits has a function as delay control means.

Read access signal RD and write access signal WT are input to NAND gate 12.
The read access signal RD is a signal indicating that the current access is a read access at an H level, and the write access signal WT is a signal indicating that the current access is a write access at an H level. Both access signals RD and WT are signals generated inside the CPU 1. When a write access follows a read access, as shown in FIG. 4, both access signals RD and WT
Have overlapping H-level periods. Thus, during a period when both access signals RD and WT overlap, the NAND gate 12 outputs an L-level read-write signal RW ^* indicating that write access follows read access.

The read / write signal RW ^* is inverted by the inverter 13 and input to the J terminal of the JK flip-flop 14 and the R (reset) terminal of the counter 15.
Then, since the JK flip-flop 14 is set, the output of the Q ^* terminal changes from H level to L level.
On the other hand, a counter 15 which is a 4-bit binary counter
Counts the number of clocks CLK externally supplied to the CPU 1 when reset by the read-write signal RW ^* . The 4-bit count data output from the counter 15 is provided to the comparator 16.

In the MMU 1, a delay value (the number of clocks) corresponding to the address of the data to be written in the next write access is extracted from any of the registers IDL _{1 to} IDL _n and supplied to the comparator 16. The comparator 16 compares the data of the delay value with the above-mentioned count data sequentially inputted, and outputs a coincidence detection signal (H level) from the EQ terminal when both coincide with each other. give. As a result, the JK flip-flop 14 is reset, and the output of the Q ^* terminal changes from L level to H level.

The AND gate 17 receives an inverted output signal from its Q ^* terminal and an access control signal NXTACS for instructing the start of the next access. The access control signal NXTACS is generated inside the CPU 1 and is directly output to the outside of the CPU 1 as shown by a broken line in a configuration in which the access control circuit is not provided in the CPU 1 as described above. However, in the CPU 1 provided with the access control circuit, since the inverted output signal is at the L level only for the period T of the predetermined number of clocks, the access control signal NXTACS is
By passing through the gate 17, it is output as a delayed access control signal NXTACS '.

The reset signal RST ^* input to the R (reset) terminal of the JK flip-flop 14 is normally generated inside the CPU 1 when initialization such as power-on is required.

Here, the operation of the present memory control system when a read access is followed by a write access will be described.

As shown in FIG. 5, in the read access, both the CE ^* terminal and the terminal OE ^* (not shown) are at L level, as in the above-described conventional configuration (see FIGS. 6 and 7). Access to the flash ROM 2 is possible during a certain time. When the CE ^* (OE ^* ) terminal changes to the L level and the access period t _ACN ends, the flash R
Since the OM 2 has a slow response, the OM 2 outputs data to the CPU bus 4 some time after the CE ^* terminal (OE ^* ) terminal goes low. Then, the CPU 1 sets the access period t
Immediately before the end of _ACN , the logic level of the READY ^* terminal becomes L
While the level is at the level, the data on the CPU bus 4 is fetched.

Since the write access following the read access is delayed as described above, the flash RO is applied to the CPU bus 4 at the end of the output disable period t _OZ.
After the output of M2 becomes high impedance, CPU
Write data is output from 1 (shown by a solid line in FIG. 5). Therefore, the collision between the read data and the write data as shown by the broken line in FIG.

In this embodiment, as described above, the collision between read access and write data is prevented by delaying the start of the write access by the access control circuit only when the read access is followed by the write access. Can be prevented. Further, since the access control circuit is provided inside the CPU 1, the number of parts can be reduced as compared with the conventional configuration (see FIG. 8) in which data is exchanged between the CPU and the low-speed device via the buffer. it can. As a result, the cost and the mounting area of the memory control system can be reduced.

In this embodiment, the delay time of the write access by the access control circuit can be suppressed to a necessary minimum, so that the access speed can be made equal to that of the above-described conventional configuration (see FIG. 8) at a minimum. . When a write access is performed after a continuous read access in the page mode, the write access is delayed between the last read access and the subsequent write access, as described above. Can be minimized. Therefore, it is possible to eliminate the inconvenience that the delay due to the buffer is accumulated for each read access as in the above-described conventional configuration using the buffer.

In this embodiment, the CPU 1
Has been described only for the flash ROM 2, but the present invention is not limited to this.
The same effect can be obtained in the case of access. However, I /
Since O is not a memory, the page mode cannot be applied and the MMU 11 cannot be used.

[0045]

As described above, the CPU according to the present invention has:
An access definition value that defines an access space of a low-speed device is set for each low-speed device, and a delay that represents a time for delaying the write access when the CPU performs a write access following a read access to the low-speed device. An access space defining means for setting a value together with the access prescribed value; and when the CPU recognizes that the access to the low-speed device is a write access following a read access, the access space defining means is configured based on the delay value corresponding to the address space to be accessed. And delay control means for delaying write access.

Thus, when a write access follows a read access, data collision between the two accesses can be prevented. Further, since there is no need to provide an interface circuit for delaying write access between the CPU and the low-speed device, the number of components can be reduced.

Therefore, it is possible to improve the speed and reliability of the access to the low-speed device by the CPU, and it is possible to greatly reduce the number of components.

A memory control system according to the present invention comprises the CPU according to claim 1 and a semiconductor memory circuit operating in a page mode which can be accessed continuously as the low-speed device.

As a result, only the final read access
Since the same access is performed as when the CPU is used, the delay included in the entire read access time can be significantly reduced as compared with the conventional configuration. Therefore, similarly to the above-described CPU, not only the speed and reliability of the access to the low-speed device of the CPU can be improved, but also the access speed of the low-speed semiconductor memory circuit in the page mode can be greatly improved. Is played together.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory control system according to an embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a configuration of an access control circuit built in a CPU in the memory control system.

FIG. 3 is a block diagram showing a configuration of a register provided in place of an MMU in the access control circuit.

FIG. 4 is a time chart showing an operation of the access control circuit.

FIG. 5 is a time chart showing the operation of the memory control system.

FIG. 6 is a block diagram showing a configuration of a conventional CPU system.

FIG. 7 is a time chart illustrating an operation of the CPU system of FIG. 6;

FIG. 8 is a block diagram showing a configuration of another conventional CPU system.

FIG. 9 is a time chart illustrating an operation of the CPU system of FIG. 8;

[Explanation of symbols]

1 CPU 2 Flash ROM (low-speed device, semiconductor memory circuit) 11 MMU (access space defining means) 18 Logic circuit section (delay control means)

Claims (2)

[Claims] An access definition value for defining an access space of a low-speed device is set for each low-speed device.
When the PU performs a write access following a read access to the low-speed device, an access space defining means for setting a delay value indicating a time for delaying the write access together with the access specification value; And the delay control means for delaying the write access based on the delay value corresponding to the address space to be accessed when the CPU recognizes that the write access is the write access following the read access. CPU. 2. A memory control system comprising: the CPU according to claim 1; and a semiconductor memory circuit operating in a page mode that can be accessed continuously as the low-speed device.