JP2000099171A - Power source circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To eliminate the need for a reference voltage generation circuit. A booster circuit receives a power supply voltage Vd and generates a voltage Vc higher than the power supply voltage;
A depletion-type NMOS transistor 15 in which c is the drain and the power supply voltage Vd is applied to the gate is provided, and a load circuit 17 is connected to the source of the transistor 15 as an output terminal 16. A voltage Vo higher than the power supply voltage Vd by the threshold value of the transistor 15 is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit capable of stably generating a voltage higher or lower than a predetermined voltage with a simple circuit.

[0002]

2. Description of the Related Art Conventionally, as a power supply circuit for obtaining a stable boosted voltage, as shown in FIG.
2 and the power supply terminal 31
A booster circuit 33 that generates a voltage higher than the voltage of
The boosted output terminal 34 of the booster circuit 33 is connected to the power supply terminal 36 of the reference voltage generator 35, connected to the drain of an enhancement type NMOS transistor 37, and the gate of the transistor 37 is connected to the reference of the reference voltage generator 35. A voltage output terminal 38 is connected, a source of the transistor 37 is connected to an output terminal 39, and a load circuit 40 is connected thereto.

Here, the power supply voltage of the power supply terminal 31 is Vd,
Assuming that the threshold voltage of the transistor 37 is Vt, the pinch-off voltage is Vp, the voltage of the boosted output terminal 34 is Vc, the reference voltage output to the reference voltage output terminal 38 is Vr, and the voltage output to the output terminal 39 is Vo, The output voltage Vo is as follows: Vo = Vr−Vt (1)

If the boosted voltage Vc at this time is set so that Vc> Vo + Vp = Vr−Vt + Vp (2), the transistor 37 operates in the saturation region, so that the load current flowing through the load circuit 40 and the power supply voltage Vd , The output voltage Vo holds the voltage represented by the above equation (1) and the transistor 37 operates as a three-terminal regulator due to the saturation characteristics of the transistor 37.

[0005]

However, in this power supply circuit, the transistor 37 is operated as a three-terminal regulator, and the output voltage Vo is set to ΔV higher than the power supply voltage Vd.
In order to generate a stable reference voltage Vr higher than the power supply voltage Vd, Vr> Vd + Vt + ΔV (3)
Was needed.

Further, in this reference voltage generating circuit 35, in order to generate a stable reference voltage Vr higher than the power supply voltage Vd, the power supply voltage Vd cannot be directly input as the power supply voltage, and the boosted voltage Vc is not supplied as the power supply voltage. Must be input as voltage.

However, since the boosted voltage generally has a power supply ripple generated by the circuit operation in the boosting process, the ripple component superimposed on the boosted voltage Vc is the reference voltage Vc.
When r appears, the effect also appears on the output voltage Vo, and the stability of the output voltage Vo deteriorates.

For this reason, conventionally, the reference voltage generating circuit 3
As No. 5, a circuit that uses a bandgap or the like to generate a reference voltage using a complicated circuit so as not to be affected by the power supply voltage must be used.

The present invention has been made in view of the above points, and an object of the present invention is to provide a power supply circuit which does not require a reference voltage generation circuit having a complicated design.

[0010]

According to a first aspect of the present invention, there is provided a booster circuit for receiving a first voltage and generating and outputting a voltage higher than a high potential side voltage of the first voltage. ,
A depletion-type first NMOS in which an output voltage of the booster circuit is applied to a drain and the high potential side voltage is applied to a gate;
A first NMOS transistor having a source connected to the output terminal and a load circuit connected to the output terminal.

According to a second aspect of the present invention, in the first aspect, a depletion-type second NMOS transistor in which an output voltage of the booster circuit is applied to a drain and the high-potential side voltage is applied to a gate is provided. The configuration is such that the gate of the NMOS transistor is switched to be connected to the source of the second NMOS transistor.

In a third aspect based on the second aspect, the second NMOS transistor is configured such that the high potential side voltage is applied to the gate, the output voltage of the booster circuit is applied to the drain, and the source is the next gate. And a depletion type having at least a final stage in which a gate is connected to the source of the preceding stage, an output voltage of the booster circuit is applied to the drain, and a source is connected to the gate of the first NMOS transistor. And was replaced with an NMOS transistor.

According to a fourth aspect of the present invention, there is provided a booster circuit for receiving a second voltage and generating and outputting a voltage lower than a low potential side voltage of the second voltage, and an output voltage of the booster circuit having a drain connected to the low potential The first type of depletion type in which the side voltage is applied to the gate
The first PMOS transistor
The source of the transistor is connected to the output terminal, and a load circuit is connected to the output terminal.

In a fifth aspect based on the fourth aspect, a depletion-type second PMOS transistor in which the output voltage of the booster circuit is applied to the drain and the low-potential-side voltage is applied to the gate is provided. The gate of the PMOS transistor is switched to be connected to the source of the second PMOS transistor.

In a sixth aspect based on the fifth aspect, the second PMOS transistor is configured such that the low-potential-side voltage is applied to the gate, the output voltage of the booster circuit is applied to the drain, and the source is the next-stage gate. And a final stage having at least a gate connected to the source of the preceding stage, a drain connected to the output voltage of the booster circuit, and a source connected to the gate of the first PMOS transistor. And replaced with a PMOS transistor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG.
FIG. 1 is a diagram showing a power supply circuit 10 according to a first embodiment of the present invention. The power supply circuit 10 includes a power supply terminal 11 and a ground terminal 1.
And a booster circuit 13 for generating a voltage higher than the voltage of the power supply terminal 11 by applying a voltage applied between the booster circuit 2 and the booster output terminal 14 of the booster circuit 13 to the drain of a depletion type NMOS transistor 15. The power supply terminal 11 is connected to the gate of the transistor 15, the source is connected to the output terminal 16, and the load circuit 17 is connected to the terminal 16.

The voltage of the power supply terminal 11 is Vd, the threshold voltage of the transistor 15 is -Vtn (the polarity of the threshold voltage of the depletion transistor is opposite to that of the enhancement transistor), and the pinch-off voltage of the transistor 15 is Vp. , The boosted voltage of the boosted output terminal 14
c, assuming that the output voltage of the output terminal 16 is Vo, the output voltage Vo is Vo = Vd + Vtn (4), which is higher than the power supply voltage Vd by the threshold voltage Vtn of the transistor 15.

If the boosted voltage Vc is set to Vc> Vd + Vtn + Vp (5), the output voltage Vo is kept stable, and the transistor 15 operates as a three-terminal regulator.

As described above, in the present circuit, the output voltage Vo becomes "Vd + Vtn" as shown in the equation (4). One power supply voltage Vd is a stable voltage, and the other voltage Vtn is a fixed value that does not change. Therefore, if the relationship of the above equation (5) is satisfied, the output voltage Vo changes with the voltage change of the boosted voltage Vc. Is always output as a stable voltage. In this circuit, a depletion-type NMOS transistor is used, so that a reference voltage generation circuit which is necessary in the conventional circuit is not required.

FIG. 1B is a diagram showing the circuit configuration of the booster circuit 13. The switches 41 to 44, the capacitors 45,
46, a power supply voltage Vd input between the power supply terminal 11 and the ground terminal 12.
Is output to the boosted output terminal 14.

The operation divides one operation cycle into two timings, and switches 42, 4
Turn on 3 and turn off switches 41 and 44,
The capacitor 45 is charged with the voltage Vd, and the switches 42 and 43 are turned off and the switches 41 and 4 are turned off at the next timing.
4 is turned on, and a voltage 2Vd obtained by adding the voltage Vd of the power supply terminal 11 and the voltage Vd charged in the capacitor 45
Is output to the boosted output terminal 14 and held by the capacitor 46.

FIG. 2 shows a power supply circuit 10 'according to a modification of the first embodiment.
An S transistor 18 is further added. That is, the gate of the transistor 18 is connected to the power supply terminal 11,
The drain is connected to the boost output terminal 14 and the source is connected to the gate of the transistor 15.

In the power supply circuit 10 ', the transistor 1
8 has a voltage “Vd + V higher than the voltage Vd of the power supply terminal 11 by the threshold voltage Vtn of the transistor 18.
tn "is output, and a voltage" Vd + 2Vtn "higher than the voltage" Vd + Vtn "by the threshold voltage Vtn of the transistor 15 is output to the source of the transistor 16. That is, a voltage higher by 2 Vtn than the power supply voltage can be output to the output terminal 16. However, at this time, it is necessary to satisfy the condition of “Vc> Vd + 2Vtn + Vp”.

If only a plurality of NMOS transistors of the same depletion type as the transistor 18 are connected in series so that the drain is commonly connected to the boosted output terminal 14 and the gate at the subsequent stage is connected to the source at the previous stage, the number is reduced. Assuming that n, “Vd + (n + 1) V
tn ”voltage is obtained. However, in this case, “Vc> V
d + (n + 1) Vtn + Vp ”.

[Second Embodiment] FIG. 3A is a diagram showing a power supply circuit 20 according to a second embodiment. The power supply circuit 20 is a circuit that generates a stable voltage lower than the GND level. The power supply circuit 20 receives a voltage applied between the power supply terminal 21 and the ground terminal 22 and outputs a voltage lower than the voltage of the ground terminal 22. A booster circuit 23 for generating the voltage is provided, and a booster output terminal 24 of the booster circuit 23 is connected to a depletion type PMOS.
The transistor 25 is connected to the drain, the gate of the transistor 25 is connected to the ground terminal 22, the source is connected to the output terminal 26, and the load circuit 2 is connected to the terminal 26.
7 are connected.

The operation is the same as that of the circuit shown in FIG. 1A. The voltage of the power supply terminal 21 is Vd, the threshold voltage of the transistor 25 is Vtp, the pinch-off voltage is Vp, and the boosted voltage of the boosted output terminal 24 is Is −Vc and the output voltage of the output terminal 26 is Vo, the output voltage Vo becomes −Vtp (6), and the voltage V is lower than the potential of the ground terminal 22 by Vtp.
o is obtained at the output terminal 26.

If the boost voltage Vc is set to Vc <-Vtp-Vp (7), the output voltage Vo is kept stable, and the transistor 25 operates as a three-terminal regulator.

FIG. 3B is a diagram showing the circuit configuration of the booster circuit 23. The switches 51 to 54, the capacitors 55,
And a power supply voltage Vd input between the power supply terminal 21 and the ground terminal 22.
Is output to the boosted output terminal 24.
The operation is the same as that of the booster circuit 13 shown in FIG.

FIG. 4 shows a power supply circuit 20 'according to a modification of the second embodiment.
An S transistor 28 is further added. That is, the gate of the transistor 28 is connected to the ground terminal 22,
The drain is connected to the boost output terminal 24 and the source is connected to the gate of the transistor 25.

In the power supply circuit 20 ', the transistor 2
A voltage "-Vtp" lower than the voltage of the ground terminal 22 by the threshold voltage Vtn of the transistor 18 is output to the source of the transistor 8, and the source of the transistor 26 is connected to the source of the transistor 15 more than the voltage "-Vtp". A voltage “−2Vtp” lower by the threshold voltage Vtp is output. That is, a voltage lower by 2 Vtp than the ground voltage can be output to the output terminal 26. However, in this case, it is necessary to satisfy the condition of “Vc <−2Vtp−Vp”.

If a plurality of PMOS transistors of the same depression type as the transistor 28 are connected in series so that the drain is commonly connected to the boosted output terminal 24 and the gate at the subsequent stage is connected to the source at the previous stage, the number is reduced. Assuming n, the output terminal 26 has "-(n + 1) Vtp"
Is obtained. However, in this case, “Vc <− (n
+1) Vtp−Vp ”.

[Other Embodiments] In the first embodiment, the power supply terminal 11 is used as a terminal to which another arbitrary voltage is input, and the transistor 15 is connected to the transistor 15 more than the higher voltage of the arbitrary voltage. Threshold voltage Vtn (or 2Vtn,
A configuration in which a voltage higher by (n + 1) Vtn) is applied to the load circuit 17 may be employed. Further, in the second embodiment, the ground terminal 22 is used as a terminal to which another arbitrary voltage is input, and the threshold voltage Vtp (or 2Vtp, (n + 1) of the transistor 25 is higher than the lower voltage of the arbitrary voltage. ) Vt
A configuration in which a voltage lower by p) is applied to the load circuit 27 may be employed.

[0033]

As described above, according to the present invention, by using a depletion type MOS transistor, the same boosting and voltage stabilization as in the conventional circuit can be achieved without using the reference voltage generating circuit required in the conventional circuit. This has the advantage that the power supply circuit can be greatly simplified and downsized.

[Brief description of the drawings]

FIG. 1A is a circuit diagram of a power supply circuit according to a first embodiment of the present invention, and FIG. 1B is a circuit diagram of a booster circuit.

FIG. 2 is a circuit diagram of a modified example of the power supply circuit according to the first embodiment.

FIG. 3A is a circuit diagram of a power supply circuit according to a second embodiment of the present invention, and FIG. 3B is a circuit diagram of a booster circuit.

FIG. 4 is a circuit diagram of a modified example of the power supply circuit according to the second embodiment.

FIG. 5 is a circuit diagram of a conventional power supply circuit.

[Description of References] 10, 10 ': power supply circuit, 11: power supply terminal, 12: ground terminal, 13: booster circuit, 14: booster output terminal, 15: depletion type NMOS transistor, 16: output terminal, 17: load Circuit, 18: NMO of depletion type
S transistors 20, 20 ': power supply circuit, 21: power supply terminal, 22: ground terminal, 23: booster circuit, 24: booster output terminal, 25: depletion type PMOS transistor, 26: output terminal, 27: load circuit, 28 : Depletion type PMO
S transistor 30: power supply circuit, 31: power supply terminal, 32: ground terminal, 3
3: boost circuit, 34: boost output terminal, 35: reference voltage generation circuit, 36: power supply terminal, 37: enhancement type N
MOS transistor, 38: reference voltage output terminal, 39:
Output terminal, 40: load circuit 41-44: switch, 45, 46: capacitor 51-54: switch, 55, 56: capacitor

Claims (6)

[Claims] A booster circuit for receiving a first voltage and generating and outputting a voltage higher than a high-potential-side voltage of the first voltage; an output voltage of the booster circuit being a drain and the high-potential-side voltage being a gate; And a depletion-type first NMOS transistor applied to the power supply circuit, wherein a source of the first NMOS transistor is connected to an output terminal and a load circuit is connected to the output terminal. 2. A depletion-type second NMOS transistor in which an output voltage of the booster circuit is applied to a drain and the high-potential-side voltage is applied to a gate, wherein the first NMOS transistor is provided.
The power supply circuit according to claim 1, wherein the gate of the S transistor is switched to be connected to the source of the second NMOS transistor. 3. The second NMOS transistor comprises: a first stage in which the high-potential-side voltage is applied to a gate, an output voltage of the booster circuit applied to a drain, and a source connected to the next gate; A depletion-type NMO having at least a terminal connected to the source of the booster circuit, a drain connected to the output voltage of the booster circuit, and a source connected to the gate of the first NMOS transistor.
3. The power supply circuit according to claim 2, wherein the power supply circuit is replaced with an S transistor. 4. A booster circuit for receiving a second voltage to generate and output a voltage lower than a low potential side voltage of the second voltage, an output voltage of the booster circuit being a drain, and the low potential side voltage being a gate. And a depletion-type first PMOS transistor applied to the power supply circuit, wherein a source of the first PMOS transistor is connected to an output terminal and a load circuit is connected to the output terminal. 5. A depletion-type second PMOS transistor in which an output voltage of said booster circuit is applied to a drain and said low-potential-side voltage is applied to a gate, wherein said first PMOS transistor is provided.
The power supply circuit according to claim 4, wherein the gate of the S transistor is switched to be connected to the source of the second PMOS transistor. 6. The second PMOS transistor comprises: a first stage in which the low potential side voltage is applied to a gate, an output voltage of the booster circuit applied to a drain, and a source connected to the next gate; And a final stage in which the output voltage of the boosting circuit is applied to the drain and the source is connected to the gate of the first PMOS transistor.
The power supply circuit according to claim 5, wherein the power supply circuit is replaced with an S transistor.