JP2000091565A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save labor in a manufacturing process and greatly reduce the manufacturing cost by omitting a photomask process which was necessary for forming a thick oxide film and a source region. SOLUTION: In this method, after a gate electrode 13 is formed selectively, a channel region 16 and an impurity diffused region 17A are formed and an NSG film 15A is further formed over the entire surface, and a source region is formed by dividing the impurity diffused region 17A into parts at the same time as with formation of a gate contact 0P. Therefore, the photomask process which was necessary for forming a source region can be eliminated. Therefore, a photomask is required in only three processes of formation of a patterning mask for forming a gate electrode, formation for forming an opening 0P for making contact with a gate electrode (formation of a recessed part 0B1 for forming a source region) and the mask formation for patterning a wiring layer. Since only three photomasks need to be used in all in this way, a mask process and a process involved therein can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a reduction in the number of mask steps in a process for manufacturing a power MOSFET and a structure for suppressing parasitic capacitance generated in this process.

[0002]

2. Description of the Related Art A conventional power MOSFET and a method of manufacturing the same will be described below with reference to the drawings. FIG.
FIG. 6 is a cross-sectional view showing a structure of a conventional power MOSFET, and FIGS. 6 to 8 are cross-sectional views illustrating a method for manufacturing a conventional power MOSFET.

In a conventional power MOSFET, as shown in FIG. 5, a drain layer 1A composed of an n- type epitaxial layer is formed on an n + type semiconductor substrate 1, and a p-type impurity A channel region 6 formed by diffusion is formed. At the center thereof, a body contact region 8 formed by diffusion of p + -type impurities is formed. A source region 7 formed by n + -type impurity diffusion is provided on the surface layer of the channel region 6 so as to surround the body contact region 8. I have.

A thick insulating film 3 is provided in a region where a pad electrode 10 described later is formed.

Further, a gate insulating film 2 and a gate electrode 4 are sequentially formed on the channel region 6 so as to overlap the channel region 6 and a part of the source region 7.

In addition, the PS is so formed as to cover the gate electrode 4.
A G (Phospho-Silicate Glass) film 5 is formed.
The PSG film 5 is provided with an opening in a part of the region where the insulating film 3 is formed, and a pad electrode 10 for making contact with the gate electrode 4 exposed from the opening is formed in the opening and its periphery. Is formed.

On the source region 7 and the body contact region 8, a source electrode wiring 9 for making contact with the source region 7 is formed.

The manufacturing process of the above power MOSFET will be described below with reference to FIGS.

First, an n- type drain layer 1A is formed on an n + type semiconductor substrate 1 by epitaxial growth. Next, a thick oxide film 3 is formed thereon, a resist film is selectively formed by a photolithography process, and the resist film is patterned using the first mask to form an insulating film 3 for a pad electrode. Then, an oxide film to be the gate insulating film 2 is formed again. Next, a polysilicon film 4A is formed on the entire surface. (See FIG. 6 above.) Hereinafter, a region where a thick oxide film is formed is referred to as a peripheral region.

Next, a photoresist film is formed on the polysilicon film 4A, and the polysilicon layer and the oxide film are etched using the patterned resist film as a second mask to form a gate as shown in FIG. An insulating film 2 and a gate electrode 4 are formed. Here, the gate electrode 4 is formed in a lattice shape. Hereinafter, a region where the gate electrode is formed in a lattice shape is referred to as a cell region.

Next, a p-type impurity is implanted using the gate insulating film 5 and the gate electrode 4 as a mask to form a channel region 6 in a part of the surface layer of the drain layer 1A. (Refer to FIG. 7 above.) Next, a photoresist (not shown) is applied again on the entire surface, and a third photoresist film is patterned by photolithography so as to be selectively formed at the center of the channel region 6. Using this as a mask, an n-type impurity is implanted into channel region 6 to form source region 7. Thereafter, the resist film is removed, a photoresist is applied again, and the photoresist is patterned so as to form an opening in the center, and then a new resist film (not shown) is used as a fourth mask to form a p-type impurity. Is implanted into channel region 3 to form body contact region 8. Next, the fourth resist film is removed to form a PSG film on the entire surface (see FIG. 8).

Thereafter, a resist film (not shown) is formed on the PSG film 5.
Patterning by photolithography so that an opening is formed in a peripheral region where pad electrodes are to be formed and in a partial region of the body region 8 and the source region 7.
Using this as the fifth mask, the PSG film 5 is etched and removed. Next, a metal such as aluminum is formed on the entire surface by vapor deposition or the like, and this is patterned by a sixth mask, and the source electrode 9 is insulated so as to be in contact with the exposed body region 8 and a part of the source region 7. By forming the pad electrodes 10 on the film 3 respectively, a power MOSFET having a structure as shown in FIG. 5 is formed.

[0013]

With respect to the planar type power MOSFET described above, 1) a mask forming step for forming a thick oxide film for the first bonding pad 2) patterning for forming a gate electrode 3) Step of forming resist mask for forming source region 7 (FIG. 8) 4) Step of forming resist mask for forming body region 8 (FIG. 8) 5) Source region 7 6) Photomask used in photolithography process for patterning in resist mask forming process for patterning pad electrode 10 and source electrode wiring 9 arrangement when forming contact hole in PSG film 8 Is required, so as many as six photomasks are required.

As a result, the number of masking steps and the steps accompanying the masking step become extremely large, and the manufacturing steps become complicated, resulting in a problem that the manufacturing cost is increased.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks. First, a gate insulating film, a conductor layer, and an insulating film are sequentially formed around a semiconductor chip. The number of masks can be reduced by one, a channel region and a first impurity region layer are formed using the gate electrode as a mask,
Then, the second insulating film corresponding to the central portion of the first impurity region layer and the gate contact region and / or the first
Forming a source region by etching the insulating film to form a removed region in which a central portion of the first impurity region is completely removed; forming a body contact region of one conductivity type through the removed region; When a metal is formed via a sidewall, it can be realized with a total of three masks.

Second, in the step of forming the removal region, an opening from which a gate electrode is removed is formed in a part of the peripheral region, so that the removal region EL is formed in the peripheral region without increasing the number of steps. Can be formed, and an increase in parasitic capacitance can be prevented.

Third, in the step of forming the sidewall, if the second insulating film located at the opening in the peripheral region is covered with a mask, the withstand voltage of the opening can be improved.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a planar type power MOSFET according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a sectional view illustrating the structure of a planar power MOSFET according to the embodiment of the present invention. FIGS. 1 to 4 illustrate a method of manufacturing the planar power MOSFET according to the embodiment. FIG.

Here, as an example, an N-type power MOS
A method of manufacturing an FET will be described. A P-type power MOSFET can be manufactured in a similar manner by changing the conductivity type.

In this power MOSFET, as shown in FIG. 4, a drain layer 11A consisting of an n- type epitaxial layer is formed on an n + type semiconductor substrate 11, and a p-type impurity diffusion A channel region 16 is formed. A concave portion OB1 is formed at the center thereof, and a source region 17 formed by n + type impurity diffusion is provided on the surface layer of the channel region 16 so as to surround the concave portion OB1.

In the vicinity of the source region 17 on the drain layer 11A, the gate insulating film 12, the gate electrode 13, and the NS
G films 14 are sequentially formed. On the side walls of the gate insulating film 12, the gate electrode 13, and the NSG film 14, a sidewall 18 also made of an NSG film is formed. The recess OB <b> 1 is formed such that its end coincides with the end of the source region 17. In addition, this recess O
A P ++ type body contact region BC is formed via B1.

The NS covering the gate electrode 13
An opening OP is formed in a part of the G film 14, and the NSG film on the right side of the opening OP has a removal region EL.

Further, a source electrode wiring 19 made of AlSi is formed so as to cover the concave portion OB1 formed in the center of the channel region 16, and a source electrode wiring 19 made of AlSi is formed.
The gate electrode wiring 20 for making contact with the gate electrode 13 through the opening OP of the NSG film 14 described above.
Are formed on the NSG film 14 described above.

Although not shown in FIG. 4, if necessary, as shown in FIG.
The recess OB2 formed at the same time as the recess 1 may be formed at the same time, and the recess 0B2 may be employed as a channel stopper described later.

On the back surface of the semiconductor substrate 11, a drain electrode D is formed.

Next, the manufacturing process of the power MOSFET will be described.

First, as shown in FIG. 1, an n + type semiconductor substrate 11 is formed.
An n @--type drain layer 11A is formed thereon by epitaxial growth. Next, an oxide film 12A, a polysilicon film 13A, and an NSG film 1 which will later become the gate insulating film 12
4 is deposited.

Then, as shown in FIG. 2, a photoresist film (not shown) is formed on the NSG film 14, and the patterned resist film is used as a first mask to form the NSG film 14,
The gate insulating film 12 and the gate electrode 13 are formed by etching the polysilicon layer 13A and the oxide film 12A. Here, the gate electrode is formed in a lattice shape. Here, the removal region EL is formed simultaneously with the patterning of the gate electrode 13. This removed region is a feature of the present invention, and the gate electrode 1 formed in the peripheral region is formed.
3, provided to suppress an increase in parasitic capacitance generated by the gate insulating film 12 and the semiconductor layer.

Next, a channel region 16 is formed on the drain layer 11A by implanting and diffusing a p-type impurity using the gate insulating film 12, the gate electrode 13, and the NSG film 14 as a mask. After that, an n + -type impurity is implanted into the surface layer of the channel region 16 and n +
Form impurity diffusion region 17A is formed.

Thereafter, the NSG film 15A is formed again on the entire surface to obtain a structure as shown in FIG.

Next, a photoresist is applied and patterned by photolithography so that an opening is formed in a part of the formation region of the gate electrode 13.
Using the R2 as a second mask, the NSG films 14 and 15A are etched to form the openings OP and, at the same time, the recesses OB1 corresponding to the body contact regions BC.

As can be seen from FIG. 2, an NSG film 15A is formed on the body contact region BC, and the NSG film 1
4, 15A are formed in two layers.

The thickness of the gate electrode 13 and the impurity diffusion region 1
Ultimately, depending on the diffusion depth of 7A, the spacer 18
Is formed, the bottom of OB1 is etched deeper than the bottom of the source region, and the opening OP may be formed by exposing the poly-Si.

For example, the NSG film 15A is etched by PR2, the semiconductor layer is exposed in the concave portion OB1, and the NSG film 14 is exposed in OP, and then the mask PR is formed.
2 as a mask or by removing this mask NSG
Etching may be further performed using the film 15A as a mask, the gate material may be etched in the OP portion, and the OB1 may be etched deeper than the bottom of the source region.

Then, through the opening of the recess OB1, P
The ++ type body contact region BC is formed by, for example, ion implantation.

After that, the entire surface is etched back and NSG
N is applied to the side walls of the film 14, the gate electrode 13, and the gate insulating film 12.
A sidewall 18 made of the SG film 15 is formed. Also in this case, the concave portion OB1 of the channel region 16 and the gate contact OP are slightly etched. Therefore, in this step, finally, the gate material is etched in the OP portion, and at the same time, in the OB1, the gate material is etched deeper than the bottom of the source region. You may do it.

In any case, finally, the center of the n-type impurity diffusion region 17A is removed by the concave portion OB1.
Each of the n-type impurity diffusion regions is formed as a source region 17.

Here, a sidewall is also formed in the removal region EL, and the semiconductor layer is exposed.

Thereafter, AlSi is deposited and deposited on the entire surface by CVD or sputtering, and is patterned by
Exposed body contact region BC and source region 1
By forming a source electrode wiring 19 and a gate electrode wiring 20 for making contact with the gate electrode so as to be in contact with 7, a power MOSFET having a structure as shown in FIG. 4 is completed. Further, a drain electrode D is formed on the back surface of the semiconductor substrate.

Although not illustrated in the drawings, the removal region EL where the semiconductor layer is exposed is thereafter covered entirely with a passivation film (such as a Si3N4 film or a polyimide film), so that characteristic deterioration and short-circuiting occur. Problems such as are eliminated.

As described above, according to the method of manufacturing the semiconductor device according to the present embodiment, after the gate electrode 13 is selectively formed, the channel region 16 and the impurity diffusion region 1 are formed.
7A, an NSG film 15A is formed on the entire surface, and the impurity diffusion region 17 is formed simultaneously with the formation of the gate contact OP.
Since the source region is formed by dividing A, the photomask process required for forming the source region in the conventional example can be reduced.

Therefore, in the embodiment of the present invention, the steps requiring a photomask are: 1) a step of forming a patterning mask for forming a gate electrode (FIG. 2); and 2) a contact with the gate electrode. 3) Step of forming opening OP for forming (recess OB1 for forming source region) 3) Mask forming step for patterning wiring layer Only three steps are required.

As described above, in this embodiment, only three photomasks need to be used for convenience, and the number of masking steps and steps accompanying the masking steps are very large, unlike the conventional case using six photomasks. Further, it is possible to suppress the problem that the manufacturing process becomes complicated and the manufacturing cost increases.

By forming the recess OB2 at the same time as the formation of the recess OB1 as shown in FIG. 9, the OB2 can be used as a channel stopper for the current flowing from the lower layer of the gate electrode 13 to the periphery of the semiconductor chip.

Although the number of masks is increased by one, as shown in FIG. 10, if the removal region EL is covered with the photoresist PR during the etch back, the removal region EL is covered with the NSG film 15A, and the exposed region is exposed. Can be prevented. FIG. 10 shows this completed drawing, in which metal wiring is formed. Note that the OB2 shown in FIG. 9 may be formed here. In such a process, since two NSG films are formed in the peripheral region,
The shock at the time of bonding can be absorbed.

In the above description, NSG was used as the insulating film.
Although the films 14 and 15 are used, the PSG film described in the conventional example may be used. Reference numeral 14 denotes an NSG film (or a PSG film)
Thus, the reference numeral 15A may be a PSG film (or an NSG film).

[0048]

As described above, the omission of the thick oxide film and the photomask process required for forming the source region are omitted. Therefore, in the embodiment of the present invention, a photomask is required throughout all processes. The steps are: 1) a step of forming a patterning mask for forming a gate electrode 2) a step of forming an opening for making contact with the gate electrode 3) a step of forming a mask for patterning a wiring layer It is.

As described above, in this embodiment, it is only necessary to use three photomasks for convenience. Unlike the conventional method using six photomasks, the number of masking steps and the steps accompanying these steps can be reduced. This makes it possible to save labor in the manufacturing process and significantly reduce the manufacturing cost.

Further, by removing a part of the gate electrode located in the peripheral region and a gate insulating film under the part of the gate electrode, an increase in parasitic capacitance can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a power MOSFET according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a power MOSFET according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a power MOSFET according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the method for manufacturing the power MOSFET according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the structure of a conventional planar power MOSFET.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a conventional power MOSFET.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional power MOSFET.

FIG. 8 is a sectional view illustrating a method for manufacturing a conventional power MOSFET.

FIG. 9 shows a power M for explaining a modification of the manufacturing method of the present invention.
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 10 is a cross-sectional view of a power MOSFET illustrating a modification of the manufacturing method of the present invention.

FIG. 11 is a cross-sectional view of a power MOSFET illustrating a modification of the manufacturing method of the present invention.

Claims (3)

[Claims] A step of forming a drain layer of one conductivity type on a surface layer of a semiconductor substrate of one conductivity type, which is one component of a semiconductor chip; and a gate insulating film extending around the semiconductor chip on the drain layer. Forming a conductive layer and a first insulating film sequentially; and patterning the first insulating film, the conductive layer and the gate insulating film located in the cell region of the semiconductor chip to form a lattice comprising the conductive layer. Forming a channel region by implanting a reverse conductivity type impurity into a surface layer of the drain layer using the gate electrode as a mask, and forming a channel region on the channel region using the gate electrode as a mask. Forming a first impurity region layer of one conductivity type by injecting impurities of a conductivity type; forming a second insulating film on the entire surface; a central portion of the first impurity region layer and a gate contour The source region is formed by etching the second insulating film and / or the first insulating film corresponding to the source region to form a removed region in which the central portion of the first impurity region is completely removed, and the source region is formed through the removed region. Forming a one-conductivity-type body / contact region, forming a sidewall in the gate electrode, and forming a source electrode in the source region and a gate electrode in the gate contact region. A method for manufacturing a semiconductor device, comprising: 2. In the step of forming the removal region,
2. The method according to claim 1, wherein an opening from which a gate electrode is removed is formed in a part of the peripheral region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step of forming the sidewall, a second insulating film located at the opening in the peripheral region is covered with a mask.