JP2000091564A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to prevent the surface of a substrate from being contaminated without deteriorating element isolation in the case where spacers are respectively formed on the sidewalls of a gate electrode, and, at the same time, to make it possible to reduce damages to the substrate and moreover, to make it possible to manufacture a MOS field-effect transistor having favorable characteristics. SOLUTION: In a method of manufacturing a MOS FET having an LDD (lightly doped drain) structure, a polycrystalline Si film 4a and a WSix film 4b are formed on a p-type Si substrate 1 via a gate insulating film 3 and the films 4a and 4b are patterned to form a gate electrode 4 of a polycide structure. An Si3N4 film 7 which is used as a capping layer, is formed on the whole surface in such a way as to cover the upper surface of the electrode 4 and the sidewalls of the electrode 4. After SiO2 films 8 are formed on the film 7 as films for sidewall spacer formation, the films 8 are etched back by an RIE (reactive ion etching) method to form sidewall spacers 9 on the sidewalls of the electrode 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method suitable for manufacturing a MIS field-effect transistor having an LDD structure.

[0002]

2. Description of the Related Art Conventionally, in a MOS field effect transistor (hereinafter referred to as a MOSFET), a structure called an LDD (Lightly Doped Drain) has been proposed in order to alleviate an electric field near a drain region and improve hot electron resistance. Is widely adopted.

FIGS. 7 to 11 are sectional views for explaining a method of manufacturing a MOSFET having an LDD structure according to the prior art.

The conventional LDD-structure MOSF
In the ET manufacturing method, first, as shown in FIG.
A field insulating film 102 such as a silicon dioxide (SiO ₂ ) film is selectively formed on a surface of a p-type silicon (Si) substrate 101 by a LOCOS method to perform element isolation.
At this time, the p-type Si substrate 101 in the element isolation region
A p-type impurity such as boron (B), which has been introduced in advance by an ion implantation method or the like, diffuses therein, and a p ⁺ -type channel stop region (not shown) is formed below the field insulating film 102. You. Thereafter, a gate insulating film 103 made of a SiO ₂ film having a thickness of about 10 nm is formed on the surface of the active region surrounded by the field insulating film 102 by, for example, a thermal oxidation method.

Next, a polycrystalline Si film 104a is formed on the entire surface by, for example, a chemical vapor deposition (CVD) method. Next, in order to reduce the resistance value, the polycrystalline Si film 104a is heavily doped with an n-type impurity such as P by, for example, an ion implantation method. Next, on this polycrystalline Si film 104a, tungsten silicide (W
Forming a Si _x) film 104b. Then, patterning of these polycrystalline Si film 104a and the WSi _x film 104b in a predetermined shape. Thereby, the p-type Si substrate 101
Above, the polycrystalline Si film 104a and the WSi _x film 104 These patterned via a gate insulating film 103
b, a so-called polycide gate electrode 10
4 are formed.

[0006] Next, as shown in FIG.
4 is used as a mask, and n such as P is injected into the active region surrounded by the field insulating film 102 by ion implantation.
Doping with type impurities. Thereby, the gate electrode 10
4, n ⁻ -type layers 105 and 106 are formed in a self-aligned manner.

Next, as shown in FIG. 9, a predetermined thickness of S (side wall spacer) is formed as a film for forming a spacer (sidewall spacer) provided on the side wall of the gate electrode 104 by the CVD method.
An iO ₂ film 107 is formed on the entire surface.

Next, as shown in FIG. 10, the SiO ₂ film 107 is formed by reactive ion etching (RIE).
Etch back in the direction perpendicular to the surface of the mold Si substrate 101. The etch-back by the RIE method is performed until the surface of the p-type Si substrate 101 in the active region surrounded by the surface of the gate electrode 104 and the field insulating film 102 is exposed. As a result, sidewall spacers 108 made of SiO ₂ are formed on the sidewalls of the gate electrode 104.

Next, as shown in FIG. 11, using the sidewall spacer 108 and the gate electrode 104 as a mask, an active region surrounded by the field insulating film 102 is formed.
An n-type impurity such as arsenic (As) is doped at a high concentration by an ion implantation method. Thereafter, if necessary, annealing for electrically activating the implanted impurities is performed. As a result, an n ⁺ -type source region 109 and a drain region 110 are formed in a self-alignment manner with the sidewall spacer 108. These source region 109 and drain region 110 form side wall spacers 108.
N ⁻ -type low impurity concentration portions 109 a and 11
0a. These low impurity concentration portions 109a, 11
Oa is composed of n ⁻ -type layers 105 and 106, respectively.

After that, although not shown, after an interlayer insulating film such as a SiO ₂ film is formed on the entire surface by the CVD method,
A predetermined portion of the interlayer insulating film is removed by etching to form a contact hole reaching the source region 109 and the drain region 110. Next, after forming, for example, an Al film on the entire surface by a sputtering method or a vacuum evaporation method,
The l film is patterned into a predetermined shape by etching,
A source electrode and a drain electrode are formed. Next, a surface protection film is formed on the entire surface, and an n-channel MOS having an LDD structure is formed.
Complete the FET.

[0011]

However, the following problem arises in the conventional method of manufacturing a MOSFET having an LDD structure. Hereinafter, L according to this prior art
Regarding the problem of the manufacturing method of the MOSFET having the DD structure,
This will be described with reference to FIG.

That is, M of the LDD structure according to the prior art
In the manufacturing method of the OSFET, when the SiO ₂ film 107 is etched back to form the sidewall spacers 108 on the side walls of the gate electrode 104, the SiO ₂ film (SiO ₂ film) on the active region surrounded by the field insulating film 102 is formed. In order to stably etch off the film 107 and the gate insulating film 103), it is necessary to set appropriate over-etching. At this time, as shown in FIG. 12, SiO ₂
Since the field insulating film 102 made of is also considerably etched, there is a problem that the thickness of the field insulating film 102 decreases and the element isolation characteristics deteriorate. As a measure against this, the field insulating film 10 after the etch-back process is used.
If the field insulating film 102 is formed thick at the time of selective oxidation by the LOCOS method in order to secure the thickness of 2, the bird's beak length increases.

Further, since the p-type Si substrate 101 corresponding to the source region forming portion and the drain region forming portion is exposed by the overetching in the above-described etch-back step, damage or defects may occur in these portions. is there. In this case, as a countermeasure, it is necessary to optimize the process conditions so that damage to the substrate is reduced.

In the above-described etch-back step, the SiO ₂ film 107 on the gate electrode 104 having a polycide structure is formed.
There the WSi _x film 104b is removed to expose substantially at the same time as this SiO ₂ film on the active region is exposed even p-type Si substrate 101 is removed. Therefore, WSi _x film 104b etched tungsten (W) to the p-type Si substrate 101, enters in particular to its source region formation portion and the drain region forming unit, results in the formation of heavy metal contamination layer. Therefore, as a countermeasure, it is generally necessary to include a removal flow of the heavy metal contaminated layer in the post-treatment.

Further, the p-type Si substrate 101 corresponding to the source region forming portion and the drain region forming portion is formed by over-etching in the above-described etch-back step.
Is etched, in the finally formed source region 109 and drain region 110, the profile of the low impurity concentration portion and the high impurity concentration portion immediately below the sidewall spacer 108 changes, and the transistor characteristics deteriorate. There's a problem.

Accordingly, it is an object of the present invention to prevent contamination of the substrate surface and reduce damage to the substrate without deteriorating the element isolation ability when a spacer is formed on the side wall of the gate electrode. It is another object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a MIS field-effect transistor having good characteristics.

[0017]

In order to achieve the above object, the present invention relates to a method of manufacturing a semiconductor device having a spacer on a side wall of a gate electrode provided on a substrate via a gate insulating film. Forming a conductive film for forming a gate electrode via a gate insulating film, patterning the conductive film for forming a gate electrode to form a gate electrode, and forming a capping layer on the entire surface so as to cover the gate electrode. Forming, forming a spacer forming film made of a material different from the capping layer on the capping layer, and forming a spacer on the side wall of the gate electrode by etching back the spacer forming film. It is characterized by the following.

In the present invention, when the spacer forming film is etched back, the capping layer and the spacer forming film are etched such that the spacer forming film is selectively etched with respect to the capping layer. As a material, it is preferable to use materials having different etching rates in etching when etching back a film for forming a spacer. Further, in the present invention, the etch-back of the spacer-forming film is preferably performed under the condition that the etching rate of the spacer-forming film is higher than the etching rate of the capping layer, at least until the surface of the capping layer is exposed. . At the time of this etch back, for example, the etching is stopped at a depth halfway in the thickness direction of the capping layer so that the field insulating film for element isolation, the gate electrode, and the substrate are not exposed.

In the present invention, since the capping layer needs to have an insulating property, an insulator such as silicon nitride or silicon dioxide is used as a material of the capping layer. In the present invention, the film for forming a spacer preferably has an insulating property. As a material of the film for forming the spacer, for example, an insulator such as silicon dioxide or silicon nitride is used. In the present invention, the combination of the capping layer and the material for forming the spacer is such that when etching back the film for forming the spacer, the film for forming the spacer can be etched with a high selectivity ratio with respect to the capping layer. Is preferably selected. From this viewpoint, typically, silicon nitride is used as the material of the capping layer, and silicon dioxide is used as the material of the film for forming the spacer. In addition to this combination, silicon dioxide as the material of the capping layer and the material for forming the spacer are used. Silicon nitride may be used as the material of the film.

In the present invention, the gate electrode may be made of, for example, a high melting point metal film such as W. For example, the gate electrode may be made of a polycrystalline silicon film and a high melting point metal silicide film on this polycrystalline silicon film. It may have a so-called polycide structure. When the gate electrode has a polycide structure, as the refractory metal silicide film,
For example, a tungsten silicide film, a molybdenum silicide film, a tantalum silicide film, a titanium silicide film, or the like is used.

According to the present invention configured as described above, when forming a spacer on the side wall of the gate electrode, the conductive film for forming the gate electrode is patterned to form the gate electrode, and then the gate electrode is formed. A capping layer is formed on the entire surface so as to cover, a spacer forming film made of a material different from that of the capping layer is formed on the capping layer, and then the spacer forming film is etched back. As a result, the gate electrode, the substrate, and the field insulating film for element isolation are not exposed, and therefore, the gate electrode, the substrate, and the field insulating film are prevented from being etched when the spacer forming film is etched back. can do.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. 1 to 6 are sectional views for explaining a method for manufacturing a MOSFET having an LDD structure according to an embodiment of the present invention. In this embodiment, a case where an n-channel MOSFET is manufactured will be described as an example.

In the method for manufacturing a MOSFET according to this embodiment, as shown in FIG. 1, first, a field insulating film 2 such as a SiO ₂ film is selectively formed on the surface of a p-type Si substrate 1 by a LOCOS method. To perform element isolation. At this time, the p-type Si substrate 1 in the element isolation region
A p-type impurity such as B, which has been introduced in advance by an ion implantation method or the like, diffuses therein, and a p ⁺ -type channel stop region (not shown) is formed below the field insulating film 2. Thereafter, the surface of the active region surrounded by the field insulating film 2 is coated, for example, with a thickness of about 10
A gate insulating film 3 made of a ₂ nm thick SiO ₂ film is formed.

Next, a polycrystalline Si film 4a is formed on the entire surface by, for example, a CVD method. Next, in order to reduce the resistance value, the polycrystalline Si film 4a is heavily doped with an n-type impurity such as P by, for example, an ion implantation method. Next, WS is formed on the polycrystalline Si film 4a by, for example, the CVD method.
forming the i _x film 4b. Next, these polycrystalline Si films 4
a and WSi _x film 4b is patterned into a predetermined shape by etching. Thus, on the p-type Si substrate 1, a polycrystalline Si film 4a and the WSi _x film 4b are those patterned via a gate insulating film 3, a gate electrode 4 of the so-called polycide structure is formed.

Next, as shown in FIG. 2, the active region surrounded by the field insulating film 2 is doped with an n-type impurity such as P by ion implantation using the gate electrode 4 as a mask. Thereby, n ⁻ -type layers 5 and 6 are formed in a self-aligned manner with respect to gate electrode 4.

Next, as shown in FIG. 3, silicon nitride (Si) as a capping layer is covered by, for example, a plasma CVD method so as to cover the upper surface and side walls of the gate electrode 4.
_Nx ) film 7 is formed on the entire surface. Here, in this embodiment, as described later, a film for forming a sidewall spacer is formed on the SiN _x film 7 as the capping layer, and this film is etched back to form a sidewall of the gate electrode. In order to prevent the p-type Si substrate 1 from being exposed by removing the SiN _x film 7 by the over-etching at the time of the etch back, the SiN _x film 7 is Thickness (this thickness is determined according to the etching conditions)
It is necessary to form above. On the other hand, if the SiN _x film 7 is too thick, there is a concern that the SiN _x film 7 may be adversely affected by stress. In consideration of the above points, here, the thickness of the SiN _x film 7 is selected to be, for example, 3 nm or more and 10 nm or less, and specifically, for example, 5 nm.

Next, as shown in FIG. 4, an SiO ₂ film 8 (eg, NS) having a predetermined thickness is formed on the SiN _x film 7 as a film for forming a sidewall spacer by, eg, CVD.
G film).

Next, as shown in FIG. 5, the SiO ₂ film 8 is etched back by, eg, RIE method in a direction perpendicular to the surface of the p-type Si substrate 1 until at least the surface of the SiN _x film 7 is exposed. I do. The RIE is conditions the etching rate of the SiO ₂ film 8 is greater than the etching rate of the SiN _x film 7, i.e., S for the SiN _x film 7
This is performed under the condition that the selectivity of the iO ₂ film 8 becomes high. in this case,
For example, although the etching end point cannot be detected by the spectroscopic analysis method, since the SiN _x film 7 becomes the etching stop layer,
By setting an etching time sufficient to remove the SiO ₂ film 8 in a portion other than the side wall of the gate electrode 4, the S
The etch back of the iO ₂ film 8 can be performed stably. The RIE at the time of this etch back uses, for example, a mixed gas of CHF ₃ and CO as an etching gas,
The selection is performed with a selectivity ratio of SiO ₂ / SiN _x of about 8 to 10. As a result, the side wall spacer 9 made of SiO ₂ is formed on the side wall of the gate electrode 4 via the SiN _x film 7.
Is formed. At this time, the gate electrode 4, the p-type Si substrate 1, and the field insulating film 2 are covered with the SiN _x film 7 in portions other than the sidewall spacers 9, that is, the gate electrode 4, the p-type Si substrate 1, The field insulating film 2 is not exposed.

Next, as shown in FIG. 6, using the side wall spacer 9 and the gate electrode 4 as a mask, an n-type impurity such as As is injected into the active region surrounded by the field insulating film 2 by ion implantation. Is highly doped. Thereafter, if necessary, annealing for electrically activating the implanted impurities is performed. As a result, an n ⁺ -type source region 10 and a drain region 11 are formed in a self-alignment manner with the sidewall spacer 9. The source region 10 and the drain region 11 are formed in a lower portion of the side wall spacer 9 in the n ⁻ -type low impurity concentration portion 1.
0a and 11a. Here, these low impurity concentration portions 10a and 11a are composed of n ⁻ -type layers 5 and 6, respectively.

Thereafter, although not shown, for example, CVD
After an interlayer insulating film such as a SiO ₂ film is formed on the entire surface by a method, a predetermined portion of the interlayer insulating film is removed by etching, and a contact hole reaching the source region 10 and the drain region 11 is formed. Next, for example, an Al film is formed on the entire surface by a sputtering method or a vacuum evaporation method, and then the Al film is patterned into a predetermined shape by etching to form a source electrode and a drain electrode. next,
A surface protection film is formed on the entire surface, and an n-channel M having an LDD structure is formed.
Complete the OSFET.

As described above, according to this embodiment,
When the sidewall of the gate electrode 4 to form a sidewall spacer 9, after forming the gate electrode 4 by patterning the polycrystalline Si film 4a and the WSi _x film 4b, so as to cover the upper and side surfaces of the gate electrode 4 An SiN _x film 7 is formed on the entire surface as a capping layer, and an SiO ₂ film 8 is formed on the SiN _x film 7 as a film for forming a spacer, and then the SiO ₂ film 8 is selected with respect to the SiN _x film 7. The gate electrode 4, the p-type Si substrate 1, and the field insulating film 2 are not exposed because the etch back is performed under the condition that the ratio is high. Therefore, when the SiO ₂ film 8 is etched back, the gate electrode 4 is not etched. , P-type Si substrate 1 and field insulating film 2 can be prevented from being etched. As a result, the following advantages can be obtained.

That is, since the field insulating film 2 is not etched, the thickness of the field insulating film 2 does not decrease, and deterioration of element isolation characteristics can be prevented. In addition, since it is not necessary to previously form the field insulating film 2 at the time of selective oxidation by the LOCOS method, it is possible to suppress an increase in bird's beak length.

Also, since the p-type Si substrate 1 is not exposed,
This damage to the p-type Si substrate 1, especially the p-type S in the portions corresponding to the source region forming portion and the drain region forming portion.
Damage to the i-substrate 1 can be minimized.

The surface of the gate electrode 4, ie, WS
Since i _x film 4b is not exposed by W from the WSi _x film 4b, be p-type Si substrate 1, in particular the portion corresponding to the source region formation portion and the drain region forming unit to prevent contamination it can. Therefore, p-type Si
The removal flow of the heavy metal contaminant layer formed on the substrate 1 does not need to be included in the post-processing, and the manufacturing process can be simplified.

Further, since the p-type Si substrate 1 is not etched, the profile of the low impurity concentration portion and the high impurity concentration portion immediately below the sidewall spacer 9 in the finally formed source region 10 and drain region 11 is changed. Without doing so, a MOSFET with good characteristics can be obtained.

Further, according to this embodiment, the SiN _x film 7 is formed on the entire surface, and the SiN _x film 7 is formed by the CVD method.
Since the O ₂ film 8 is formed, it is possible to eliminate the variation of the film thickness due to the dependence of the film formation rate on the base, which is generally known, and thus, the remaining film after the etch back of the SiO ₂ film 8 is achieved. There is also an advantage that the variation in can be kept small.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, the numerical values, materials, processes, structures, and the like described in the embodiments are merely examples,
It is not limited to this.

Specifically, in the above-described embodiment, SiN _x is used as the material of the capping layer, and SiO ₂ is used as the material of the film for forming the side wall spacer. S as material
iO ₂ may be used, and SiN _x may be used as a material of a film for forming a sidewall spacer.

Further, WSi _x in the above-described embodiment
Instead of the film 4b, MoSi _x film, TaSi _x film or T
such as i Si _x film may be other refractory metal silicide film. Further, instead of the gate electrode 4 having the polycide structure in the above-described embodiment, a gate electrode made of a refractory metal film such as a W film may be used.

Further, in the above-described embodiment, the case where the present invention is applied to the manufacture of the n-channel MOSFET has been described.
T as well as CMOS ICs and Bi-CMOS I
The present invention can be applied to the manufacture of all semiconductor devices having a MOSFET such as C.

[0041]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the gate electrode is formed by patterning the conductive film for forming the gate electrode when forming the spacer on the side wall of the gate electrode. After that, a capping layer is formed on the entire surface so as to cover the gate electrode, a film for forming a spacer made of a material different from that of the capping layer is formed on the capping layer, and then the film for forming the spacer is formed. By performing the etch back, the gate electrode, the substrate, and the field insulating film for isolation between elements are not exposed. Therefore, when the film for forming the spacer is etched back, the gate electrode, the substrate, and the field insulating film are removed. Can be prevented from being etched. Therefore, according to the method of manufacturing a semiconductor device according to the present invention, when forming a spacer on the side wall of the gate electrode, it is possible to prevent contamination of the substrate surface without deteriorating the element isolation capability and to prevent the substrate from being contaminated. Damage can be reduced, and a MIS field-effect transistor having good characteristics can be manufactured.

[Brief description of the drawings]

FIG. 1 shows an M of an LDD structure according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 2 shows an M of an LDD structure according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 3 shows an M of an LDD structure according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 4 shows an M of an LDD structure according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 5 shows an M of an LDD structure according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 6 shows an M of an LDD structure according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 7 is a cross-sectional view for describing a method of manufacturing a MOSFET having an LDD structure according to a conventional technique.

FIG. 8 is a cross-sectional view for explaining a method of manufacturing a conventional MOSFET having an LDD structure.

FIG. 9 is a cross-sectional view for explaining a method of manufacturing a MOSFET having an LDD structure according to a conventional technique.

FIG. 10 shows a conventional MOSFET having an LDD structure.
FIG. 6 is a cross-sectional view for describing the method for manufacturing the semiconductor device.

FIG. 11 shows a conventional MOSFET having an LDD structure.
FIG. 6 is a cross-sectional view for describing the method for manufacturing the semiconductor device.

FIG. 12 shows a conventional MOSFET having an LDD structure.
13 is a cross-sectional view for describing a problem with the manufacturing method of FIG.

[Explanation of symbols]

1 ... p-type Si substrate, 2 ... field insulating film, 3
... Gate insulating film, 4 ... Gate electrode, 4a ...
Polycrystalline Si film, 4b ··· WSi _x film, 5,6 ··· n
^- -type layer, 7 · · · SiN _x film, 8 · · · SiO ₂ film, 9
... Sidewall spacer, 10 ... Source region, 11 ... Drain region, 10a, 11a ... Low impurity concentration part

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having a spacer on a side wall of a gate electrode provided on a substrate with a gate insulating film interposed therebetween, the conductive material for forming the gate electrode being formed on the substrate via the gate insulating film. Forming a film, forming the gate electrode by patterning the conductive film for forming the gate electrode, forming a capping layer over the entire surface so as to cover the gate electrode, Forming a spacer-forming film made of a material different from that of the capping layer; and etching back the spacer-forming film to form the spacer on a side wall of the gate electrode. A method for manufacturing a semiconductor device. 2. The semiconductor according to claim 1, wherein the capping layer and the spacer forming film are made of materials having different etching rates in etching when etching back the spacer forming film. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said etch-back is performed under a condition that an etching rate of said film for forming said spacer is higher than an etching rate of said capping layer. 4. The method according to claim 1, wherein said capping layer is made of silicon nitride or silicon dioxide. 5. The method according to claim 1, wherein the spacer forming film is made of silicon dioxide or silicon nitride. 6. The method according to claim 1, wherein said capping layer is made of silicon nitride, and said film for forming said spacer is made of silicon dioxide. 7. The method according to claim 1, wherein the capping layer is made of silicon dioxide, and the film for forming the spacer is made of silicon nitride. 8. The method according to claim 1, wherein said gate electrode comprises a polycrystalline silicon film and a refractory metal silicide film on said polycrystalline silicon film.