JP2000068988A - External control clock signal and multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain transmission of data when no external clock from a modem is given to a buffer in a low speed channel. SOLUTION: Clock input interruption detection circuits 106, 107 connect to an external clock side in a low speed channel to monitor the state of the external clock. If input of S side and R side external clocks ST1, ST2 is interrupted, an S side clock selector 103 and an R side clock selector 104 are controlled to select an internal clock RT in a low speed channel respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external clock control method for a buffer used when connecting a low-speed channel in a multiplexer to a modem, and to a multiplexer.

[0002]

2. Description of the Related Art A conventional buffer clock switching method will be described. In the low-speed channel in the multiplexer,
When a modem (DCE) is connected and operated, a data signal dependent on its own internal clock is transmitted. Therefore, for the purpose of absorbing the frequency difference between the clocks, a buffer is provided in the low-speed channel to perform data transmission between the low-speed channel and the modem.

[0003] In a low-speed channel in a multiplexing apparatus, a terminal (DTE) is connected and operated, but a modem may be connected due to the operational configuration. In this case, since both the low-speed channel and the modem are connected as a modem (DCE), they each transmit a data signal dependent on their own internal clock. Therefore, when a low-speed channel is connected to a modem, the S-side buffer 201 and the R-side buffer are connected to "S" and "R", respectively, as shown in FIG. A buffer 202 is provided, and data signals in both buffers are exchanged with a clock transmitted from a connected modem. In the prior art described above, the S-side buffer 201 and R
When the side buffer 202 is used in dependence on an external clock, the following settings are made.

First, in the S-side buffer 201, data writing depends on the S-side external clock ST1.
The clock destination of the S-side clock selector 203 is set to S
Side external clock ST1. R side buffer 202
In order to make the data reading dependent on the R-side external clock ST2, the clock fetch destination of the R-side clock selector is set to the R-side external clock ST2. With the above setting, the S-side buffer 201 can take in the data SD dependent on the S-side external clock ST1, and the R-side buffer 202 can read the data RD dependent on the R-side external clock ST2.

[0005]

However, the S-side and R-side buffers 201 and 202 which are dependent on the external clock.
When the S-side external clock ST1 and the R-side external clock ST2 are not input to the S-side buffer 201, respectively, the S-side buffer 201 cannot write the data SD,
In the side buffer 202, the data RD cannot be read. Therefore, if a clock transmission failure occurs between the modem and the low-speed channel, the transmission clock from the modem will not be input to the buffer,
The low-speed channel cannot transmit data. In addition, when the external clock is dependent, there is a problem that the presence or absence of the input of the external clock is not known.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an external clock control method and a multiplexing apparatus capable of transmitting data even when an external clock is not input from a modem to a buffer in a low-speed channel.

[0007]

According to the present invention, in an external clock control system for a buffer used when connecting a low-speed channel in a multiplexing apparatus to a modem, an S-side buffer of an S-side buffer in a low-speed channel is used. A first clock input disconnection detection circuit for monitoring the signal state of the S-side external clock is provided between the external clock and the S-side clock selector, and the R-side external clock of the R-side buffer and the R-side clock selector of the R-side clock selector in the low-speed channel are provided. A second clock input disconnection detection circuit for monitoring a signal state of the R-side external clock between the first and second clocks;
And the second clock input disconnection detection circuit monitors the signal state of the external clock, and when the S-side and the R-side external clock are disconnected, the S-side and the R-side clock selectors respectively operate at a low speed. An external clock control method characterized by performing control so as to switch to an internal clock in a channel is obtained.

Further, according to the present invention, in an external clock control method for a buffer used when connecting a low-speed channel in a multiplexing apparatus to a modem, an S-side external clock of an S-side buffer in a low-speed channel and an S-side external clock are controlled. A first clock input disconnection detection circuit for monitoring the signal state of the S-side external clock is provided between the R-side clock selector and the R-side external clock of the R-side buffer in the low-speed channel. A second clock input disconnection detection circuit for monitoring a signal state of the external clock;
Clock input disconnection detection circuit monitors the signal state of the external clock, and when the S-side and the R-side external clocks are disconnected, the S-side and the R-side clock selectors respectively control the internal state of the low-speed channel. The external clock control method is characterized in that control is performed so as to switch to a clock, and even if an external clock is not input to at least one of the two buffers, transmission can be performed without cutting data. can get.

Further, according to the present invention, there is provided an external clock control system having a function of outputting a maintenance alarm to the outside when the external clock is abnormal and the input is interrupted. .

Further, according to the present invention, the S-side buffer and the R-side buffer are connected to the S-side buffer and the R-side buffer, respectively.
When using the S-side buffer dependent on the S-side external clock, the S-side buffer sets the clock capture destination of the S-side clock selector to the S-side external clock in order to make data writing dependent on the S-side external clock, The R-side buffer sets the clock fetch destination of the R-side clock selector to the R-side external clock in order to make data reading dependent on the R-side external clock, and the S-side buffer sets the clock fetch destination to the S-side external clock. An external clock control method is obtained in which dependent data is taken in, and the R-side buffer reads out data dependent on the R-side external clock.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. This embodiment is different from the conventional embodiment in that the S-side buffer 10 in the low-speed channel is
A first clock input disconnection detection circuit for monitoring the signal state of the S-side external clock is provided between the S-side external clock and the S-side clock selector, and the R-side external clock and the R-side clock of the R-side buffer in the low-speed channel are provided. This is exactly the same except that a second clock input disconnection detection circuit for monitoring the signal state of the R-side external clock is provided between the clock selectors on the R side.

Regarding the operation, a clock input disconnection detection circuit is connected to the external clock side in the low-speed channel, and the signal state of the external clock is monitored.
Since the S-side clock selector 103 and the R-side clock selector 104 perform control so as to switch to the internal clock RT in the low-speed channel even when the external clocks ST1 and ST2 are cut off, the connection between the modem and the low-speed channel is performed. , Data transmission becomes possible.

When a low-speed channel is connected to a modem and the S-side buffer 101 and the R-side buffer 102 are used in dependence on an external clock, the following settings are made. The S-side buffer 101 outputs data to the S-side external clock S
In order to be dependent on T1, the clock fetch destination of the S-side clock selector 103 is set to the S-side external clock ST1. In addition, in the R-side buffer 102, the clock fetch destination of the R-side clock selector 104 is set to the R-side external clock ST2 in order to make the data reading dependent on the R-side external clock ST2. Thereby, the S-side buffer 1
01, the data S dependent on the S-side external clock ST1
The R-side buffer 102 can read the data RD dependent on the R-side external clock ST2.

Then, the clock input disconnection detection circuit 106 is connected to the S-side external clock ST1, and the R-side external clock S
The clock input disconnection detection circuit 107 is connected to T2, and its output is connected to the inputs of the S-side clock selector 103 and the R-side clock selector 104, respectively.

With the above-described configuration, the clock input disconnection detection circuits 106 and 107 provide the S-side external clocks ST1 and R
The signal state of the external clock ST2 is monitored, and if the external clock is cut off, the S-side clock selector 103 and the R-side clock selector 104 are controlled to switch to the low-speed channel internal clock 105, respectively.

If the S-side external clock has an abnormality and the input is interrupted, an abnormality can be objectively determined by providing a function for outputting a maintenance alarm to the outside.

[0017]

According to the present invention, even if the external clock is no longer input to the buffer in the low-speed channel, the data is taken in with the internal clock of the low-speed channel, so that the transmission can be performed without interrupting the data. It is possible.

Further, according to the present invention, a data error is increased with respect to a bit slip as compared with a case where data transmission is performed in accordance with an external clock, but this is effective in relieving data interruption.

According to the present invention, when the clock is abnormal,
A maintenance alarm is output externally, and the abnormality can be objectively recognized.

According to the present invention, even if the transmission clock is not input from the modem to the buffer of the low-speed channel in the multiplexing device during data transmission by connecting the multiplexing device and the modem, Can be transmitted.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

[Explanation of symbols]

 101 S-side buffer 102 R-side buffer 103 S-side clock selector 104 R-side clock selector 105 Internal clock 106 S-side clock input disconnection detection circuit 107 R-side clock input disconnection detection circuit

Claims (8)

[Claims] 1. An external clock control system for a buffer used when connecting a modem to a low-speed channel in a multiplexer, wherein an S-side external clock of an S-side buffer and an S-side clock selector in a low-speed channel are provided. A first clock input disconnection detection circuit for monitoring a signal state of the S-side external clock; and a signal state of the R-side external clock between the R-side external clock of the R-side buffer and the R-side clock selector in the low-speed channel. A second clock input disconnection detecting circuit for monitoring the signal state of the external clock, wherein the first and second clock input disconnection detecting circuits monitor a signal state of the external clock.
An external clock control system, wherein when the input of the external clock of the side and the external clock of the R side is interrupted, the control of the clock selectors of the S side and the R side is respectively switched to the internal clock in the low-speed channel. 2. An external clock control method for a buffer used when connecting a modem to a low-speed channel in a multiplexer, wherein an S-side external clock of an S-side buffer and an S-side clock selector in a low-speed channel are used. A first clock input disconnection detection circuit for monitoring a signal state of the S-side external clock; and a signal state of the R-side external clock between the R-side external clock of the R-side buffer and the R-side clock selector in the low-speed channel. A second clock input disconnection detecting circuit for monitoring the signal state of the external clock, wherein the first and second clock input disconnection detecting circuits monitor a signal state of the external clock.
The S-side and the R-side clock selectors perform control so as to switch to the internal clocks in the low-speed channels, respectively, when the input of the external clock is interrupted, and the external clock is supplied to at least one of the buffers. An external clock control method characterized in that transmission can be performed without interrupting data even when input is stopped. 3. The external clock control system according to claim 1, further comprising a function of outputting a maintenance alarm to the outside when the external clock is abnormal and the input is interrupted. 4. When using the S-side buffer and the R-side buffer dependent on the S-side and R-side external clocks, respectively, the S-side buffer depends on the S-side external clock for writing data. In order to make
The clock capture destination of the R-side clock selector is set to the S-side external clock, and the R-side buffer sets the clock capture destination of the R-side clock selector to the R-side clock in order to make data reading dependent on the R-side external clock.
Side external clock, and the S side buffer
4. The external clock control method according to claim 1, wherein the data dependent on the external clock is taken in, and the R buffer reads out the data dependent on the external clock. 5. An S-side external clock and an S-side clock of an S-side buffer in a low-speed channel in a multiplexer that employs an external clock control method of a buffer used when connecting a low-speed channel in the apparatus and a modem. A first clock input disconnection detection circuit for monitoring the signal state of the S-side external clock between the selectors, and the R-side external clock between the R-side external clock of the R-side buffer and the R-side clock selector in the low-speed channel A second clock input disconnection detection circuit for monitoring the signal status of the external clock, wherein the first and second clock input disconnection detection circuits monitor the signal status of the external clock. When the input is cut off, the S-side and the R-side clock selectors are controlled to switch to the internal clocks in the low-speed channel, respectively. A multiplexing device. 6. An S-side external clock and an S-side clock of an S-side buffer in a low-speed channel in a multiplexer that employs an external clock control method of a buffer used when connecting a low-speed channel in the apparatus and a modem. A first clock input disconnection detection circuit for monitoring the signal state of the S-side external clock between the selectors, and the R-side external clock between the R-side external clock of the R-side buffer and the R-side clock selector in the low-speed channel A second clock input disconnection detection circuit for monitoring the signal status of the external clock, wherein the first and second clock input disconnection detection circuits monitor the signal status of the external clock. When the input is cut off, the S-side and the R-side clock selectors perform control so as to switch to the internal clock in the low-speed channel, respectively. A multiplexing apparatus capable of performing transmission without cutting data even if an external clock is not input to at least one of the buffers. 7. The multiplexing apparatus according to claim 5, further comprising a maintenance alarm section for outputting a maintenance alarm to the outside when the external clock is abnormal and the input is interrupted. 8. When the S-side buffer and the R-side buffer are used depending on the S-side and the R-side external clock, respectively, the S-side buffer depends on the S-side external clock for writing data. In order to make
The clock capture destination of the R-side clock selector is set to the S-side external clock, and the R-side buffer sets the clock capture destination of the R-side clock selector to the R-side clock in order to make data reading dependent on the R-side external clock.
Side external clock, and the S side buffer
8. The multiplexing apparatus according to claim 5, wherein the data dependent on the external clock is taken in, and the data dependent on the external clock is read out by the R-side buffer.