JP2000058742A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip type semiconductor device wherein, with a recessed part provided on the rear surface side of a chip, wire-bonding to an electrode pad concealed under the chip is allowed. SOLUTION: A first semiconductor chip 10 is fitted to an island 13 while a second semiconductor chip 11 is fitted on the first semiconductor chip 10. The first semiconductor chip 10 is connected to a lead terminal 17 with a first bonding wire 16a while the second semiconductor chip 11 is connected to the lead terminal 17 with a second bonding wire 16b. The first and the second semiconductor chips 10 and 11 have similar chip size and shape, and a first electrode pad 12a is concealed under the second semiconductor chip 11 from a top view. The end of the semiconductor chip 11 is locally cut to provide a recessed part 19, the space of the recessed part 19 is used to connect the first electrode pad 12a to the second bonding wire 16a, and a bonding agent 15 expands as far as the recessed part 19 for solidification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be miniaturized by combining a plurality of semiconductor chips having an approximate size while overlapping and molding a plurality of semiconductor chips.

[0002]

2. Description of the Related Art A transfer molding method for sealing a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. Technology. A lead frame is used as a support material for the semiconductor chip 1. The semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pads of the semiconductor chip 1 and the leads 4 are connected to the wires 5.
It is manufactured by setting a lead frame in a mold having a desired outer shape, injecting an epoxy resin into the mold, and curing the lead frame.

On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration.

In view of this, a technique of sealing a plurality of semiconductor chips in one package, which has existed as an idea (for example, Japanese Patent Application Laid-Open No. 55-1111517), has been attracting attention, and there has been a movement to realize it. Have been. That is, FIG.
As shown in FIG. 1, the first semiconductor chip 1
a, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and the lead terminals 4 are connected with the bonding wires 5a, 5b and sealed with the resin 2. It is.

[0005]

The structure shown in FIG. 6B is as follows.
In order to secure wire bonding with the first semiconductor chip 1a, the electrode pad portion of the first semiconductor chip 1a is exposed when the second semiconductor chip 1b is fixed, that is, there is a difference in chip size. That is an absolute condition. For this reason, there is a disadvantage that, for example, two chips of the same model are incorporated, or chips of different models cannot be adopted when their chip sizes are similar. Although it is conceivable to superimpose two semiconductor chips in a cross shape, the condition is that there is a difference in the vertical and horizontal dimensions of the chip size, and the restrictions still remain.

To solve this, for example, FIG.
As shown in FIG.
There is a method of fixing these so that the back surfaces of a and 1b face each other. However, since the loop height of the bonding wire needs to be doubled, the thickness of the entire semiconductor device (X in FIG. 6C) increases, and there is a disadvantage that the thickness cannot be reduced.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has been formed on first and second semiconductor chips and on the respective surfaces of the first and second semiconductor chips. An electrode pad, an electrode means for external connection, and a bonding wire for connecting the electrode pad of the first and second semiconductor chips to the electrode means, respectively. In a semiconductor device which is overlapped and sealed in one package, the two are overlapped so that the upper part of the electrode pad of the first semiconductor chip is covered with the second semiconductor chip, and the electrode of the first semiconductor chip is overlapped. A concave portion is formed by locally thinning the back surface of the second semiconductor chip located on the pad, and a bonding wire connected to an electrode pad of the first semiconductor chip passes through the concave portion and the first wire passes through the first semiconductor chip. Half of A back surface of the second semiconductor chip, wherein the first and second semiconductor chips are bonded to an electrode pad of the body chip, and the first and second semiconductor chips are fixed with an insulating adhesive; Is characterized by being in contact with.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail.

First, FIG. 1 is a sectional view showing a main part of a semiconductor device of the present invention, FIG. 2A is a sectional view showing the whole, and FIG. 2B is a plan view showing the whole.

In these figures, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. A large number of active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 by various diffusion heat treatments in a previous process. First and second semiconductor chips 1
First and second external connection first and second
Electrode pads 12a and 12b are formed of aluminum electrodes. A passivation film is formed on each of the electrode pads 12a, 12b.
The top of b is open for electrical connection. The passivation film is a silicon nitride film, a silicon oxide film, a polyimide insulating film, or the like. In the example of FIG. 2B, the electrode pads 12a and 12b are arranged collectively along two opposing sides of the semiconductor chips 10 and 11.

A first semiconductor chip 10 is die-bonded onto an island 13 of a lead frame by an adhesive 14. The second semiconductor chip 11 is the first semiconductor chip 10
Is fixed by an adhesive 15 on the passivation film. The adhesive 14 is conductive or insulating, and the adhesive 15 is an insulating epoxy-based adhesive.

One end of a first bonding wire 16a made of a gold wire is connected to the first electrode pad 12a, and the other end of the first bonding wire 16a is connected to an external lead terminal 17 by wire bonding. Have been. One end of a second bonding wire 16b is wire-bonded to the surface of the second electrode pad 12b,
The other end of the second bonding wire 16b is wire-bonded to a lead terminal 17 for external lead-out.

The main portion including the first and second semiconductor chips 10 and 11, the lead terminals 17, and the first and second bonding wires 16a and 16b is surrounded by an epoxy-based thermosetting resin 18. It is molded to form a semiconductor device package. The lead terminal 17 is led out from the side wall of the package to be an external connection terminal. The lead terminal 17 is bent into a Z-shape. The back surface of the island 13 is exposed on the surface of the resin 18 and forms the same plane as the surface of the resin 18.

The combination of the first and second semiconductor chips 10, 11 is arbitrary. For example, when semiconductor storage devices such as an EEPROM (flash memory) are used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity can be doubled or tripled in one package.
・ ・ It can be done. Also, the first semiconductor chip 1
It is also conceivable that a semiconductor memory device such as an EEPROM (flash memory) is formed on the second semiconductor chip 11 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example). In either case, each chip has an I / O terminal for inputting and outputting data,
It has an address terminal for designating a data address and a chip enable terminal for permitting data input / output, and the pin arrangements of both chips are very similar. for that reason,
The I / O terminal and the lead terminal 17 for the address terminal of the first and second semiconductor chips 10 and 11 can be shared, and by applying an exclusive chip enable signal to each chip, one of them can be used. It is possible to exclusively select the memory cells of one semiconductor chip.

In the case of the first combination example, the first semiconductor chip 10 and the second semiconductor chip 11 have the same size and shape, and
The arrangement of a and 12b is the same. Therefore, when they are overlapped, the electrode pads 12 a of the first semiconductor chip 10 are hidden behind the second semiconductor chip 11. Specifically, FIG.
In the example of (B), the first electrode pad 12a is located immediately below the second electrode pad 12b. Also in the case of the second combination example, the chip size and shape may be similar and the pin arrangement may be very similar.

Thus, a concave portion 19 is formed above the first electrode pad 12a along two opposing sides of the second semiconductor chip 12b, and the second semiconductor chip 11 is protruded like an eaves. I have. The recess 19 has a width enough to expose the first electrode 12a from the end of the first semiconductor chip 10 (FIG. 1:
W), and has a height sufficient to accommodate the wire height of the first bonding wire 16a (FIG. 1: t1). In the present embodiment, the housing height is realized by grinding the back surface of the second semiconductor chip 11 by about half the thickness (FIG. 1: t2) with a dicing blade. Since the height to be stored is the height from the surface of the first semiconductor chip 10, the dicing depth (t2) is determined in consideration of the thickness of the adhesive 15.

The recess 19 forms a space above the first electrode pad 12a, in which the first bonding wire 16a is ball-bonded to the first electrode pad 12a. The first bonding wire 16a continuous from the ball portion 20 passes through the concave portion 19, and the lead terminal 1
7 is second-bonded. When the surface of the lead terminal 17 is higher than the height of the surface of the first semiconductor chip 10, the first bonding wire 16a passes through the recess 19 from the first electrode 12a and is led out in the lateral direction. Then, a trajectory that rises outside the end of the second semiconductor chip 11 and reaches the leading end of the lead terminal 17 is drawn.

The adhesive 15 is used for the first and second semiconductor chips 1.
0 and 11 are fixed to each other, and at the same time, they flow out into the concave portion 19 and the ball portion 20 of the first bonding wire 12a.
The periphery is wrapped and solidified so as to fill the recess 19. The solidified adhesive 15 also contacts the back surface of the second semiconductor chip 11 locally thinned by the concave portion 19, and preferably contacts the entire lower portion of the second electrode pad 12b. By solidifying the adhesive 15 in this state, there is no need to create a space below the second electrode pad 12b. Therefore, the second electrode pad 12b is
When the bonding wire 16b is bonded, the solidified adhesive 15 plays a role of supporting the second semiconductor chip 11.

By providing the recess 19 in this manner, wire bonding to the first semiconductor chip 11 is enabled, and the first bonding wire 16a is
Contact with the back surface of the semiconductor chip 11 is avoided. Further, the first bonding wire 16a is
Allows the height of the entire semiconductor device (FIG. 1: t3) to be reduced.

In addition, by bonding the adhesive 15 to the recess 19 and solidifying it, the bondability with respect to the second electrode pad 12b can be improved.

In the present embodiment, the island 13 has a thickness of 150 to 200 μm, and the first and second semiconductor chips 10 and 11 have a thickness of 250 μm by a back grinding process.
The thickness of the adhesives 14, 15 needs to be 20 to 30 .mu.m, and the remaining thickness of the resin above the bonding wire needs to be 150 to 200 .mu.m. The present applicant has realized a semiconductor device in which the height t3 of the package is reduced to 1.0 mm or less while accommodating these thicknesses.

Hereinafter, a method for producing the product of the present invention will be described.

First step: see FIG. 3 First and second semiconductor chips 10 and 11 are prepared. These can be obtained by dicing and separating each from a semiconductor wafer on which various circuit elements have been formed in the previous step. The second semiconductor chip 1 in which the concave portion 19 is formed
1 can be obtained by performing the following special processing at the time of dicing.

First, a semiconductor wafer 32 having a first main surface 30 and a second main surface 31 is prepared, and circuit elements are formed on the first main surface 30. Then, as shown in FIG. 3A, the dicing line is recognized from the second main surface 31 side, and is wide (about 1.
0 mm) by the first dicing blade 33, the groove 3 having a depth of 130 μ with respect to the entire wafer thickness of 280 μ.
4 is formed. The center line of the dicing blade 33 coincides with the center line of the dicing line. Next, FIG.
As shown in the figure, the width is narrow along the dicing line (about 4
The wafer 32 is completely cut by the second dicing blade 35 (0 μm). The groove 34 formed by half dicing may be provided only at the position where the concave portion 19 is provided, or may be provided so as to form the concave portion 19 on all four sides of the semiconductor chips 10 and 11. Also, the second dicing blade 3
5 may be cut from the first main surface 30 side,
The form which cuts from the main surface 31 side may be used.

Second Step: See FIG. 4A A lead frame having an island 13 for fixing a semiconductor chip and a lead terminal 17 for external connection is prepared. The semiconductor chip 10 is fixed. The adhesive 14 is a conductive or epoxy insulating adhesive such as an Ag paste. Then, the first electrode 1 of the first semiconductor chip 10
2a and the lead terminal 17 are connected to the first bonding wire 1
Connect at 6a. The wire loop of the first bonding wire 16a is formed as low as possible.

Third step: Refer to FIG. 4B. On the first semiconductor chip 10, an insulating adhesive 15 is applied. The adhesive 15 is a liquid adhesive having an epoxy-based viscosity, and a predetermined amount is supplied from the dispenser 50 at 200 ° C. Perform baking treatment for several tens minutes. Fourth step: See FIG. 4 (C). The second semiconductor chip 11 is transported by a pyramid collet and placed on the first semiconductor chip 10. At this time, the second semiconductor chip 11 is pushed down by the pyramid collet at a pressure of several tens g / cm 2, and the adhesive 15 is spread between the first and second semiconductor chips 10 and 11 with a uniform thickness. The adhesive 15 extends to the recess 19 so as to fill the space. At this time, the expanded adhesive 15
Represents the back surface 5 of the second semiconductor chip 11 even in the concave portion 19.
1 and desirably in contact with the entire area directly below the second electrode pad 12b. This control depends on the amount, viscosity, baking temperature and the like when the adhesive 15 is applied. Then, a baking process for evaporating and solidifying the organic solvent contained in the adhesive 15 is performed at 200 ° C. for several tens of minutes.

Fifth step: See FIG. 4D. The second electrode pad 12b and the lead terminal 17 are wire-bonded by ball bonding. The second bonding wire 16b having the ball 52 formed at the tip of the wire is pushed down by the capillary 53, and the ball 52 is fixed by applying a predetermined pressure and ultrasonic vibration to the surface of the second electrode pad 12b (1st bonding). Then, the second bonding wire 16b is fixed to the lead terminal 17 by the operation of the capillary 53 (2nd bonding). At the time of the first bonding, the adhesive 15 that has been expanded and solidified to the concave portion 19 serves as a base against the pressure for pushing down the capillary 53. Thereby, at the time of wire bonding, the concave portion 1 of the second semiconductor chip 11 is formed.
9 prevents cracks and chips from occurring and improves bondability.

Thereafter, the whole is resin-molded, and individual semiconductor devices are separated from the lead frame to complete a product.

FIG. 5 shows a second embodiment. This is an example in which a tape carrier and solder balls are used instead of the lead frame. The first semiconductor chip 10 is bonded and fixed on the polyimide base film 40, and the second semiconductor chip 11 is fixed on the first semiconductor chip 10.
A conductive pattern 41 corresponding to the lead terminal 17 is formed on the surface of the base film 40, and the first and second electrode pads 12a, 12b and the conductive pattern 41 are respectively connected to the first and second bonding wires 16a, 16b. A through hole is formed in the base film 40,
The through holes are connected to solder balls 42 formed on the back surface of the base film 40, and the periphery is molded with a thermosetting resin.

Although the above embodiment has described the case where there are two semiconductor chips, it is needless to say that the same operation can be performed when three or four semiconductor chips are stacked.

[0031]

As described above, according to the present invention,
The back surface of the second semiconductor chip 11 is ground to form a concave portion 19, and the first electrode 12 is formed using a space formed by the concave portion 19.
Since the first bonding wires 12a are bonded to a, there is an advantage that even when the sizes and shapes of the semiconductor chips 10 and 11 are similar, wire bonding can be performed by stacking a plurality of semiconductor chips. Thus, for example, one package can have twice the storage capacity.

Further, the use of the concave portion 19 can absorb the loop height of the first bonding wire 16a, and thus has an advantage that the thickness of the package can be reduced.

Further, by expanding and solidifying the adhesive 15 to the concave portion 19, a structure in which the lower portion of the second electrode pad 12b does not become hollow can be obtained. Thus, there is an advantage that deterioration of bondability during wire bonding can be prevented.

Further, any size and shape of the semiconductor chips 10 and 11 can be combined, which has the advantage of increasing the degree of freedom in product development.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIGS. 2A and 2B are cross-sectional views for explaining the present invention; FIGS.
It is a top view.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing the concave portion 19;

FIG. 4 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (4)

[Claims] 1. A semiconductor device comprising: first and second semiconductor chips;
And an electrode pad formed on each surface of the second semiconductor chip, electrode means for external connection, and bonding wires for connecting the electrode pads of the first and second semiconductor chips to the electrode means, respectively. In the semiconductor device in which the first and second semiconductor chips are overlapped and sealed in one package, the upper part of the electrode pad of the first semiconductor chip is the second semiconductor chip.
The two are overlapped so as to be covered by the semiconductor chip, and the back surface of the second semiconductor chip located on the electrode pad of the first semiconductor chip is locally thinned to form a concave portion. A bonding wire connected to the electrode pad of the semiconductor chip passes through the recess and is bonded to the electrode pad of the first semiconductor chip, and the first and second semiconductor chips are fixed with an insulating adhesive. A semiconductor device, wherein the adhesive reaches the concave portion and is in contact with the back surface of the second semiconductor chip. 2. The semiconductor device according to claim 1, wherein said concave portion is formed by half dicing from a back surface. 3. The semiconductor device according to claim 1, wherein said adhesive is expanded to a position immediately below an electrode pad of said second semiconductor chip. 4. A step of preparing a first semiconductor chip and a second semiconductor chip in which a concave portion is formed by locally thinning an end of the first semiconductor chip, and fixing the first semiconductor chip to a predetermined fixing portion. A step of connecting an electrode pad of the first semiconductor chip and an electrode means for external connection with a first bonding wire; a step of applying an adhesive on the first semiconductor chip; The second semiconductor chip is stacked on the first semiconductor chip so that the first bonding wire is accommodated in the concave portion and the adhesive reaches the concave portion, and the adhesive is solidified. And a step of connecting an electrode pad of the second semiconductor chip located above the concave portion and an electrode means for external connection with a second bonding wire. Semiconduct Manufacturing method of the device.