JP2000050287A - Image input device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image input device that conducts AE and AWB control at high speed without increasing current consumption. SOLUTION: This image input device consists of an XY address two-dimensional pixel array 1, a video signal read vertical scanning circuit 2 for the pixel array that is placed at a 1st end of the pixel array, a video signal read horizontal scanning circuit 3 for the pixel array placed at a 2nd end adjacent to the 1st end, an AE/AWB control pixel signal read vertical scanning circuit 4 that is placed at a 3rd end facing opposite to the 1st end of the pixel array, an AE/AWB control pixel signal read horizontal scanning circuit 5 that is placed at a 4th end facing opposite to the 2nd end of the pixel array, and an arithmetic circuit 6 that applies analog processing to the AE/AWB control pixel signal read by the AE/AWB control pixel signal read vertical and horizontal scanning circuits to provide the output of an AE/AWB control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device, and more particularly to an image input device capable of performing exposure control and white balance adjustment at high speed.

[0002]

2. Description of the Related Art Conventionally, an image input apparatus for photographing a subject image with an image sensor, converting the image into an electric signal, and inputting it is configured as shown in FIG. In FIG. 15, reference numeral 101 denotes a single-chip color CCD image sensor for photoelectrically converting an optical signal into an electrical signal, which has an electronic shutter function. The CCD image sensor 101 includes a lens 102 and an aperture / shutter mechanism 103.
Through which the subject light is input. C
The output of the CD imaging device 101 is amplified by an amplifier 104 after noise is removed by a correlated double sampling circuit or the like.
Reference numeral 105 denotes an A / D converter for converting the output of the amplifier 104, which is analog data, into digital data. Reference numeral 106 denotes a camera signal processing circuit for processing a signal from the CCD image sensor 101 as video data. 107 is C before the original shooting
An AF detection circuit for extracting AF (auto-focus) information for controlling focus, an AE detection circuit for extracting AE (auto-exposure, auto iris) information for controlling exposure, and a white balance using an imaging signal or the like from the CD image sensor 101. An AWB detection circuit for extracting AWB (auto white balance) information to be set.
The output signal from the AWB detection circuit 107 is sent to the lens 102 via the CPU 108 to provide AF information to the aperture / shutter mechanism 103.
AE information and AWB information to the camera signal processing circuit 106.

Reference numeral 109 denotes a compression circuit (JPEG) for compressing the data amount, and the image data compressed by the compression circuit 109 is recorded on a memory card or the like. Reference numeral 110 denotes a DRAM, which is used as a working memory when performing color processing of video data and the like. 11
A timing generator 1 generates a timing pulse for driving the CCD 101, and drives the CCD 101 under the control of the CPU 108.

Next, the operation of the image input apparatus having the above configuration will be described. An image signal generated by the CCD image sensor 101 by imaging is converted into a digital signal by an A / D converter 105, subjected to predetermined signal processing by a camera signal processing circuit 106, and then temporarily stored as image data in a DRAM 110. Is done. Further, AF, AE, and AW are performed by using the image data converted into digital signals by the A / D converter 105.
The AF, AE, and AWB information is extracted by a B detection circuit 107, and the AF information is given to a lens 102 via a CPU 108 to perform an AF operation.
To perform the AE operation, and the AWB information to the camera signal processing circuit 106 to perform the AWB processing operation.

[0005]

By the way, in the above-mentioned conventional image input apparatus, an AF, AE, and AWB detection circuit is used.
107 detects AF, AE, and AWB information by using image data obtained by converting an image pickup signal from the CCD image pickup device 101 into a digital signal by an A / D converter 105. However, there is a problem that AF, AE, and AWB control cannot be performed at high speed. In addition, the CCD imaging device 10
There is a problem that operating 1 requires a large amount of power.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional image input apparatus, and provides an image input apparatus capable of performing AE and AWB control at high speed without increasing current consumption. The purpose is to do.

[0007]

According to a first aspect of the present invention, there is provided a pixel array in which pixels having photoelectric conversion elements are two-dimensionally arranged, and a first pixel array of the pixel array. A first scanning unit arranged at an end of the pixel array for scanning the entire pixel area of the pixel array; and a first scanning unit arranged at a second end adjacent to the first end of the pixel array. Second scanning means for scanning the entire pixel area of the pixel array and reading video signals from the pixel array in cooperation with the means, and a third scanning means opposed to a first end of the pixel array.
A third scanning means disposed at an end of the pixel array for scanning a predetermined area of the pixel array; and a third scanning means disposed at a fourth end of the pixel array opposed to a second end of the pixel array. A fourth scanning unit for scanning a predetermined area of the pixel array in cooperation with the third scanning unit to read out pixel signals for exposure control and white balance control from a pixel group in the predetermined area of the pixel array; The image input device is constituted by means for outputting an exposure control signal and a white balance control signal by analog operation based on a pixel signal of a predetermined area read by the fourth scanning means.

In the image input apparatus thus constructed, the signals obtained by the first and second scanning means are used as video signals, and the pixel signals of a predetermined area obtained by the third and fourth scanning means are converted to high-speed signals. Instead of digital operation, direct analog operation is performed, and exposure control signal and white balance control signal are output in a short time.
Exposure control and white balance control processing can be performed at high speed without increasing current consumption.

According to a fourth aspect of the present invention, there is provided a pixel array in which pixels having photoelectric conversion elements are two-dimensionally arranged.
First scanning means disposed at a first end of the pixel array and having a function of scanning all pixel areas of the pixel array and a function of scanning a predetermined area of the pixel array; A function of reading a video signal from the pixel array in cooperation with a function of the first scanning means for scanning the entire pixel area of the pixel array; The first scanning means scans a predetermined area of the pixel array in cooperation with a function of scanning a predetermined area of the pixel array, and outputs a pixel signal for exposure control and white balance control from a pixel group of the predetermined area of the pixel array. A second scanning unit having a reading function, and an exposure control signal and a white balance control signal based on an analog operation based on a pixel signal of a predetermined area read by the first and second scanning units. And it constitutes an image input device in a stage.

In the image input device thus configured, a signal obtained by a function of scanning the entire pixel area of the pixel array of the first and second scanning means is a video signal,
Further, since the pixel signals obtained by the function of scanning the predetermined area of the pixel array of the first and second scanning means are directly subjected to analog calculation, and the exposure control signal and the white balance control signal are output, the exposure control is performed. Signals and white balance control signals can be performed at high speed without increasing the circuit scale and without increasing current consumption.

[0011]

Next, an embodiment will be described. FIG. 1 is a schematic block diagram showing a configuration of a main part of an embodiment of an image input apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes an XY address type two-dimensional pixel array; 2, a vertical scanning circuit for reading a video signal of the pixel array 1 disposed at a first end of the pixel array 1; The video signal readout horizontal scanning circuit 4 of the pixel array 1 arranged at the second end adjacent to the first end of the pixel array 1 is arranged at the third end opposite to the first end of the pixel array 1. AE / AWB control pixel signal reading vertical scanning circuit,
Reference numeral 5 denotes an AE / AWB control pixel signal readout horizontal scanning circuit arranged at a fourth end opposite to the second end of the pixel array 1, and 6 denotes an AE / AWB control pixel signal readout vertical and horizontal scan circuit. A for performing analog arithmetic processing on the AE / AWB control pixel signal read out by the scanning by 4 and 5
An E / AWB control signal operation circuit.

The AE / AWB control pixel signal reading vertical and horizontal scanning circuits 4 and 5 output pixel signals of an arbitrary M × N pixel block of the pixel array 1, for example, as shown in FIG. Readout or as shown in FIG. 2 (B), a pixel can be selected and read out according to a desired purpose such that pixel signals at the center and four corners are read out. AE / AWB
The control signal calculation circuit is configured to calculate and output an average value or a peak value of the read pixel signals of the desired area in an analog manner. The video signal read by the vertical and horizontal scanning circuit for reading the video signal is subjected to A / D conversion as before, and then subjected to predetermined signal processing.

In the above embodiment, the vertical and horizontal scanning circuits for reading out video signals and the vertical and horizontal scanning circuits for reading out pixel signals for AE / AWB control are separately provided, but these are separately provided. As shown in FIG. 3, the video signal reading vertical and horizontal scanning circuits
It is also possible to provide an E / AWB control pixel signal reading function, so that the circuit scale can be reduced. In FIG. 3, reference numeral 2 'denotes a vertical scanning circuit having a video signal readout function and a pixel signal readout function for AE / AWB control, and 3' denotes a video signal readout and AE / AWB control.
This is a horizontal scanning circuit having a control pixel signal reading function.

Next, a configuration in which the average value is calculated and output in an analog manner from the pixel signals of the 3 × 3 pixel block of the pixel array will be conceptually described with reference to FIG. FIG.
In the figure, reference numeral 11 denotes a 3 × 3 pixel block of the pixel array, and each of the vertical selection lines 12j, 12 (j + 1), 12 (j +
In (2), a selection signal is simultaneously output from the AE / AWB control pixel signal reading vertical scanning circuit, and three vertical selection lines are simultaneously selected, and each of the vertical signal lines 13i, 13 ( The horizontal selection switches 14i, 14 (i + 1), 14 (i + 2) connected to (i + 1), 13 (i + 2) are configured to be simultaneously turned on by the AE / AWB control pixel signal reading horizontal scanning circuit. . Then, the vertical signal lines 13i, 13 (i + 1),
The pixel signal from 13 (i + 2) is added by the adder 15 and 3
It is configured such that a current addition value of a × 3 pixel signal can be obtained. Then, AE / AWB control processing is performed based on this current value.

FIG. 5 is a schematic configuration diagram showing an example of a configuration for calculating a peak value of a pixel signal of a 3 × 3 pixel block. In FIG. 5, 16i, 16 (i + 1), 16 (i + 2) are current sources connected to the vertical signal lines 13i, 13 (i + 1), 13 (i + 2), 17i, 17 (i + 1), 17 (i + 2). Is a switch connected between the vertical signal lines. In the pixel peak value detection circuit having such a configuration, the vertical selection lines 12j, 12 (j + 1), and 12 (j + 2) are simultaneously selected and the AE / AWB control pixel signal is obtained, as in the case of calculating the average value. The selection switch 14 (i + 1) is turned on by the readout horizontal scanning circuit, and the switches 17i and 17 (i + 1) are simultaneously turned on. The output terminals of the 3 × 3 pixels are connected to one current source (load transistor).
16 (i + 1), 3 × 3 from output terminal 18
The maximum value of the pixel is output, and the peak value can be detected in the voltage mode. Based on this peak value, AE / A
Perform WB control processing.

In the above configuration example, the average value or the peak value of all the pixels in the pixel block 11 is obtained. For example, in the case of a single-chip color image pickup device using a Bayer array color filter, the same color is used. A switch circuit for reading out the pixel signals is provided, and arithmetic processing is performed for each color signal as shown in FIG. In FIG. 6, 21-1
R, 21-1G, 21-1B,..., 21-3B are switches for reading out pixel signals of the same color driven by pulses φR, φG, φB, and 22-1, 22-2, 22-3 are R, G,
... Φ6 are vertical selection signals. At the timing, the vertical selection signals φ1, φ3, φ5 are applied to the arrangement row of R, G, R, G pixels, and the vertical selection signal is applied to the arrangement row of G, B, G, B pixels. Is applied, a pulse φR is applied to turn on the switches 21-1R, 21-2R, and 21-3R to perform current addition of the R pixel signal. , G3,..., G pixels, the vertical selection signals φ1, φ3, φ5
The vertical selection signal is not applied to the array row of G, B, G, and B pixels, and a pulse φG is applied to switch 21-1G, 21G.
-2G and 21-3G are turned on to perform current addition of G pixel signals. At the timing, vertical selection signals φ2, φ4, φ6 are applied to the array rows of G, B, G, B pixels. A vertical selection signal is not applied to an array row of R, G, R, and G pixels, and a pulse φB is applied so that 21-1B, 21-2
B, 21-3B are turned ON, and the current addition of the B pixel signal is performed. In the pixel array shown in FIG. 6, the signal of the white G pixel is not used.

In this specification, the case where there is no color filter other than the one shown in FIG. 6 is shown. However, in the case where a color filter is provided, similar to the case shown in FIG. , And is configured to perform scanning such that signals can be handled for each color.

Next, an example of the configuration of an image input apparatus in which an average value is obtained by a more specific current addition method will be described with reference to FIG. In FIG. 7, 31 is a pixel, 32j, 32 (j
+1), 32 (j + 2) ... are vertical selection lines, 33j, 33 (j + 1),
33 (j + 2)... Are reset signal lines, 34i, 34 (i + 1), 34
(i + 2): vertical signal lines, 35i, 35 (i + 1), 35 (i + 2)
... are FPN (fixed pattern noise) suppression circuits using a current copier cell connected to one end of each vertical signal line, 36i, 36 (i + 1), 36 (i + 2) are horizontal selection switches, and 37 is A signal output line 38 commonly connected to the output side of the horizontal selection switch is a current-voltage conversion circuit.

Each pixel 31 has a configuration as shown in FIG. 8 (p-channel pixel). In FIG. 8, 31-1 is a photodiode, 31-2 is an amplifying MOSFET, 31-
3 is a vertical selection MOSFET, 31-4 is a reset MO.
SFET.

Next, the configuration of the current copier cell will be described. The current copier cell is shown in FIG.
As shown in (B), the MOS transistor M _M and the capacitance C
And switches S _X , S _Y , and S _Z. Then, as shown in the drive timing diagrams of FIGS. 9A and 9C, in the phase 0, the switches S _X and S _Y
Is closed, and the input current I ₀ flows into the cell. When the equilibrium state is reached, the voltage applied to the capacitor C becomes a gate-source voltage corresponding to the input current I ₀ . Next, as shown in FIG. 9B, when the switch S _X is opened and S _Z is closed in phase 1, the cell is connected to the load, and the current I ₁ flowing at this time depends on the potential of the previous capacitor C end. Controlled,
The current is equal to I ₀ .

Next, an FPN suppressing circuit using the current copier cell having such a configuration will be described. This FP
The N suppression circuit arranges two current copier cells, stores a (signal + offset) current in one, and stores an offset current in the other, reads them out simultaneously, and obtains the difference by taking the difference.
This is to suppress PN. That is, as shown in FIG. 10, an n-channel copier cell 41 and a p-channel copier cell 42
And a single-ended configuration. Dummy transistors 41a and 42a are added to the switch to suppress clock feedthrough, and cascode transistors 43 and 44 are added to suppress the output conductance effect.

Next, the operation of the thus configured FPN suppressing circuit will be described. First, the operation at the first timing shown in the pulse timing chart of FIG. The sum of the signal current I _SIG and the offset current I _OFF in phase φ ₁ (I _IN) is stored in the n-channel copier cell 41. After resetting the pixel, the offset current I _OFF flows into the FPN suppressing circuit in the phase φ ₂ , and at this time, the n-channel copier cell 41 outputs (I _SIG +
In order to pull in I _OFF ), the p-channel copier cell 42 in the input phase receives I _P = (I _SIG + I _OFF ) −I _OFF
+ I ₀ = I _SIG + I ₀ will be stored. That is, only a signal component that does not include an offset current component (I _OFF ) that varies from pixel to pixel is stored. Here, the bias current I ₀ is added in order to suppress a long settling time when the signal current I _SIG is small. Phase φ
_{When the} circuit leads to the load at ₃ , the signal component I
_SIG (I _OUT ) flows out of the circuit.

Next, the operation at the second timing shown in FIG. 11B will be described. The sum of the signal current I _SIG and the offset current I _OFF in phase φ ₁ (I _IN) is, n
It is stored in the channel copier cell 41. This current is transferred and stored in the p-channel copier cell 42 while the pixel is reset. Next, the offset current I _OFF is stored in the n-channel copier cell 41. At this point, the offset current I _OFF is stored in the n-channel copier cell 41,
(I _SIG + I _OFF ) is stored in the p-channel copier cell 42. When the circuit is connected to the load by phase phi _3,
If they are different, the signal component I _SIG (I _OUT ) flows out of the circuit. This timing operation does not require the bias current I ₀ .

Next, the operation of the current addition type image input apparatus to which the FPN suppressing circuit using the current copier cell shown in FIG. 7 is applied will be described with reference to the timing chart of FIG. The timing chart of FIG. 12 corresponds to the timing chart shown in FIG. φ ₁ ~φ ₃ Figure 10
The pulses φ _2i and φ _3i output during the horizontal scanning period in the FPN suppression circuit shown in FIG. to φ ₁ of the _{period, (I OFFi -ΔI SIGi) +} (I
_{OFF (i + 1)} -ΔI _{SIG (i + 1)} ) is stored in the n-channel copier cell. Here, I _OFFi and I _{OFF (i + 1)} are signal currents immediately after resetting and generate FPN. the current value is stored in the p-channel copier cell phi ₂ periods.
During this time, the pixel is reset by a reset pulse phi _RS. The next phi _{1 period, (I OFFi + I OFF (} i + 1)) is stored in the n-channel copier cell. Φ _2i , φ _3i , φ _{2 (i + 1)} , φ _{3 (i + 1)} are turned on during the horizontal scanning period,
Addition of pixels is performed.

As described above, the horizontal blanking period (H-B
The current addition in the vertical direction and the FPN cancellation are performed during L), and the current addition in the horizontal direction is performed during the horizontal scanning period, thereby obtaining a suppressed current addition value of 2 × 2 pixels of FPN. The frame rate increases according to the number of pixels added,
High-speed AE and AWB control processing becomes possible.

Next, a specific example of the configuration of an image input apparatus of the peak value detection system will be described with reference to FIG. Reference numeral 51 denotes a pixel having a pixel configuration shown in FIG. Figure
In 14, 51-1 is a photodiode, 51-2 is an amplification MOSFET, 51-3 is a vertical selection MOSFET, 51
-4 is a reset MOSFET. In FIG.
52-1, 52-2,... Are vertical selection lines, 53-1 and 53-
Are reset signal lines, 54-1, 54-2, ...
Are vertical signal lines, 55-1, 55-2,... Are AE, AWB
Scan pulses φ _S1 , φ _S2 from the horizontal scanning circuit for detection,
· Horizontal selection switches 56-1 and 56 driven by
−2,... Are peak value detecting transistors _MP , and no horizontal scanning pulses φ _S1 , φ _S2,.
The gate potential of the peak value detection transistor M _P horizontal selection switch is off, so that the current to the peak value detection transistor M _P is biased to V _DD so as not flowing. 57 is a transistor M for peak value detection
A signal output line commonly connected to _P , which is connected to a power supply _VDD via a current source 58, and 59 is an output terminal.
The 60-1 and 60-2, ... it is in the load MOS transistor M _L, and constitutes a source follower with the amplifying MOS transistor constituting the pixel 51.

FIG. 15 shows a 2 × 2 pixel array in a 6 × 6 pixel array.
FIG. 4 is a pulse timing chart when detecting a peak value of a subarray. Since the drain current of a MOS transistor is proportional to the square of its gate-source voltage, a plurality of M
When the sum of the currents supplied to the OS transistors is constant, the current flows into the MOS transistor having the largest gate-source voltage. For the circuit arrangement of FIG. 13, the gate-source voltage of the transistor is maximized with the lowest input potential of the potential applied to the gate of the peak value detecting transistor M _P. Therefore, the output terminal
At 59, the output V _PEAK corresponding to the lowest input potential appears. In the case where the n-channel pixel shown in FIG. 14 is used, the output voltage becomes lower as the amount of incident light increases. Therefore, the peak value of the incident light amount can be detected.

The peak value detecting circuit using the p-channel pixel 51 'has a configuration as shown in FIG.

[0029]

As described above based on the embodiment, according to the first aspect of the present invention, the pixel signals obtained from the first and second scanning means are used as video signals, and the third and fourth pixel signals are obtained. Since the AE / AWB control signal is output by analog calculation using the pixel signal obtained from the scanning means, the AE / AWB control processing can be performed at high speed without increasing current consumption. According to the fourth aspect of the present invention, a signal obtained by a function of scanning the entire pixel area of the pixel array of the first and second scanning means is used as a video signal, and a pixel of the first and second scanning means is used as a video signal. Since the pixel signal obtained by the function of scanning a predetermined area of the array is directly subjected to analog calculation and the exposure control signal and the white balance control signal are output, the circuit scale of the exposure control signal and the white balance control signal is reduced. High-speed operation can be performed without increasing the current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of an image input device according to the present invention.

FIG. 2 is an AE / AWB in the embodiment shown in FIG.
FIG. 4 is a diagram illustrating a manner of reading pixel signals by a control pixel signal reading vertical and horizontal scanning circuit.

FIG. 3 is a block diagram showing a configuration of a main part of a modification of the embodiment shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration example in which an average value of pixel signals of a 3 × 3 pixel block of a pixel array is output by analog arithmetic processing.

FIG. 5 is a block diagram illustrating a configuration example in which a peak value of a pixel signal of a 3 × 3 pixel block of a pixel array is output by analog arithmetic processing.

FIG. 6 is a diagram illustrating a configuration example in a case where an average value of all pixels in a pixel block is obtained for each color in a color imaging device.

FIG. 7 is a diagram showing a specific configuration example of an image input device in which an average value is obtained by a current addition method.

FIG. 8 is a diagram illustrating a configuration example of a pixel in FIG. 7;

9 is a diagram illustrating a configuration of a current copier cell used in the FPN suppression circuit in FIG. 7;

FIG. 10 is a diagram illustrating a configuration of an FPN suppression circuit using a current copier cell.

11 is a timing chart for explaining the operation of the FPN suppressing circuit shown in FIG.

12 is a timing chart for explaining an operation of the image input device including the FPN suppressing circuit shown in FIG.

FIG. 13 is a diagram illustrating a specific configuration example of an image input device using a peak value detection method.

14 is a diagram illustrating a configuration example of a pixel in the image input device illustrated in FIG. 13;

FIG. 15 is a timing chart for explaining the operation of the image input device shown in FIG. 13;

FIG. 16 is a diagram illustrating a configuration of a peak value detection circuit when a pixel having a p-channel configuration is used.

FIG. 17 is a block diagram illustrating a configuration example of a conventional image input device.

[Explanation of symbols]

1 XY address type two-dimensional pixel array 2 Video signal reading vertical scanning circuit 3 Video signal reading horizontal scanning circuit 4 AE / AWB control pixel signal reading vertical scanning circuit 5 AE / AWB control pixel signal reading horizontal scanning circuit 6 AE / AWB Control signal operation circuit 11 Pixel block 12j, 12 (j + 1), 12 (j + 2) Vertical selection line 13i, 13 (i + 1), 13 (i + 2) Vertical signal line 14i, 14 (i + 1), 14 (i + 2) Horizontal selection switch 15 Adders 16i, 16 (i + 1), 16 (i + 2) Current sources 17i, 17 (i + 1), 17 (i + 2) Switch 18 Output terminals 21-1R, 21-1G, 21-1B Switches 22-1, 22-2, 22-3 Current addition circuit 31 Pixel 31-1 Photodiode 31-2 Amplification MOSFET 31-3 Vertical selection MOSFET 31-4 Reset MOSFET 32j, 32 (j + 1), 32 (j + 2), ... Vertical selection line 33j, 33 (j + 1), 33 (j + 2), ... Reset Signal lines 34i, 34 (i + 1), 34 (i + 2),... Vertical signal lines 35i, 35 (i + 1), 35 (i + 2),... FPN suppressing circuits 36i, 36 (i + 1) using current copier cells , 36 (i + 2), ... Horizontal selection switch 37 Signal output line 38 Current-voltage conversion circuit 41 N-channel copier cell 42 P-channel copier cell 43, 44 Cascode transistor 51 Pixel 51-1 Photodiode 51-2 Amplification MOSFET 51 -3 Vertical selection MOSFET 51-4 Reset MOSFETs 52-1, 52-2, ... Vertical selection lines 53-1, 53-2, ... Reset signal lines 54-1, 54-2, ...・ Vertical signal line 55-1, 55-2,... Horizontal selection switch 56-1, 56-2,... Peak value detection transistor 57 Signal output line 58 Current source 59 Output terminal 60-1, 60- 2, ... Load MOS transistor

Continued on the front page F term (reference) 5C022 AA13 AB04 AB05 AB06 AB12 AB28 AB30 AC42 AC52 AC54 AC56 AC69 5C065 AA03 BB02 BB08 BB11 BB48 CC01 DD15 DD17 EE06 EE12 GG12 GG16 GG17 GG18 GG29 GG30 GG32

Claims (6)

[Claims] 1. A pixel array in which pixels having photoelectric conversion elements are two-dimensionally arranged, and a first array arranged at a first end of the pixel array and scanning all pixel regions of the pixel array.
And a scanning means disposed at a second end adjacent to a first end of the pixel array, and cooperating with the first scanning means to scan the entire pixel area of the pixel array and Second scanning means for reading a video signal from the array, and third scanning means disposed at a third end of the pixel array opposite to the first end for scanning a predetermined area of the pixel array And a predetermined area of the pixel array which is arranged at a fourth end opposite to the second end of the pixel array and scans a predetermined area of the pixel array in cooperation with the third scanning means. A fourth scanning means for reading out pixel signals for exposure control and white balance control from the pixel group of the above, and an exposure by analog operation based on the pixel signals of a predetermined area read out by the third and fourth scanning means. Control signal and white balance control signal An image input apparatus characterized by comprising a means for outputting. 2. The control signal output means outputs a control signal by performing signal processing for each color component on a pixel signal of a predetermined area read by the third and fourth scanning means. The image input device according to claim 1, wherein the image input device is configured as follows. 3. The control signal output unit is configured to output a peak value or an addition value of a pixel signal of a predetermined area of the pixel array read by the third and fourth scanning units. The image input device according to claim 1 or 2, wherein: 4. A pixel array in which pixels having photoelectric conversion elements are two-dimensionally arranged, and a function for scanning a whole pixel area of the pixel array, which is arranged at a first end of the pixel array. Scanning a predetermined area of the array.
The scanning means and the second scanning means arranged at a second end adjacent to the first end of the pixel array and cooperating with a function of the first scanning means for scanning the entire pixel area of the pixel array. Scanning a predetermined area of the pixel array in cooperation with a function of reading a video signal from the array and a function of scanning the predetermined area of the pixel array of the first scanning means. A second scanning unit having a function of reading out pixel signals for exposure control and white balance control, and an exposure control signal based on an analog operation based on a pixel signal of a predetermined area read out by the first and second scanning units And an output unit for outputting a white balance control signal. 5. The control signal output means performs signal processing for each color component with respect to a pixel signal in a predetermined area read by the first and second scanning means, and outputs each control signal. The image input device according to claim 4, wherein: 6. The control signal output unit is configured to output a peak value or an addition value of a pixel signal of a predetermined area of the pixel array read by the first and second scanning units. The image input device according to claim 4 or 5, wherein: