JP2000050148A - Television camera equipment - Google Patents

Abstract

(57) Abstract: In a television camera system that performs digital signal processing, a signal processing circuit for performing optimal video signal processing according to switching of the number of CCD pixels or the aspect ratio of a frame image is replaced with an exchange unit. And without increasing the circuit scale by paralleling the circuits. A ROM load type FPGA is used as a processing circuit for a digital video signal A / D converted at a CCD clock rate, and a digital signal processing circuit in the FPGA is provided according to the number of CCD pixels or the aspect ratio of a frame image. change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television camera device for performing digital signal processing, and more particularly to a television camera device capable of capturing an image in response to a change in the aspect ratio of a frame image or a change in the number of pixels of the frame image. It is related to the improvement of.

[0002]

2. Description of the Related Art In recent years, in a CCD (charge coupled device) image pickup device used in a television camera device, the number of pixels of a frame image which can be picked up is increasing year by year with the technical progress. . Further, a broadcast station or the like often uses a plurality of television cameras having different numbers of pixels and aspect ratios of frame images. For this reason, there is a growing demand for a television camera system capable of capturing images in accordance with a plurality of types of pixels and the aspect ratio of a frame image.

In particular, techniques for widening the screen aspect ratio (aspect ratio) from the conventional 4: 3 to 16: 9 have been actively adopted. : 3 and 16: 9 aspect ratio switching function is particularly required.

[0004] Here, the aspect ratio switching between 4: 3 and 16: 9 can be performed by changing the CCD reading method or by using a memory to write video signal data to the memory at a clock rate (clock rate). frequency)
And a clock rate for reading the data. However, in either method, it is necessary to change the effective CCD drive frequency (sampling clock rate).

In a television camera device using this conventional technique, a video signal output from a camera head having a CCD image pickup device is input and a video signal is processed.
When the CU (camera control unit) performs the video signal processing by analog signal processing, the CC
Even if the number of pixels of the frame image output from the D image sensor was changed, it was not necessary to change the circuit configuration of the analog video signal processing circuit. That is, in the case of digital signal processing, a change in the clock rate necessitates a change in the circuit configuration accordingly,
If the video signal processing is analog signal processing, an analog signal processing circuit configuration that can be shared by responding to a plurality of clock rates can be used. .

However, in recent years, digital signal processing has been increasingly used in video signal processing, and signal processing circuits used in television camera apparatuses have also been digitized.

For this reason, when the signal processing circuit used in the television camera device is also digitized, the following problem arises when the number of pixels or the aspect ratio of the frame image in the camera head changes. That is, in a television camera device for which the highest image quality is required in a broadcast television camera or the like, digital signal processing is performed in order to prevent beats or aliasing noise from occurring in a video signal, which would deteriorate the video quality. Is necessary A
A method of adjusting the clock rate of / D conversion (analog to digital conversion) to the sampling clock rate of the CCD image sensor is used.

Further, when digital signal processing is performed, depending on the signal processing rate, for example, the frequency characteristics of the filter change. Therefore, in the case of a television camera system that performs digital signal processing, the number of pixels in a frame image is small. When the aspect ratio of the frame image is changed, it is necessary to change the processing circuit in accordance with the change.

Therefore, in the conventional method, it is necessary to replace the unit for performing the video signal processing in accordance with the number of pixels or the aspect ratio of the frame image, and unless a circuit configuration and a device structure that allow the replacement are used. No. Alternatively, it is necessary to provide a plurality of digital video signal processing circuits corresponding to each signal processing rate, which has a drawback that the circuit scale and the device scale become enormous.

[0010]

As described above, in the conventional camera system for performing digital signal processing, if the number of pixels or the aspect ratio of the frame image changes according to the CCD used, the signal processing circuit needs to be changed. become.

Therefore, in the conventional method, the number of pixels or the aspect ratio of the frame image corresponding to the CCD is adjusted according to
It is necessary to replace the units or to provide a plurality of digital circuits corresponding to each signal processing rate, which has a disadvantage that the circuit scale becomes enormous.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and provides a television camera device having a digital video signal processing circuit capable of responding to a change in the number of pixels or the aspect ratio of a frame image with a smaller circuit and a simpler device structure. For the purpose of realization.

[0013]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a television camera apparatus for performing video signal processing, which detects a sampling clock rate of the video signal and controls a video signal processing circuit. The circuit configuration information of a field programmable logic device (hereinafter referred to as an FPGA) to be configured is determined by the detected sampling clock.
By selecting the circuit configuration information according to the rate and reading the selected circuit configuration information into the FPGA, the F
The PGA has a video signal processing circuit configuration corresponding to the detected sampling clock rate.

The present invention also provides a means for detecting a sampling clock rate of the video signal, a field programmable logic device (hereinafter referred to as an FPGA) constituting a circuit for performing video signal processing, and a circuit for the FPGA. Means for storing configuration information; and means for controlling output of circuit configuration information corresponding to the detected sampling clock rate from the storage means to the FPGA, wherein the FPGA is configured to control the detected clock. The video signal processing circuit has a configuration corresponding to the rate.

[0015]

FIG. 1 is a block diagram showing an embodiment of a television camera apparatus according to the present invention, and will be described in detail with reference to FIG. CCD image sensor (CC
D) The output video signal from 1 is input to the analog signal processing circuit 2, and the analog signal processing circuit 2 performs necessary processing such as amplification processing. The video signal processed by the analog signal processing circuit 2 is input to an A / D conversion circuit 3 and the CCD 1
Is sampled at the same clock rate as the driving clock of the digital clock and converted into a digital signal.

The video signal digitized by the A / D conversion circuit 3 is a signal that does not require a change in the configuration of the processing circuit depending on the number of pixels or the aspect ratio of the frame image picked up by the CCD 1 in the video signal processing. It is input to a digital signal processing circuit 4 for performing processing. The video signal processing performed by the digital signal processing circuit 4
Even if the number of pixels or the aspect ratio of the frame image captured in D1 is changed, the video signal processing is performed in common regardless of the change.

The video signal input to the digital signal processing circuit 4 is subjected to a predetermined video signal processing, and then is subjected to an F
It is supplied to a digital signal processing circuit 6 composed of PGA. Further, the processed video signal is supplied to the CPU unit 5.
Is input to The CPU unit 5 detects the sampling clock rate of the input video signal, and holds data representing the detected rate.

The digital signal processing circuit 6 includes the CPU
Under the control based on the data held according to the detected rate from the section 5, digital signal processing is performed according to the number of pixels or the aspect ratio of the frame image picked up by the CCD 1. The signal processed by the digital signal processing circuit 6 passes through a D / A conversion (digital-to-analog conversion) circuit 7 and a digital I / F (interface) circuit 8 and is output as an output signal of a television camera device. Each of them is output as an analog video output signal or digital video output signal to a subsequent stage (not shown).

Here, one of the types of FPGA,
"ROM (read only memory) load type (or SRAM (static random access
The structure of an FPGA called “memory) type”) and a method of changing a signal processing circuit corresponding to the number of pixels or the aspect ratio of a CCD frame image using this type of FPGA will be briefly described.

As shown in FIG. 4 for explaining an example of the internal block configuration of a ROM load type FPGA,
A logic cell array unit 30 having a large number of logic circuit cells and wiring switching transistors, wherein the switching state of the switching transistors is controlled so that the logic circuit wiring is reconstructed in accordance with the control; For example, when the power is turned on or when a command signal for loading the control data from the outside is input, the RAM unit 31 stores the control data for controlling the switch state. And a load circuit section 32 for reading data from the attached ROM.

In the signal processing circuit composed of such an FPGA, the logic circuit configuration can be freely changed by changing the data written from the external ROM.

In the present invention, utilizing the characteristics of the FPGA, a ROM in which control data for forming a plurality of logic circuits corresponding to n kinds of video signal clock rates in advance, respectively, is written in a television. Mounted on camera device. Then, under the control of the CPU, one of the control data written in the ROM is selected in accordance with the clock rate of the detected video signal. Then, the selected control data is F
By being loaded into the PGA, a logic circuit configuration for realizing a video signal processing circuit for performing digital signal processing suitable for the number of pixels or the aspect ratio of the CCD frame image can be configured inside the FPGA. .

In the following, FIG.
The operation will be described with reference to FIG. 3, which shows a configuration example of a circuit block including the CPU unit 5 and the digital signal processing circuit 6. The CPU unit 5 detects the clock rate of the video signal according to the change in the number of pixels or the aspect ratio of the CCD frame image, and outputs the detection information to the ROM selection circuit 24. The ROM selection circuit 24 is connected to a plurality of ROMs. Control data corresponding to each clock rate of the video signal is stored in each of the n ROMs 21 to 23, and the control data is stored in the respective ROMs.
And input to the ROM selection circuit 24. RO
In the M selection circuit 24, based on the detection information input from the CPU unit 5, the control data output from the ROM in which the control data corresponding to the detected clock rate is stored among the n ROMs 21 to 23 is stored. Select FP
Output to GA20. By doing so, the output of the ROM containing the control data suitable for the number of CCD pixels or the aspect ratio of the frame image is selected. Therefore, when the power of the television camera device is turned on or the reloading of the control data to the FPGA 20 is instructed. When a load instruction to be executed is obtained, the selected control data is loaded into the FPGA 20.

Here, for example, when the clock rate of the video signal, that is, the clock frequency is changed without changing the circuit of the digital video signal processing circuit 6, the digital video signal processing circuit 6 realizes the digital video signal processing circuit 6. The change in the filter characteristics will be described. It is assumed that, for the video signal before the clock rate is changed, for example, a digital filter circuit having a filtering characteristic as shown in FIG. Here, when the clock rate is converted and, for example, the clock rate increases,
As shown in FIG. 5B, the characteristics change.

Therefore, according to the present invention, the clock rate conversion of the video signal is performed, and even after the conversion, the digital video signal processing circuit 6 realizes the same digital filter characteristics as those before the clock rate conversion. For this purpose, the same filter characteristics can be obtained by changing the filter coefficient value of the digital filter, the number of taps, and the like.

In the present invention, the logic circuit configuration for changing the filter coefficient value of the digital filter, the number of taps, and the like is changed by selecting control data from the ROMs 21 to 23, thereby enabling the internal logic circuit configuration of the FPGA 20 to be changed. Is suitable for each clock rate.
Digital signal processing suitable for the number of pixels or the aspect ratio of a CCD frame image can be performed without causing unit replacement or a large increase in circuit scale.

Next, a second embodiment of the present invention will be described.
This embodiment is an embodiment in which the present invention is applied to a television camera device of a type often separated into a camera head and a camera control unit (CCU), which is often used in a television camera device for broadcasting. In the television camera system shown here, when a plurality of camera heads are used, a plurality of camera heads having CCDs of different numbers of pixels are connected to one CCU, and video signals output from the camera heads to the CCU are connected. The clock rates of the two may be different.

This embodiment is also applicable to a case where video signals of different clock rates are input to the CCU and video signal processing is performed on a video signal selected from the input video signals. The digital signal processing is switched to a digital signal processing suitable for the number of pixels or the aspect ratio of the frame image of the CCD relating to the video signal, and the CCU can perform the signal processing.

The configuration and operation of this embodiment will now be described with reference to FIG.
This will be described with reference to FIG. Reference numeral 10 denotes a camera head. In this camera head 10, as in the first embodiment, a CCD
The video signal output from 1 is subjected to necessary processing such as amplification in an analog signal processing circuit 2 and then input to an A / D conversion circuit 3 where it is sampled at the same clock rate as the CCD drive clock rate. It is converted to a digital signal. The video signal digitized by the A / D conversion circuit 3 is subjected to signal processing that does not require changing the configuration of the processing circuit depending on the number of pixels or the aspect ratio of the frame image captured by the CCD 1 in the video signal processing. To a digital signal processing circuit 4 for processing.

The video signal processed and output by the digital signal processing circuit 4 is input to the digital signal transmission unit 13 and multiplexed together with the data signal including the number of CCU pixels and the aspect ratio information output from the CPU 12. You. The signal multiplexed by the digital signal transmission unit 13 is output from the camera head 10 and is output from the CCU 11
Transmitted to

The CCU 11 receives a signal from the camera head 10. Further, a similar signal is input from the camera head 10 'or the camera head 10 ".
The signals transmitted from these multiple camera heads are
It is input to the digital signal receiving unit 14 of the CCU 11.

In the digital signal receiving unit 14, a predetermined signal is selected from the signals input from the plurality of camera heads, and the CPU unit 1 is selected from the selected signal.
2 and a video signal. Then, it outputs the separated data signal to the CPU section 15 and outputs the separated video signal to the digital signal processing circuit 6 using a ROM load type FPGA. The configuration of the digital signal processing circuit 6 is exactly the same as the digital signal processing circuit 6 of the first embodiment shown in FIG.
The digital signal processing circuit 6 includes the CPU 1
Under the control of 5, the signal processing according to the clock rate of the video signal from the selected camera head is performed.

The digital video signal 17 processed in this way is converted into an analog video output signal by the D / A converter 7 or is converted into a digital video output signal via the digital I / F circuit 8 at a subsequent stage (not shown). Is output to

As described above, a CCD having a different number of pixels can be provided in the same CCU without replacing the units required in the conventional system or providing a plurality of circuits in parallel to increase the circuit configuration. A plurality of camera heads can be connected, and the operability of the camera system can be greatly improved.

In the above description, an FPGA is used as an element for performing digital signal processing suitable for the number of pixels of a CCD based on data stored in a ROM, but a DSP (digital signal processor) may be used instead. The same effect can be obtained.

[0036]

As described above, according to the present invention,
Digital signal processing suitable for the number of pixels of the CCD or the aspect ratio of the frame image can be easily performed,
In addition, the operability of the system can be improved as well as the size and cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block configuration of an embodiment of a television camera device according to the present invention.

FIG. 2 is a diagram showing a block configuration of another embodiment of the television camera device of the present invention.

FIG. 3 is a diagram showing an example of a block configuration of a digital signal processing circuit according to the present invention.

FIG. 4 is a diagram showing an example of an internal block configuration of a ROM load type FPGA;

FIG. 5 is a diagram for explaining frequency characteristics of a digital filter.

[Explanation of symbols]

1: CCD image sensor 2: A / D conversion circuit 3: Analog signal processing circuit 4: Digital signal processing circuit
5, 12, 15: CPU unit, 6, 16: digital signal processing circuit, 7: D / A conversion circuit, 8: digital interface circuit.

Claims (2)

[Claims] 1. A television camera device for performing video signal processing, wherein a sampling clock rate of the video signal is detected, and a field programmable circuit constituting a video signal processing circuit according to the detected sampling clock rate. By selecting the corresponding circuit configuration information of a logic device (hereinafter referred to as an FPGA) and providing the selected circuit configuration information to the FPGA, the FPG
A television camera device, wherein the circuit configuration of A is a video signal processing circuit configuration corresponding to the detected sampling clock rate. 2. A television camera apparatus for performing video signal processing, comprising: means for detecting a sampling clock rate of the video signal; and a field programmable logic device (hereinafter referred to as FPGA) constituting a circuit for performing the video signal processing. ), Means for storing circuit configuration information for the FPGA, and means for controlling output of circuit configuration information corresponding to the detected sampling clock rate from the storage means to the FPGA. A television camera device, wherein the FPGA constitutes a video signal processing circuit according to the detected sampling clock rate.