JP2000040827A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: In a semiconductor device using a flattening film, when opening different wiring layers under the flattening film at the same time, to prevent excessive or under etching without increasing the number of steps. To provide a method of manufacturing a semiconductor device capable of performing the following. SOLUTION: In a region where a lower layer wiring (short-circuit line) 16a is formed, the thickness of a flattening film 37 formed thereon is relative to the thickness of the flattening film 37 other than the lower layer wiring 16a. A dummy wiring D is formed to make it thinner. Also,
By not removing the interlayer insulating film 33 or the upper wiring (conductive film) on the lower wiring 16a before forming the flattening film 37, the flattening film 37 on the lower wiring 16a is formed relatively thin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more specifically, to a semiconductor device including a plurality of wiring layers and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, when a semiconductor device is formed by laminating one or more wiring layers and one or more insulating layers, a plurality of overlapping wiring layers or insulating layers are processed by etching or the like. There are many cases where the opening is made by the following method.

As an example of forming an opening in a semiconductor device as described above, a short-circuit line for electrostatic breakdown is previously formed at the time of manufacturing an active matrix substrate or the like formed on an insulating substrate, and this is formed after manufacturing. The case of removal will be described below.

That is, in the case of manufacturing a semiconductor device as described above, it has conventionally been necessary to form the semiconductor device on an insulating substrate, such as glass, in order to effectively prevent electrostatic breakdown due to static electricity during the manufacturing. If so, it is a mandatory requirement.

In this case, various methods have conventionally been used to prevent the electrostatic breakdown. Among them, the most effective one is a short-circuit wire for preventing electrostatic breakdown (generally, a short ring or a short ring). This is a method in which an active matrix substrate or the like is manufactured while forming a guard ring in advance, and the short-circuit line is removed after completion.

According to this method, electrostatic breakdown does not occur until the short-circuit line is removed, so that the active matrix substrate and the like can be effectively protected.

Here, regarding a manufacturing process of an active matrix substrate or the like including the short-circuit line, a thin film transistor (hereinafter simply referred to as T) in a pixel portion formed in a display region of a liquid crystal display device as the active matrix substrate or the like.
It is called FT (Thin Film Transistor). ) Is described as an example.

First, as a first step, a semiconductor layer to be a source region, a channel region and a drain region of a TFT is formed on a substrate, and a gate insulating film is formed thereon.

Next, as a second step, a gate electrode is formed above the channel region on the gate insulating film, and the short-circuit line is laminated at a predetermined position with a metal.

Further, as a third step, a first interlayer insulating layer is laminated on a region of the TFT including the gate electrode and the short-circuit line, and a portion corresponding to the short-circuit line of the first interlayer insulating layer is opened to open the short-circuit line. And, in parallel with this, contact holes are respectively formed by opening portions of the first interlayer insulating layer corresponding to the source region and the drain region, and then the first interlayer insulating layer is connected to the contact holes. A source electrode and a drain electrode are formed over the insulating layer.

Then, as a fourth step, an insulating layer is formed as a flattening film on the entire substrate including on the opened short-circuit line and on the source electrode and the drain electrode.

Next, as a fifth step, the flattening film on the short-circuit line and the flattening film on the drain electrode are opened by photolithography and etching.

Then, as a sixth step, a contact hole is formed in the opening on the drain electrode, and a pixel electrode is formed on the flattening film so as to be connected to the contact hole.

Finally, as a seventh step, the pixel electrode is masked, and the short-circuit line having an open upper portion is removed by etching or the like to complete the TFT.

[0015]

However, in the above-described conventional manufacturing process, it is desirable that the short-circuit line be formed as early as possible after the start of TFT manufacturing. According to the manufacturing process, when opening the portion of the short-circuit line and the portion of the drain electrode after the formation of the planarization film (the fifth step), the insulating film (the fifth The thickness of the first interlayer insulating layer plus the thickness of the drain electrode is greater than the thickness of the insulating film at the drain electrode portion. The thickness is increased accordingly (the difference is often, for example, about 5000 Å).

On the other hand, when the short-circuit line is completely removed after the formation of the pixel electrode, it is permissible to overetch the short-circuit line when opening the insulating layer on the short-circuit line in the fifth step. Is not recognized as being insufficiently etched, but when a contact hole for connection with a pixel electrode is formed on the drain electrode, the taper shape and size of the opening of the flattening film are strictly adjusted to some extent. It must be formed, and therefore, when opening the opening for the contact hole, the etching cannot be excessive.

Accordingly, the portion of the insulating layer which is desired to be over-etched becomes thicker, whereas the portion of the insulating layer which cannot be excessively etched becomes thinner, and these openings are formed in one step (the fifth step). If you try to go inside
If the specifications of the etching are set so as to be suitable for the removal of the insulating layer at the drain electrode portion, the short-circuit line cannot be sufficiently opened afterwards, and the short-circuit line cannot be completely removed thereafter. If the specifications of the etching are set so as to be suitable for the removal of the insulating layer, there is a problem that the drain electrode portion is excessively etched and the electrical conductivity and the like of the drain electrode deteriorate.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device using a flattening film, which is used for simultaneously opening different wiring layers under the flattening film. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing excessive or under-etching without increasing the amount of etching.

[0019]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention is a semiconductor device formed by stacking a plurality of insulating films and a plurality of wiring layers on a substrate. A flattening insulating film for flattening a step caused by the wiring layer in the insulating film is formed, and an opening is partially formed in the flattening insulating film. Is characterized by forming a dummy pattern.

Therefore, since the insulating layer is thin by the thickness of the dummy pattern, the insulating film can be easily removed at the time of manufacturing the semiconductor device.

Further, the method of manufacturing a semiconductor device according to the present invention
In a method of manufacturing a semiconductor device formed by laminating a plurality of insulating films and a plurality of wiring layers on a substrate, a wiring forming step of forming a wiring layer on the substrate; A flattening insulating film forming step of forming one insulating film of the insulating films as a flattening film for flattening a step caused by the wiring layer on one wiring layer; and partially forming the flattening film. A flattening insulating film opening step of opening, and a dummy pattern forming step of forming a dummy pattern,
The dummy pattern is formed in a layer below an opening formed in the flattening film.

Still further, the present invention relates to a method of manufacturing a semiconductor device formed by laminating a plurality of insulating films and a plurality of wiring layers on a substrate.
An interlayer insulating layer forming step of forming one insulating layer of the plurality of insulating films as an interlayer insulating layer, and a flattening film formed above the interlayer insulating layer and flattening a step caused by the wiring layer A flattening insulating film forming step of forming an insulating film as a step; and a flattening insulating film opening step of partially opening the flattening film. The etching rate of the layer is higher than the etching rate of the planarizing film, and during the step of opening the planarizing insulating film, the interlayer insulating layer formed below the opening formed in the planarizing film is simultaneously removed. It is characterized by doing.

Therefore, compared to the case where the interlayer insulating film has been removed in advance, the flattening insulating film having a lower etching rate becomes thinner and the total etching time is reduced, so that the insulating layer can be surely removed.

Still further, according to the present invention, there is provided a method of manufacturing a semiconductor device formed by laminating a plurality of insulating films and a plurality of wiring layers on a substrate.
An interlayer insulating layer forming step of forming one insulating layer of the plurality of insulating films as an interlayer insulating layer; a wiring layer forming step of forming the plurality of wiring layers on the interlayer insulating layer; A flattening insulating film forming step of forming the insulating film as a flattening film for flattening a step caused by the wiring layer in an upper layer; and a flattening insulating film opening step of partially opening the flattening film. Then, the wiring layer is simultaneously removed in the step of opening the planarization insulating film.

Therefore, compared with the case where the wiring is removed in advance, the flattening insulating film becomes thinner, and the insulating layer can be surely removed.

Further, the method of manufacturing a semiconductor device according to the present invention
In addition to the above configuration, in the planarizing insulating film opening step, at least two different wiring layers among the plurality of wiring layers are simultaneously exposed. Therefore,
The thickness of the flattening film on each wiring layer can be appropriately adjusted, and the opening of the flattening film can be formed without causing excessive etching or insufficient etching.

Further, the method of manufacturing a semiconductor device according to the present invention
In addition to the above configuration, the method further includes a short-circuit line forming step of forming a short-circuit line for preventing electrostatic breakdown of the semiconductor device, wherein the exposed wiring layer is the short-circuit line.

Therefore, when a flattening insulating layer is formed on the short-circuit line and in a region other than the short-circuit line, and when the insulating layer on the short-circuit line is subsequently opened, the insulating film on the short-circuit line is formed thinner. Thus, the short-circuit line can be reliably exposed.

Further, since the semiconductor device of the present invention is formed by the above-described method for manufacturing a semiconductor device, occurrence of defects due to overetching or underetching of the opening on the flattening film is small, and the number of steps is small. Therefore, it can be manufactured at low cost.

[0030]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. The embodiment described below is an active matrix type liquid crystal display device as an active matrix substrate or the like, and the present invention is applied to a method for manufacturing a liquid crystal display device having a short-circuit line for preventing electrostatic breakdown. This is an embodiment when applied.

(I) Embodiment of Liquid Crystal Display Device First, as an embodiment of an active matrix type liquid crystal display device manufactured according to the present invention, a configuration of an active matrix device for a liquid crystal panel will be described.

First, the overall configuration of the active matrix device will be described with reference to FIG. In addition, FIG.
A state is shown in which a plurality of active matrix devices 1 of the embodiment are formed in a matrix on one large glass substrate.

That is, the active matrix device 1 in this state is subjected to a substrate cutting step of cutting along a substrate cutting line indicated by a dotted line in the figure, and further to a panel chamfering step as necessary. Each is an active matrix device.

As shown in FIG. 1, the active matrix device 1 includes a substrate 10 made of a glass substrate, a quartz substrate, or the like, and an image display region 11 located on the center side of the substrate 10 is provided with a liquid crystal driving device. A plurality of pixel portions each including a pixel electrode and a TFT are formed in a matrix.

The active matrix device 1 includes a plurality of scanning lines (gate wirings) 12 connected to the gate electrodes of TFTs in a plurality of pixel portions, and a plurality of data lines (source wirings) connected to the source electrodes of the TFTs. ) 13, a short-circuit line 16a as a protection pattern for preventing electrostatic breakdown,
Is provided.

The active matrix device 1 includes a scanning line driving circuit 14 for supplying a scanning signal to the scanning lines 12 and a data line driving circuit 15 for supplying a data signal to the data lines 13 around the image display area 11. Is provided. At this time, the scanning line driving circuits 14 are provided on both sides of the image display area 11.

In the following description, in addition to the circuit for directly supplying a data signal during the normal operation of a liquid crystal panel completed by incorporating the active matrix device 1, the data line 13 is boosted to a predetermined potential before the data signal is supplied. A pre-charge circuit for supplying a pre-charge signal for sampling, a sampling circuit for sampling an analog image signal and supplying it to the data line 13, and supplying a predetermined electric signal to the data line 13 at the time of electrical inspection of the circuit and wiring. Such as an inspection circuit for supplying an electric signal to a data line is collectively referred to as a data line driving circuit 15.

Next, a specific configuration of the short-circuit line 16a as the above-mentioned protection pattern will be described with reference to FIG.

In FIG. 2, the short-circuit line 16a is, for example,
Initial stage of manufacture of the active matrix device 1 (specifically,
For example, at the time of forming a gate electrode 24 described later), the scanning line 1
2 is formed from the same conductive film as a polysilicon film or the like, and is closer to the center (that is, closer to the image display area) than the scanning line drive circuit 14 and the data line drive circuit 15 in each active matrix device 1. The scanning lines 12 and the data lines 13 are wired along the periphery of the image display area, and are connected to each other with a short circuit or a predetermined resistance.

(II) First Embodiment of Manufacturing Method Next, an active matrix device 1 including a short-circuit line 16a
A first embodiment of a manufacturing method according to the present invention for manufacturing a semiconductor device will be described with reference to FIGS.

FIGS. 3 to 6 show a pixel portion TFT (LDD (Lightly D)) formed in each pixel portion in the display area 11 in the short-circuit line 16a of the active matrix device 1. FIG.
opedDrain) TFT and scanning line driving circuit 1
4 is a cross-sectional view schematically illustrating a manufacturing process of a driver TFT (TFT having an LDD structure) included in either the data line driving circuit 4 or the data line driving circuit 15. FIG. Further, in each cross-sectional view, the left side of the drawing shows the manufacturing process of the pixel portion TFT, the center shows the manufacturing process of the driver TFT, and the right side of the drawing shows the manufacturing process of the short-circuit line 16a. .

In the manufacture of the active matrix device 1, first, as shown in FIG. 3A, as a first step, for example, a CVD (Chemical)
A base film 20 is formed to a thickness of about 500 to 5000 angstroms by a vapor deposition method, and a silicon film is formed on the base film 20 by a low pressure CVD method, a normal pressure CVD method, a plasma CVD method, a sputtering method, or the like. Then, the formed silicon film is crystallized by annealing in a 400 to 1200 ° C. atmosphere or irradiation of laser light, and the like, to form a crystalline silicon semiconductor layer 21.

At this time, as a material of the substrate 10, a non-alkali glass, a quartz substrate or the like is used.

Next, as shown in FIG. 3B, as a second step, the formed silicon semiconductor layer 21 is patterned by photolithography to form a pixel portion TF.
A semiconductor layer 23 constituting T, and a driver T
A semiconductor layer 23 that constitutes the FT;
A dummy electrode D is formed as a dummy wiring for forming a in a relatively upper layer.

[0045] Then, 100 SiN, formed of SiO _2, Ta ₂ 0 _5, etc. on the said semiconductor layer 23 and the dummy electrodes D
Gate insulating film 2 having a thickness of 2000 to 2000 Å
Form 2

In this case, for example, a CVD method or a sputtering method is used.

In forming the pattern shown in FIG. 3B, the surface of the silicon semiconductor layer 21 is thermally oxidized to form a gate insulating film 22 having a desired thickness. Each of the semiconductor layers 23 and the dummy electrodes D may be formed by performing the polishing.

Further, in the case where the semiconductor layer 23 is made conductive, the mask material is patterned by photolithography as necessary, and then the mask material is patterned at 10 ¹⁴ ion / m ^{2 to} 1
Ion such as P or B may be implanted into the surface of the semiconductor layer 23 at a dose of about 0 ¹⁶ ion / m ² .

Next, as shown in FIG. 3C, as a third step, a conductive film is formed on the formed gate insulating film 22 by a sputtering method or the like, and the conductive film is formed by a photolithography process. It is patterned into a predetermined shape, and the gate electrode 24 as each TFT and the short-circuit line 16a for countermeasures against static electricity
To form

At this time, the short-circuit line 16a is formed in the same layer as the gate electrode 24 because the dummy electrode D is formed below the short-circuit line 16a.

The material of the gate electrode 24 is A
l, Ti (titanium), Ta (tantalum), Cr (chromium),
It can be configured to have a single material such as Mo (molybdenum), W (tungsten), Si, Cu, or the like, an alloy thereof, or a laminated structure thereof.

Next, as shown in FIG. 4 (a), as a fourth step, an n ⁺ region serving as a drain or source in the semiconductor layer 23 of the pixel portion TFT is formed so as to correspond to the driver TFT. A mask 25 patterned by photolithography is formed on a region of the semiconductor layer 23 of the pixel portion TFT in which the region and the n ⁺ region are not formed, and 10.
Ions such as B (boron) are implanted at a dose of about ^{14 to} 10 ¹⁶ ions / m ² to form the n ⁺ region 26.

Next, as shown in FIG. 4B, as a fifth step, the mask 25 formed in FIG. 4A is removed, and the drain or source in the semiconductor layer 23 of the driver TFT is formed. In order to form a p ⁺ region,
A mask 25 patterned by photolithography is formed on the region of the semiconductor layer 23 of the driver TFT where the region corresponding to the pixel portion TFT and the p ⁺ region are not formed, and a dose of about 10 ^{14 to} 10 ¹⁶ ions / m ² is formed. P by quantity
Ions such as (phosphorus) are implanted to form the p ⁺ region 27.

Next, as shown in FIG. 4C, as a sixth step, the mask 25 formed in FIG. 4B is removed, and n is set so that the pixel portion TFT has an LDD structure. ^In order to form a region, if necessary, a mask 25 patterned by photolithography is formed on a region corresponding to the driver TFT and a region of the semiconductor layer 23 of the pixel portion TFT where the n ^- region is not formed, 10
Ions such as B are implanted at a dose of about ^{11 to} 10 ¹⁴ ions / m ² to form the n ⁻ region 28.

According to this step, two n ⁻ regions 28 and two n ⁻ regions 28 are formed in the portion that was the semiconductor layer 23 of the pixel portion TFT.
⁺ Region 26 and one channel region 29 are formed,
As a result, a pixel portion TFT having an LDD structure is formed.

[0056] Further, as shown in FIG. 5 (a), as the seventh step, to remove the mask 25 formed in FIG. 4 (c), the order of the driver TFT and TFT of LDD structure p ^- In order to form a region, a mask 25 patterned by photolithography is formed on a region corresponding to the pixel portion TFT and a region of the semiconductor layer 23 of the driver TFT where no p ⁻ region is formed, and 10 ^{11 to} 1
Implanting ions such as P, in 0 ¹⁴ ion / ^{m 2} dose of about, the to form p ^- region 31.

According to this step, two p ⁻ regions 31 and two p ⁺ regions 27
One channel region 30 is formed, thereby forming an LD
A driver TFT having a D structure is formed.

Here, the four steps shown in FIG. 4 and FIG. 5A may be interchanged.

The n ⁻ region 28 and the p ⁻ region 31 are not necessarily provided, and the driver TFT may have a so-called self-aligned structure using the gate electrode 24 as a mask material. .

Next, as shown in FIG. 5 (b), as an eighth step, the mask 25 formed in FIG. 5 (a) is removed, and SiO ₂ is formed on the devices formed so far by the CVD method.
An interlayer insulating film 33 is formed as a sub-insulating layer.

The thickness of the interlayer insulating film 33 is, for example, 1
It is about 000 to 8000 angstroms.

After forming the interlayer insulating film 33,
N ⁺ by photolithography and etching
A contact hole reaching the region 26 or the p ⁺ region 27 is formed. At this time, no opening is provided on the short-circuit line 16a.

Next, as shown in FIG. 5 (c), as a ninth step, the position of the formed contact hole and the upper surface of the interlayer insulating film 33 are reduced to a thickness of about 1000 to 10000 angstroms by sputtering or the like. A conductive film is formed and is patterned into a predetermined shape by using a photolithography process to form a source electrode 35 and a drain electrode 36 as each TFT.

At this time, the conductive film above the short-circuit line 16a has been removed.

At this time, the material of the source electrode 35 and the drain electrode 36 (that is, the conductive film) is A
It can be configured to have a single material such as l, Ti, Ta, Cr, Mo, W, Si, Cu, or an alloy thereof, or a laminated structure thereof.

Next, as shown in FIG. 6A, as a tenth step, a flattening film 37 as an insulating sub-insulating layer made of SiO ₂ is formed to a thickness of about 1000 to 8000 Å by spin coating. Form.

More specifically, perhydropolysilazane or a composition containing the same is spin-coated as a solvent and baked to form a flattening film 37 made of SiO ₂ . At this time, a material or a forming method is selected so that the surface of the flattening film 37 is as flat as possible.

Thereafter, a contact hole is opened on the drain electrode 36 of the pixel portion TFT by photolithography and etching, and the short-circuit line 16a is also opened in the same step.

In the etching process at this time, openings are formed by wet etching using, for example, a mixed solution of HF (hydrogen fluoride) and NH ₄ F ammonium fluoride.

Here, for the element immediately after the formation of the planarizing film 37 (see FIG. 6A), the drain electrode 3
6 and the upper part of the short-circuit line 16a, there is only the flattening film 37 on the drain electrode 36.
A thin flattening film 37 and an interlayer insulating film 33 are laminated on a due to the presence of the dummy electrode D.

At this time, the flattening film 37 and the interlayer insulating film 33
Comparing the etching rates with each other, the flattening film 37 has a lower etching rate than the interlayer insulating film 33 due to the difference in the manufacturing method described above.

Therefore, the flattening film 37 having a low etching rate on the short-circuit line 16a is formed thinner, so that the contact hole on the drain electrode 36 and the opening on the short-circuit line 16a are eventually formed. In the above etching step, the drain electrode 36 is not excessively etched, while the short-circuit line 16a is sufficiently etched.

As a result, the tapered shape and the size of the contact hole of the flattening film 37 can be formed to some extent strictly, and the opening on the short-circuit line 16a can be reliably formed.

Finally, as shown in FIG.
As a process, after a transparent conductive film such as ITO (Indium Tin Oxide) is formed with a thickness of about 1000 to 3000 angstroms by a sputter method or the like, the mask 41 is removed using photolithography and etching, and the pixel electrode 40 is patterned. .

At this time, an opening is formed on the short-circuit line 16a without forming the mask 41, and before the mask 41 is removed, the mask 41 on the pixel electrode 40 and the mask 41 are removed in the process of FIG. After the short-circuit line 16a is removed by etching using the formed flattening film 37 as a mask, the mask 41 is removed.
Then, the active matrix device 1 having the pixel portion TFT and the driver TFT is finally completed (see FIG. 6C).

According to the manufacturing method of the first embodiment described above, the flattening film 37 on the short-circuit line 16a can be flattened on the other pixel portion TFTs and the like by not removing the dummy electrode D and the interlayer insulating film 33. Since the film is relatively thin with respect to the film 37, it is possible to open the short-circuit line 16a without affecting other pixel portion TFTs and the like, and to form the short-circuit line 16a.
Can also be reliably removed.

Further, a flattening film 37 having a low etching rate and an interlayer insulating film 33 having a high etching rate are laminated and formed on the short-circuit line 16a.
Since only the flattening film 37 is laminated on the like, the short-circuit line 16a
The upper planarizing film 37 and the interlayer insulating film 33 are etched earlier, so that the short-circuit line 16a can be exposed and removed more quickly and reliably without affecting the pixel portion TFT and the like.

Further, since the short-circuit line 16a is formed at the same time when the gate electrode 24 of the TFT is formed, it is possible to prevent electrostatic breakdown from the formation of the gate electrode 24 to the completion of the active matrix device 1.

(III) Second Embodiment of Manufacturing Method Next, the active matrix device 1 including the short-circuit line 16a
A second embodiment, which is another embodiment of the manufacturing method according to the present invention, for manufacturing a semiconductor device will be described.

In the above-described first embodiment, the short-circuit line 16a and the drain electrode 36 and the source electrode 35 are formed to have the same height (within the same layer) as a result. In the case of, over-etching on the drain electrode is prevented by forming the drain electrode in which a contact hole for connecting to the pixel electrode is opened in a relatively lower layer.

That is, when the contact hole is formed in FIG. 5B, at the same time, in FIG. 6B, the drain electrode 36 is connected to the pixel electrode 40 and the interlayer insulating film corresponding to the portion of the drain electrode 36 in FIG. By removing 33, the drain electrode 36 is connected to the pixel electrode 40 and the flattening film 3 on the portion of the drain electrode 36.
7 is made thicker.

As a result, since the flattening film 37 on the portion where the drain electrode 36 is connected to the pixel electrode 40 is thick, the drain electrode 36 is formed when a contact hole is formed in the flattening film 37 other than the portion. Damage can be prevented.

(IV) Third Embodiment of Manufacturing Method Next, the active matrix device 1 including the short-circuit line 16a
A third embodiment, which is another embodiment of the manufacturing method according to the present invention for manufacturing a semiconductor device, will be described with reference to FIGS.

In the first and second embodiments, the conductive film serving as the source electrode 35 or the drain electrode 36 is not formed on the short-circuit line 16a.
However, in the third embodiment, instead of the interlayer insulating film 33 on the short-circuit line 16a, a conductive film serving as the source electrode 35 or the drain electrode 36 is formed on the short-circuit line 16a, and a flat surface is formed thereon. By forming the passivation film 37, the flattening film 37 on the short-circuit line 16a is relatively thinned.

In the manufacturing method according to the third embodiment, since the steps up to the step shown in FIG. 5A are completely the same as those in the first embodiment, detailed description will be omitted.

In the manufacturing method of the third embodiment, FIG.
In each of the first to seventh steps up to the step shown in FIG.
Is formed, the mask 2 formed in FIG.
5 is removed, and then an interlayer insulating film 33 is formed on the device thus far formed by the same method as that shown in FIG.

Then, after forming the interlayer insulating film 33,
N ⁺ by photolithography and etching
A contact hole reaching the region 26 or the p ⁺ region 27 is formed.

At this time, the interlayer insulating film 3 on the short-circuit line 16a
3 is also removed at the same time.

Next, a conductive film having a thickness of about 1000 to 10000 angstroms is formed by the same method as that shown in FIG. 5C, and the conductive film is patterned into a predetermined shape by photolithography. A source electrode 35 and a drain electrode 36 as a TFT are formed.

At this time, the dummy pattern 45 is formed without removing the conductive film above the short-circuit line 16a (see FIG. 7A).

Next, as shown in FIG. 7B, as a tenth step, a method similar to that shown in FIG.
The planarizing film 37 is formed to a thickness of about 1000 to 8000 angstroms.

Thereafter, a contact hole is opened on the drain electrode 36 of the pixel portion TFT by photolithography and etching, and a short-circuit line 16a is also opened.

Here, with respect to the device after the formation of the flattening film 37 is completed, the upper part of the drain electrode 36 and the short-circuit line 16
Compared to the upper part of FIG. a, there is only the planarization film 37 on the drain electrode 36, but the relatively thin planarization film 37 and the dummy pattern 45 on the short-circuit line 16 a due to the presence of the dummy electrode D. Are laminated. At this time, for example, wet etching with a solution containing HF is performed as an etching method of the flattening film opening and Al is selected as the drain electrode material, so that Al is simultaneously etched at the time of opening the flattening film.

Therefore, the flattening film 37 having a low etching rate is formed thick on the drain electrode 36, while the flattening film 37 having a low etching rate is formed thin on the short-circuit line 16a. Similarly to the first embodiment, in the formation of the contact hole on the drain electrode 36 and the etching process for the opening on the short-circuit line 16a, the drain electrode 36 is not excessively etched. Thus, the short-circuit line 16a is sufficiently etched. If the dummy pattern is not completely etched, or if a combination that can also etch the drain electrode as described above is not selected for the etching method at the time of opening the flattening film and the drain electrode material, as described later. Then, the dummy pattern may be removed during the short-circuit line removing step. As described above, the tapered shape and the size of the contact hole of the flattening film 37 can be formed to some extent strictly, and the opening on the short-circuit line 16a can be surely formed.

Finally, as shown in FIG.
As a process, after a transparent conductive film such as ITO is formed to a thickness of about 1000 to 3000 Å by a sputtering method or the like, the mask 41 is patterned by using a photolithography process and an etching process to form the pixel electrode 40.

At this time, an opening is formed on the short-circuit line 16 a without forming the mask 41, and before the mask 41 is removed, a short-circuit is performed using the mask 41 on the pixel electrode 40 and the flattening film 37. Line 16a and possibly dummy pattern 4
5 is removed by etching, and then the mask 41 is peeled off.
The active matrix device 1 having the FT is completed (see FIG. 8B).

Here, the short-circuit line 16a and the dummy pattern 45 may be removed by separate etching steps. Alternatively, if the material of the dummy pattern 45 is Al as described above, the planarizing film may be removed. If a solution containing HF is used as an etchant at the time of removing 37, the dummy pattern 45 can be removed at the same time as opening the contact hole.

The dummy pattern 45 and the short-circuit line 16a
Is formed of the same material or of a material that can be removed by the same etching process, so that the dummy pattern 45 can be removed in the same step when removing the short-circuit line 16a.

According to the manufacturing method of the third embodiment described above, the presence of the dummy electrode D and the dummy pattern 45 allows the flattening film 37 on the short-circuit line 16a to be relatively thin compared to the case where these are not provided. The short-circuit line 16
When a is removed, the short-circuit line 16a can be opened and the short-circuit line 16a can be reliably removed without affecting other pixel unit TFTs.

Further, since the short-circuit line 16a is formed at the same time when the gate electrode 24 of the TFT is formed, it is possible to prevent electrostatic breakdown from the formation of the gate electrode 24 to the completion of the active matrix device 1.

(V) Embodiment of Liquid Crystal Panel Next, an embodiment of a liquid crystal panel provided with the active matrix device 1 of the present invention will be described with reference to FIGS. FIG. 9 is a plan view of the substrate 10 as viewed from the counter substrate side of the liquid crystal panel, and FIG. 10 is a cross-sectional view taken along the line HH ′.

As shown in FIGS. 9 and 10, the liquid crystal panel is composed of the above-described active matrix device 1 in which various wirings, elements, and the like are formed on a substrate 10 and a glass substrate or the like arranged opposite to the substrate 10. Opposing substrate B and substrate 10
And a counter substrate B along the contour of the image display area 11 and a liquid crystal layer 50 sealed between the substrate 10 and the counter substrate B by the seal member 52. .

In the area outside the sealing material 52, the scanning line driving circuit 14, the data line driving circuit 15, the mounting terminals 19, and a plurality of wirings 105 for connecting these are provided.

Further, at least one corner of the counter substrate B, the TFT array substrate 10 and the counter substrate B
Vertical conductive material (silver point) 1 for establishing electrical continuity between
06 is provided.

In FIG. 10, the liquid crystal layer 50 is made of, for example, a kind of nematic liquid crystal or a liquid crystal in which several kinds of nematic liquid crystals are mixed.

Further, the sealing material 52 is an adhesive made of, for example, a photo-curable resin or a thermo-curable resin for bonding the two substrates 10 and the opposing substrate B around them, and a distance between the two substrates 10 and B. A gap material (spacer) such as glass fiber or glass beads for setting the (inter-substrate gap) to a predetermined value is mixed.

Since the liquid crystal panel configured as described above includes the above-described active matrix device 1, the defective product rate due to electrostatic breakdown is extremely low.

At this time, as described above, the short-circuit line 16a is removed during the manufacturing process of the TFT in the pixel portion, but partially remains even when the active matrix device 1 is incorporated in the liquid crystal panel. In some cases.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a configuration of an active matrix device.

FIG. 2 is a plan view showing a configuration of a protection pattern in the active matrix device.

3A and 3B are schematic cross-sectional views illustrating a first embodiment of a manufacturing process of an active matrix device, FIG. 3A is a schematic cross-sectional view illustrating a first step, and FIG. 3B is a schematic cross-sectional view illustrating a second step. It is a cross section schematic diagram, (c) is a cross section schematic diagram showing a 3rd process.

FIG. 4 is a schematic cross-sectional view (II) showing a first embodiment of the manufacturing process of the active matrix device, (a) is a schematic cross-sectional view showing a fourth step, and (b) is a fifth step. It is a cross section schematic diagram, (c) is a cross section schematic diagram which shows a 6th process.

FIG. 5 is a schematic cross-sectional view (III) showing the first embodiment of the manufacturing process of the active matrix device, and FIG.
It is a cross section showing a process, (b) is a cross section showing an eighth step, and (c) is a cross section showing a ninth step.

FIG. 6 is a schematic cross-sectional view (IV) showing a first embodiment of the manufacturing process of the active matrix device, and FIG.
It is a cross section showing a process, (b) is a cross section showing an eleventh process, and (c) is a cross section showing a completed active matrix device.

FIGS. 7A and 7B are schematic sectional views showing a third embodiment of the manufacturing process of the active matrix device, wherein FIG. 7A is a schematic sectional view showing a ninth step, and FIG. It is a cross section schematic diagram.

FIG. 8 is a schematic sectional view (II) showing a third embodiment of the manufacturing process of the active matrix device, and (a) is an eleventh embodiment.
FIG. 4 is a schematic cross-sectional view illustrating a process, and FIG. 4B is a schematic cross-sectional view illustrating a completed active matrix device.

FIG. 9 is a plan view of the liquid crystal panel as viewed from a counter substrate side.

FIG. 10 is a sectional view of the liquid crystal panel taken along line HH ′ in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Active matrix device 10 ... Substrate 11 ... Image display area 12 ... Scan line 13 ... Data line 14 ... Scan line drive circuit 15 ... Data line drive circuit 16a ... Short circuit line 20 ... Underlayer 21 ... Silicon semiconductor layer 22 ... Gate insulation Film 23 semiconductor layer 24 gate electrode 25 41 mask 26 n ⁺ region 27 p ⁺ region 28 n ^- region 29 30 channel region 31 p ^- region 33 interlayer insulating film 35 source electrode 36 ... Drain electrode 37 ... Planarization film 40 ... Pixel electrode 45 ... Dummy pattern 50 ... Liquid crystal layer 52 ... Seal material B ... Counter substrate D ... Dummy electrode

Claims (7)

[Claims] 1. A semiconductor device formed by stacking a plurality of insulating films and a plurality of wiring layers on a substrate,
A flattening insulating film for flattening a step caused by the wiring layer in the insulating film is formed, and an opening is partially formed in the flattening insulating film. Wherein a dummy pattern is formed on the semiconductor device. 2. A method for manufacturing a semiconductor device formed by laminating a plurality of insulating films and a plurality of wiring layers on a substrate, wherein: a wiring forming step of forming a wiring layer on the substrate; Forming, on one of the wiring layers, one of the insulating films as a flattening film for flattening a step caused by the wiring layer; A flattening insulating film opening step of partially opening the film; and a dummy pattern forming step of forming a dummy pattern, wherein the dummy pattern is formed below the opening formed in the flattening film. A method for manufacturing a semiconductor device, comprising: 3. A method for manufacturing a semiconductor device formed by stacking a plurality of insulating films and a plurality of wiring layers on a substrate, wherein one of the plurality of insulating films is used as an interlayer insulating layer. Forming an interlayer insulating layer, forming an insulating film as a flattening film formed above the interlayer insulating layer and flattening a step caused by the wiring layer; and forming the flattening insulating film. A flattening insulating film opening step of partially opening the film, wherein the etching means for opening the flattening film has a characteristic that an etching rate of the interlayer insulating layer is higher than an etching rate of the flattening film. And a step of removing at least a part of the interlayer insulating layer formed below the opening formed in the planarizing film in the step of opening the planarizing insulating film. 4. A method for manufacturing a semiconductor device formed by stacking a plurality of insulating films and a plurality of wiring layers on a substrate, wherein one of the plurality of insulating films is used as an interlayer insulating layer. An interlayer insulating layer forming step of forming, a wiring layer forming step of forming a plurality of the wiring layers on the interlayer insulating layer, and a flattening film for flattening a step caused by the wiring layer above the wiring layer. A flattening insulating film forming step of forming the insulating film, and a flattening insulating film opening step of partially opening the flattening film. At the time of the flattening insulating film opening step, at least the wiring layer A method for manufacturing a semiconductor device, wherein a part is removed at the same time. 5. The method for forming a semiconductor device according to claim 2, wherein in the step of opening the planarizing insulating film,
A method of manufacturing a semiconductor device, wherein at least two different wiring layers among the plurality of wiring layers are simultaneously exposed. 6. The method for forming a semiconductor device according to claim 5, further comprising a short-circuit line forming step of forming a short-circuit line for preventing electrostatic breakdown of the semiconductor device, wherein the exposed wiring layer is formed. A method for manufacturing a semiconductor device, comprising the short-circuit line. 7. A semiconductor device manufactured by the method for forming a semiconductor device according to claim 2. Description: