JP2000035916A - Memory operation management method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten data rewrite time inside a flash memory. SOLUTION: The flash memory is managed by being divided into a primary memory 12 for storing data during use at present, a secondary memory 13 for storing the data used before and a standby memory 14 secured as an erased state (writable state) at all times. The data of the standby memory 14 are successively eliminated by a CPU 11 by utilizing free time and the erased state (writable state) is attained. Thus, at the time of storing new data inside the flash memory, it is not required to erase the data inside the flash memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory operation management method suitable for rewriting data in a rewritable semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, when operating an apparatus by rewriting data in a flash memory, new data is written after erasing data stored in the flash memory.

[0003]

However, in the prior art, there is a problem that the processing time becomes long because it is necessary to write new data after erasing data stored in the flash memory.

The present invention has been made in view of the above circumstances, and has as its object to provide a memory operation management method capable of shortening the time required for rewriting data in a flash memory.

[0005]

In order to solve the above-mentioned problem, according to the first aspect of the present invention, at the time of data writing, the erasing operation and the writing operation in a memory which requires the erasing operation of existing data are managed. In the memory operation management method, a primary memory in which currently used data is stored, a secondary memory in which previously used data is stored, and a standby memory which is always kept in an erased state are provided, and new data is stored in the memory. Storing in a standby memory, and after storing new data, changing the primary memory to the secondary memory;
The method comprises the steps of: changing the secondary memory to the standby memory; changing the standby memory to the primary memory; and erasing the standby memory during a free time after the memory management change.

Further, according to the invention described in claim 2, according to claim 1,
In the memory operation management method described above, the primary memory, the secondary memory, and the standby memory are physically independent memories.

[0007] According to the third aspect of the present invention, the first aspect of the present invention.
In the memory operation management method described above, the primary memory, the secondary memory, and the standby memory are one memory virtually divided into three blocks.

According to the present invention, a primary memory for storing currently used data, a secondary memory for storing previously used data, and a standby memory which is always kept in an erased state are provided. Then, when storing new data, it is always stored in the standby memory. Since the standby memory is sequentially erased during the idle time, always write new data.
It is in the erased state (writable state). Therefore, when new data is stored in the flash memory, it is not necessary to erase the data in the flash memory, so that the writing process can be completed in a short time.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. A. Configuration of Embodiment FIG. 1 is a block diagram showing an overall configuration according to an embodiment of the present invention. In the figure, the present embodiment includes flash memories M1, M2, M3 and a CPU 11. The flash memories M1, M2, and M3 exist independently of each other, and the primary memory 12 and the secondary memory 1 are stored in accordance with the old and new data stored in the memories.
3 and the standby memory 14.
The primary memory 12 stores currently used data, the secondary memory 13 stores previously used data, and the standby memory 14 is always secured as an erased state (writable state).

As shown in FIG. 2, the CPU 11 periodically executes the periodic processing 21 and executes the non-periodic processing 22 each time an interruption occurs. And the CPU 11
Executes the flash memory erasing process 23 within the period in which the periodic process 21 and the aperiodic process 22 are not performed. The flash memory erasing process 23 is a fixed period process 21
The priority of the process is set lower than that of the aperiodic process 22 so that the process of the CPU 11 is not obstructed. The CPU 11 executes the flash memory erasing process 23
In step 2, the flash memory managed as the standby memory 14 is erased.

B. Next, the overall operation of the present embodiment will be described in detail with reference to FIGS. FIG. 3 shows a transition state of data in the flash memory and a management method thereof, and state 31 is an initial state. In the state 31, the data D1 is stored in the primary memory 12 (M1), the secondary memory 13 (M2) and the standby memory 14 (M1).
In 3), no data exists.

Next, in state 32, data D2, which is new data, is stored. The data D2 is the flash memory M designated as the standby memory 12 in the state 31.
3 is stored. Thereafter, the CPU 11 changes the flash memory M3 storing the data D2 from the standby memory 14 to the primary memory 12, and changes the data D1
Is changed from the primary memory 12 to the secondary memory 13, and
The flash memory M2 is changed from the secondary memory 13 to the standby memory 14.

Next, in state 33, data D3, which is new data, is stored. The data D3 is the flash memory M designated as the standby memory 14 in the state 32.
2 is stored. Thereafter, the CPU 11 changes the flash memory management as performed in the state B32. That is, the CPU 11 changes the flash memory M2 storing the data D3 from the standby memory 14 to the primary memory 12, changes the flash memory M3 storing the data D2 from the primary memory 12 to the secondary memory 13, and further changes , The flash memory M1 storing the data D1 is stored in the secondary memory 1
3 to the standby memory 14.

Next, a state 34 is a state immediately before storing the data D4 as new data. Since the CPU 11 executes the erasing process of the standby memory 14 using the time during which the process is performed, the data D1 stored in the standby memory 14 (M1) in the state 33 has already been erased. . Therefore, when storing the data D4 in the standby memory 14, since the flash memory (M1) has already been erased, only the write processing needs to be executed. Therefore, in the present invention, the processing time can be halved.

If the standby memory 14 is not erased in the state 34 as in the prior art, it is necessary to perform an erasing process on the flash memory M1 before writing the data D4 and then perform a writing process. Becomes longer. Generally, flash memory is erased by writing certain data.
The writing process occurs twice.

Next, state 35 is data D which is new data.
4 is stored. The CPU 11 performs the same flash memory management change as in the states 32 and 33.
That is, the CPU 11 changes the flash memory M1 storing the data D4 from the standby memory 14 to the primary memory 12, changes the flash memory M2 storing the data D3 from the primary memory 12 to the secondary memory 13, and furthermore, , The flash memory M3 storing the data D2 is changed from the secondary memory 13 to the standby memory 14.

When the writing of new data occurs after the state 35, the erasing process of the standby memory 14 has been completed, and the writing of the new data and the flash memory management state are performed in the same procedure as the states 34 and 35. To change.

FIG. 4 is a flowchart for explaining the operation of the CPU 11 when a write process of new data occurs. When Write Processing Occurs (Step S
1) The CPU 11 checks the erased state of the flash memory designated as the standby memory 14 (step S2). If the data has been erased, the writing process is performed as it is (step S5), the flash memory management is changed (step S6), and the process ends.

On the other hand, if the standby memory 14 has not been erased, the erased state is checked (step S3), and an erasing process for the unerased portion is executed (step S4). The erasure state of the flash memory can be checked by the CPU 11 storing the erasure state in a RAM or the like (not shown) used as a work area. Then, a write process and a memory management change process are performed (steps S5 and S5).
6).

In the embodiment described above, three physically independent flash memories M1, M2, M3 are prepared,
Although the data rewriting time is shortened, the present invention is not limited to this, and one flash memory may be physically divided into three blocks. Here, FIG. 5 is a conceptual diagram showing one physically blocked flash memory. As shown, one flash memory is virtually divided into three blocks B1, B2, and B3, each of which is a primary memory 51, a secondary memory 52, and a standby memory 53. A similar effect can be achieved by adopting the management method.

[0021]

As described above, according to the present invention,
Since the configuration is such that a standby memory that is always kept in an empty state (writable state) is ensured, there is an advantage that when rewriting data in the flash memory, the rewriting time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of a CPU.

FIG. 3 is a conceptual diagram showing a transition state of data in a flash memory and a management method thereof.

FIG. 4 illustrates a case where a write process of new data occurs;
5 is a flowchart for explaining the operation of the PU 11.

FIG. 5 is a conceptual diagram showing one physically blocked flash memory.

[Explanation of symbols]

 11 CPU 12 Primary memory 13 Secondary memory 14 Standby memory M1 to M3 Flash memory

Claims (3)

[Claims] In a memory operation management method for managing an erasing operation and a writing operation in a memory which requires an erasing operation of existing data at the time of data writing, a primary memory in which data currently in use is stored, The secondary memory where the previously stored data is stored,
Providing a standby memory that is always secured as an erased state, and storing new data in the standby memory; after storing the new data, changing the primary memory to the secondary memory; and setting the secondary memory to the standby memory A memory operation management method, comprising: changing to a memory, changing the standby memory to the primary memory; and, after changing the memory management, erasing the standby memory during idle time. 2. The memory operation management method according to claim 1, wherein the primary memory, the secondary memory, and the standby memory are physically independent memories. 3. The memory operation management method according to claim 1, wherein the primary memory, the secondary memory, and the standby memory are one memory virtually divided into three blocks.