JP2000032334A - Image processing apparatus and information recording medium - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the load on a CPU or the like when performing overwrite processing. In addition, efficient mask processing is required. Furthermore, the filling process must be performed without complicating the circuit configuration and increasing the price. In this image processing device, display data is generated by superimposing a plurality of images by a display processing unit that performs an image display process. Then, an overwrite detection unit 71 for detecting whether or not overwriting is necessary for each predetermined block is provided. When overwriting is unnecessary, processing of the next block is performed without performing overwriting processing, or a mask area is set. The mask area is formed by repeatedly arranging a plurality of predetermined mask patterns like tiles. Further, in addition to the pasting mode, a painting mode in which a specific area is painted with a predetermined single color in the color register 78 is performed by the same circuit as the circuit that performs the pasting mode processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an information recording medium suitable for use in an animation called sprite or cast in accordance with a scenario.

[0002]

2. Description of the Related Art Conventionally, as a method of displaying an animation, there are a frame-based animation and a sprite-based animation. Frame-based animation is a method of displaying pictures one by one like a so-called picture-story show. When creating each picture takes time and effort, the frames are displayed in order. And the load during playback is light.

[0003] On the other hand, in sprite-based animation, one picture (frame) is divided into a plurality of sprites (casts), for example, a moving character such as a hero character, a cloud, and a car, and each sprite is divided according to a predetermined scenario. To operate. This sprite-based animation has the advantage of simplifying the creation of each frame and reducing the overall memory size because multiple frame images share a sprite, and has recently been adopted for many animations. . But,
In the sprite-based animation, it is necessary to move each sprite according to a scenario at the time of reproduction, and a heavy load is imposed on a central processing unit (hereinafter referred to as a CPU) that executes a drawing process and a sprite combination process. I have.

[0004] In a conventional sprite-based animation, a so-called mask process in which a part of a drawn image is masked so as not to be displayed is known. Further, when performing an overwriting process for attaching a sprite to a sketch, there is also known a device that performs a transparent color process for making a part of the sprite transparent and displaying the sketch as it is. Also known is a blending process for blending the colors of both the sketch and the sprite at a predetermined ratio. Further, there is also known a filling process for filling a predetermined area with an arbitrary color at the time of initializing a screen or the like.

[0005] These mask processing, transparent color processing, blending processing and filling processing are often performed together with other processing such as enlargement / reduction processing. Further, each of these processes imposes a heavy load on the CPU, and the processing speed tends to be slow. The overwriting process is the basis of such a process, and this process requires more time.

On the other hand, as overwriting and transparent color related technologies,
As disclosed in Japanese Patent Laid-Open No. 190465/1992, there is known a technique for simplifying a drawing program and increasing a drawing speed by devising a calculation or the like when overlapping a mask pattern with transparency defined. Further, as an image processing apparatus that performs high-speed processing without imposing a load on CPU power, a technique disclosed in Japanese Patent Application Laid-Open No. 8-63609 is known. In this technique, a figure formed by painting in a predetermined pattern is overwritten on a predetermined pixel position of a storage device in which a sketch is stored.

[0007]

A conventional image processing apparatus for playing back sprite-based animations can cope with the load of image processing by increasing the CPU power and the mounted memory. 8-6360
This is supported by an overwriting method as in the technology of Japanese Patent Application Laid-Open No. 9-90. However, when coping with an increase in CPU power, the animation becomes extremely complicated, for example, when a three-dimensional image is formed, or when various complicated processes are performed, a very expensive CPU or a high-capacity memory is required, and the device becomes extremely difficult. It will be expensive. Also, JP-A-8-63609
It is difficult to cope with various complicated processes at high speed only by using the technology disclosed in Japanese Patent Application Laid-Open Publication No. H11-163,036.

On the other hand, recently, display devices which are portable and are handled by so-called amateurs, such as products called network displays, have begun to be adopted in convenience stores and the like. This kind of portable device which is easy to operate and is used by many people is required to keep its price down. On the other hand, although the price is kept low, the display speed is required to be equal to or higher than usual.

In the conventional sprite-based animation overwriting process, even when only a part of a sprite or a frame requires overwriting, the entire image is overwritten and the necessary part is transferred to the VRAM. . For this reason, in the case where the entire image is 1,000 × 1,000 dots, even when the portion required for the overwriting process is 10 × 10 dots, the image portion of 1,000 × 1,000 dots is overwritten. . For this reason, the overwriting process that places a load on the CPU becomes even heavier.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made in consideration of a CP in performing an overwriting process.
It is an object of the present invention to provide an image processing apparatus and a computer-readable information recording medium capable of reducing the load on U and the like. Another object of the present invention is to provide an image processing apparatus and an information recording medium that can efficiently perform a mask process. Still another object of the present invention is to provide an image processing apparatus and a computer-readable information recording medium that can prevent the circuit configuration from becoming complicated and expensive when performing the filling process.

[0011]

In order to achieve the above object, in the image processing apparatus according to the first aspect of the present invention, a display processing means for performing an image display process is used to superimpose a plurality of images to generate display data. The processing device is provided with an overwriting necessity determination unit for detecting whether or not overwriting is necessary for each predetermined block, and when overwriting is unnecessary, processing of the next block is performed without performing overwriting processing.

As described above, since the entire block is not overwritten and only the predetermined block which needs overwriting is processed, the load on the CPU and the like is reduced, and high-speed drawing can be performed. Note that the same idea can be applied to the blending process which is a modification of the above description.

Further, according to the invention described in claim 2, according to claim 1,
In the image processing apparatus described above, the overwriting necessity determining unit includes an overwriting detecting unit that detects the necessity of overwriting, an overwriting control buffer that stores a predetermined amount of the detected signal, and a processing pixel number that detects the number of processing pixels. It has a detection unit and a write mask detection unit that supplies a byte mask signal to an overwriting unnecessary portion.

As described above, a signal to be overwritten is detected,
Since the byte mask signal is given to the overwriting unnecessary part,
When performing the overwriting or blending process, the unnecessary portion is reliably detected, so that the overwriting or blending process is not performed.

According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, the overwriting control buffer has a capacity capable of storing 16 pixels, and transfers the 16-pixel unit to the next processing unit. Like that.

As described above, since the overwrite control buffer is provided for 16 pixels, the memory capacity does not increase, and the memory can be accessed efficiently. If the processing unit of the host or the local memory is 32 bits (= 1 word), in the case of 16 bits per pixel, it is equivalent to 8 words, and 8-word transfer is realized.

In addition, in the invention according to claim 4, in the image processing apparatus according to claim 1, 2, or 3, the overwriting necessity judging section judges the necessity of overwriting with eight pixels as one block. I have to.

Since the necessity of overwriting is determined in units of eight pixels, skip processing that does not perform overwriting or blending processing is performed efficiently. If this value is set too large, skip processing is hardly performed, and the efficiency is the same as that of the related art. on the other hand,
If the value is set to a small value, the number of times of capturing the background image data increases, and the processing speed decreases.

According to a fifth aspect of the present invention, in the image processing apparatus of the first, second, third or fourth aspect, if even one of the pixels in a predetermined block needs to be overwritten, the entire block is overwritten. When the processing is performed and all pixels in a predetermined block do not need to be overwritten, the overwriting processing is not performed.

As described above, when it is determined whether or not overwriting is necessary, even if at least one of the pixels in the predetermined block needs to be overwritten, the overwriting process is performed, so that the portion requiring overwriting is reliably overwritten.

Further, according to the present invention, in an image processing apparatus for processing a predetermined image by a display processing means for performing image display processing and generating display data, an image to be displayed on a display unit is masked. A mask setting means for setting a mask region for dividing the mask is provided, and the mask region is formed by repeatedly laying a plurality of predetermined mask patterns like tiles.

As described above, since the mask area for masking the image is set by using the small unit mask pattern, the mask setting can be performed efficiently. Moreover, even if a large number of mask patterns are prepared, the memory capacity does not increase. For this reason, many mask patterns can be prepared, and the selection range of image display can be expanded.

According to a seventh aspect of the present invention, there is provided an image processing apparatus for generating display data by superimposing a plurality of images by a display processing means for performing an image display process. In addition to the mode, a painting mode for painting a specific area with a predetermined single color is performed by the same circuit as the circuit that performs the sticking mode processing.

The blending process and the overwriting process are performed in a pasting mode in which an image forming sprite is pasted on a predetermined area. On the other hand, at the time of initializing the screen, drawing a straight line, and the like, a filling mode for filling a predetermined area is employed. Since these two modes can be executed by the same circuit, the cost of the circuit can be reduced and the device can be downsized.

Further, according to the invention of claim 8, in the image processing apparatus of claim 7, in the sticking mode,
At least an overwriting process, a blending process, and a transparent color process are performed. As described above, at least the most basic processing is performed at the time of image processing, so that the appearance of the image is sufficient.

In addition, in the ninth aspect of the present invention, in the image processing apparatus of the seventh or eighth aspect, the specific area is a rectangular area. As described above, since the area to be painted is a rectangular area, the painting operation is performed efficiently.

Further, in the invention according to claim 10, in the image processing apparatus according to claim 7, 8, or 9, each image is a natural image. Since the image to be handled is a natural image, both the pasting mode and the filling mode are beautiful images. Further, since the image to be handled is a natural image having a large size, the effect of executing both modes by using the same circuit becomes more remarkable.

In the information recording medium according to the eleventh aspect, an overwrite judging step for detecting whether or not overwriting is necessary for each predetermined block; A program for executing a step of performing processing and a step of processing an image for each block by a display processing unit and generating display data is recorded.

When the computer reads and executes the program on the information recording medium, all parts are not overwritten, and the processing is performed only on predetermined blocks that require overwriting. Therefore, the load on the CPU and the like is reduced, and high-speed drawing can be performed.

Further, in the information recording medium according to the present invention, the step of setting a mask area for masking an image to be displayed on the display unit and the step of repeating the mask area by repeating a predetermined mask pattern like a tile. A program is recorded for executing the steps of laying out and forming, and processing the image including the mask area by the display processing means and generating display data.

When the program on the information recording medium is read and executed by a computer, a mask area for an image is set using a small unit mask pattern. As a result, mask setting can be performed efficiently. Moreover,
Even if a large number of mask patterns are prepared, the program capacity does not increase. For this reason, many mask patterns can be prepared, and the selection range of image display can be expanded.

In addition, in the information recording medium according to the thirteenth aspect, a step of alternatively selecting a mode in which an image forming sprite is pasted on a predetermined area and a mode in which a specific area is painted with a predetermined single color; Processing the image in the mode selected by the display processing means and generating display data.

When the computer reads and executes the program on the information recording medium, the blending process, the overwriting process, and the like are performed in a pasting mode in which an image forming sprite is pasted to a predetermined area. On the other hand, at the time of initializing the screen or drawing processing of a straight line or the like, a filling mode for filling a predetermined area is employed. Since these two modes can be performed by the same program, the cost of the circuit for operating the program can be reduced and the size of the device can be reduced.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

The image processing apparatus according to the present embodiment is incorporated in a network display 1 connected to the Internet 2 serving as a network via a LAN 3 serving as a local area network. The network display 1 includes a LAN 3, a personal computer (hereinafter referred to as a personal computer) 4 serving as a host for connection to the outside, and an ISD which is a digital public line network.
N5, connected to the Internet 2 via a provider host computer (hereinafter referred to as WWW server) 6.

The WWW server 6 has a URL (Uniform
Resource Locator), but usually http
(Http) is displayed using (Hyper-Text Transfer Protocol). For this reason, it also functions as an HTTP server. The network display 1 also serves as a television monitor that can receive television broadcasts from the television station 8.

Other WWW servers 6a and 6b are connected to the Internet 2. Also, the WWW server 6 has:
A server computer 7 serving as a server, a personal computer 4a, and the like are connected via another LAN 3a and the like, and a display 7a is connected to the server computer 7. Note that L
AN3 has other network displays 1a, 1b.
And a personal computer 4b are connected.

Here, as the device into which the image processing device is incorporated, in addition to the network displays 1, 1a, 1b also serving as a part of the display means, the personal computers 4, 4a, 4b
Alternatively, the server computer 7 and the display 7a may be applied. Also, the connection between the ISDN 5 and the personal computer 4,
For connection between the SDN 5 and the LAN 3a, a DSU (Digital Service Unit), a terminal adapter, a modem,
A means for connecting to a network such as an IP router is used.

Network display 1, 1a, 1b
(Hereafter, network display 1
2), as shown in FIG. 2, a display unit 11 made of a liquid crystal at the center, an operation unit 12 arranged around the display unit 11, a speaker unit 13 for outputting sound, a specific web page. It is mainly composed of a magnetic card reader unit 14 for reading a magnetic card that can be accessed to read the address and reading other magnetic cards, and a connection unit 15 connected to a power supply line or the personal computer 4 as a host. .

The left and right operation units 12 of the display unit 11
0, there are ten types of menu buttons 12, and each of these buttons 12a
The corresponding operation menu is displayed on the display unit 11 close to. For example, various animations stored in the personal computer 4 are selected by their numbers. That is, when the first menu button 12a is pressed, 1
Make the number animation play. Various operation buttons 12b for accessing a homepage on the Internet are arranged below the display unit 11. An instruction operation unit 12c for moving the operation arrow on the screen up, down, left and right near the magnetic card reader unit 14.
Is provided.

The circuit configuration of such a network display 1 is as follows. That is, as shown in FIG.
(Liquid crystal) display unit 11 and C serving as arithmetic processing means
PU (= central processing unit) 21, dedicated graphics LSI 22 as display processing means, ROM and RAM for storing sprite data, scenario data, and the like
And external information source 2 such as personal computer 4
4 to the CPU 21 or the CPU 21
Data transmission / reception circuit 25 for transmitting instructions from PC to personal computer 4
And the VRA connected to the dedicated graphics LSI 22
M (video ram) 26, external amplifier and speaker unit 1
3 mainly includes a sound circuit 27 for supplying a sound to the display unit 3, a display control unit 28 for driving and controlling the display unit 11, and a peripheral device control unit 29.

The CPU 21, the dedicated graphics LSI 22, the memory 23, and the data transmitting / receiving circuit 25
And the peripheral device control unit 29 are connected by a high-speed host bus 30. Also, in the sound circuit 27,
A microphone input terminal 31 is connected, and external sound can be input. The display control unit 28 includes a first drive control unit 28a for driving the MIM-type liquid crystal, a second drive control unit 28b for displaying the analog-processed RGB values on the TFT-type liquid crystal, and digitally processed data. RGB value to TFT
Drive control unit 28c for displaying with a liquid crystal of the
A fourth drive control unit 28d for driving the RT,
It can correspond to a plurality of display objects. In this embodiment, the third drive control unit 28c is used.

The peripheral device control unit 29 includes the operation unit 12,
A magnetic card reader unit 14 is connected to receive data input therefrom. Further, the peripheral device control unit 29 includes an LED display unit 16 provided in the network display 1, for example, a power supply O.
N, OFF display (POWER display), display of ready state (READY display), display of busy processing (BUSY
Display) is connected, and each display is possible. Also,
A flash memory 17 composed of an EEPROM or the like can be connected. An image / sound decoding unit 18 can be appropriately incorporated in the network display 1 as necessary, and can reproduce data in a retrofit memory 19 containing a predetermined background image or animation.

The external information source 24 is located outside the network display 1 and controls the display contents of the network display 1 on a large scale.
In the memory 23, the CPU 21 fetches specific data from a web browser or a display program, receives a program for controlling display, and receives a command from the external information source 24, and switches a display flow or issues an instruction. And a program for performing a process of displaying the specified specific image at the specified specific position.

Here, the dedicated graphics LSI 22
Is controlled by the CPU 21 to control the sequence between the screens. On the other hand, the display of a series of images and sprites in each screen is performed by looking at the scenarios and data in the memory 23 and based on the scenarios and data. A series of movements of the sprite and the like are controlled. Further, the VRAM 26 can take in two or four screens. The reason why two screens or four screens are used is that one screen or two screens can be used for display and the other screen or two screens can be used for writing. This two-screen or four-screen method eliminates flicker during writing and improves image quality. The sound circuit 27 is a 16-bit, 44.1KH
z, one channel, but other values can be used as appropriate.

The sprite data and the scenario data are installed on the memory 23 of the network display 1 or a hard disk (not shown), or the retrofit memory 19 containing the data is generated and attached to the network display 1. . At the time of installation, distribution is performed by communication using the Internet 2 or another network. Note that the network display 1 has a CD-R
If an information storage medium reading unit such as an OM reading mechanism is provided, data may be installed using an information storage medium such as a CD-ROM.

The structure of the dedicated graphics LSI 22 is as follows.
It is as shown in FIG. That is, the host interface 32 connected to the host bus 30 and the VR
An internal host bus 34 and an internal VRAM bus 35 between the VRAM interface 33 connected to the AM 26;
Is provided. Then, the decoding unit 36 and the image processing unit 3
7 are connected to both buses 34 and 35, respectively. The internal host bus 34 has an audio interface 38
, And a liquid crystal display interface 39 is connected to the internal VRAM bus 35.

The decoding unit 36 includes a natural image decoding function unit,
An index image decoding function unit and a palette RAM for index images are provided. The image processing unit 3
Reference numeral 7 is for performing overwrite processing and the like described later.
The audio interface 38 has various functions such as audio control, audio mixing, and sampling rate change. For mixing, up to three channels of two channels via the host bus 30 and input from an external microphone can be mixed.

The liquid crystal display interface 39 has a display control, an overwrite control when the post-installation memory 19 is used, and a function of hardware-displaying a cursor on the display (hereinafter referred to as a hardware cursor). ing.
The hardware cursor solves the problem of the software cursor by storing the cursor data in the memory 23 in a divided manner and combining the cursor data with other data. With a software cursor, when displaying a cursor display in a predetermined portion, it is necessary to store the original image at the position of the cursor before attaching the cursor, and to rewrite the original image when the cursor moves. This process imposes a load on the CPU 21. The hardware cursor solves such a problem. The liquid crystal display interface 39 has substantially the same function as that of the display control unit 28. When a display body compatible with the standard function of the liquid crystal display interface 39 is mounted, the display control unit 28 almost does not operate. Free pass.

As shown in FIG. 5, data for controlling each frame 20 in the time axis direction is written in the memory 23. The duration of each frame 20 normally switches at a speed of appearing 25 frames per second, but in this embodiment, it can be changed within a range of 1/10 to 80 seconds. The memory 23 further stores one frame 2
A program for controlling a display position of a sprite (details will be described later) in 0 is written.

The image processing section 37 of the dedicated graphics LSI 22 basically performs an overwriting process.
For example, assuming that the sprite is the characters "A", "B", and "C", first, a program for displaying "A" is executed. This execution is performed by setting various parameters for displaying “A” and then downloading the compressed image data obtained by expanding “A” to the VRAM 26. Similarly, the image data of the characters “B” and “C” is downloaded to the VRAM 26 and overwritten (overwritten) as shown in FIG.

As shown in FIG. 7, the image processing unit 37 includes a memory control unit 41 for adjusting a request from each buffer block described later, and an original drawing image buffer block 42.
, A transparent data buffer block 43, a mask data buffer block 44, a background image buffer block 45, a final drawing image buffer block 46, a data processing unit 47, and a memory access optimization processing unit 48. You. Here, the four buffer blocks 42, 43, 44, and 45 take in data (= read) from the CPU 21, the memory 23, and the like, and the block 46 reads out data from the VRAM 26 (= write).

The memory control unit 41 adjusts requests from the buffer blocks 42, 43, 44, 45, and 46 based on a predetermined priority and can connect to the host-side memory 23 and the VRAM 26 serving as a local memory. It is to be. Access at this time can be performed in parallel. For example, the final drawing image buffer block 46 can access the VRAM 26 at the same time when the memory 23 is accessed from the original drawing image buffer block 42.

The original drawing image buffer block 42
A storage unit for temporarily storing original drawing image data (Source Image) to be described later. The storage unit accesses the memory control unit 41 and exports the fetched data to the data processing unit 47. Transparent color data buffer block 43
Is a storage unit for temporarily storing transparent color data (Trans.Data) described later, and the mask data buffer block 44 is a storage unit for temporarily storing mask data (Mask Data) described later.
It accesses the memory control section 41 and outputs the fetched data to the data processing section 47.

The background image buffer block 45 is a storage unit for temporarily storing the background data (BGData), and accesses the memory control unit 41 and at the same time, extracts the data taken into the data processing unit 47. Further, it receives a signal indicating whether or not overwriting is necessary from the memory access optimization processing section 48. The final drawing image buffer block 46 is a storage unit for temporarily storing a later-described final drawing image (Draw Image) to be received from the data processing unit 47, and accesses the memory control unit 41 and optimizes memory access. The data regarding the necessity of overwriting is received from the processing unit 48.

Here, the memory control unit 41 is the CPU 21,
Signals exchanged between the memory 23 and the VRAM 26 are composed of a total of five signals. That is, a chip select signal (CS) which is a memory control unit signal and an output enable signal (O
E), a write signal (WR), an address signal (AD),
And a data bus signal (DB). In FIG. 7 and the like, “H” added to the head of each signal means a signal on the host side, and “V” means a signal on the VRAM 26 side.

Each of the buffer blocks 42, 43, 4
From 4, 45 and 46, an address signal (ADRS) indicating the selected address, a burst signal indicating the continuous data length
(BURST), a read request signal (RDReg) indicating a read (= read) request, and a flag signal (FLAG) are output to the memory control unit 41. "S" added at the end of each signal
“T”, “M”, “B”, and “D” indicate types of data to be handled, respectively, “S” indicates an original drawing image (Source Image),
"T" is transparent data (trans.Data), "M" is mask data (Mask Data), "B" is background image (B
ackgroud Data), “D” is the final drawing image (Draw Ima
ge). In the following, signals to be described will be expressed in the same way. The final drawing image buffer block 46 also outputs a byte mask signal (MASKD).

On the other hand, from the memory control unit 41, a read request acknowledge signal (R
DRACK), a read data acknowledge signal (RDDACK), which is a read data transmission notification, and the memory 23 or VRAM 2
Data (DATAOUT) from 6 etc. are in each buffer block 4
2, 43, 44, and 45. The memory control unit 41 sends a write request acknowledge signal (WRRACK) as a write (request) request reception notice and a write data acknowledge signal (WRDACK) as a write data reception notice to the final drawing image buffer block 46.
Is output, and the data written to the VRAM 26 is output in the reverse direction. The write data is indicated as “DATAD”.

A detection signal (Det) indicating the necessity of overwriting is output from the data processing unit 47 to the memory access optimization processing unit 48. From the memory access optimization processing unit 48 to the background image buffer block 45 and the final drawing image buffer block 46, a signal for setting an operation state (Active), a signal for skipping without displaying an image (Skip), A burst signal (BURST) indicating the length and a signal (ProcLen) of the same type as the burst signal are output. Here, "BG" attached to the head of each signal
“B” indicates a signal related to a background image, and “DI” and “D” indicate signals related to a final drawing image (draw image). In addition,
A mask signal (MASK) for forming a byte mask signal described later is sent to the final drawing image buffer block 46.
Is also output.

As shown in FIG. 8, the memory control unit 41
It comprises an access arbitration unit 51, a memory interface unit 52 on the host side, a memory interface unit 53 on the VRAM 26 side, and a multiplexer circuit 54. The memory interface unit 52 on the host side includes a priority control unit 55 and a memory timing generation unit 56, and the memory interface unit 5 on the VRAM 26 side.
3 also has a priority control unit 57 and a memory timing generation unit 58
It is composed of The memory interface unit 52 on the host side and the memory interface unit 53 on the VRAM 26 have exactly the same configuration. For this reason,
The memory control unit 41 includes the buffer blocks 42, 43,
44, 45, and 46 requests can be processed in parallel.

The access arbitration unit 51 determines whether to go to the host bus 30 connected to the CPU 21 or the memory 23,
Sort if you are going to the bus that leads to 6. The access arbitration unit 51 has five request signals RDReqS, RD
ReqT, RDReqM, RDReqD and five flag signals FLAGS, FLAGT, FLAGM, FLAG
B and FLAGD are input. Each of these flag signals is a control signal for determining whether to go to the host or to the VRAM 23, and is classified into "0" and "1". For example, “0” indicates the host side, and “1” indicates the VRAN 26 side. Upon seeing this state, the access arbitration unit 51 outputs a request signal to one of the memory interface unit 52 on the host side and the memory interface unit 53 on the VRAM 26 side.

Each request signal is input to one of the priority control units 55 and 57, respectively. The priority control sections 55 and 57 receive a plurality of request signals independently. Then, the priority control units 55 and 57
Request signals from the buffer blocks 42, 43, 44, 45, and 46 are received based on a predetermined priority. In this embodiment, the request signal from the final drawing image buffer block 46 has the first priority, the background image buffer block 45 has the second priority, the original drawing image buffer block 42 has the third priority, and the mask data buffer block has the third priority. 44 is the fourth priority, and the transparent data buffer block 43 is the lowest priority.

The final drawing image buffer 46 is given the first priority because a new image cannot be captured when the buffer block 46 is full. Second
Regarding the order and the third order, which one should be prioritized depends on the type of the image, and the difference is not large, so the order may be changed. However, when rendering, a background image is required, so this embodiment is more preferable. Mask data and transparent color data are
Since each bit is 1 bit, a problem does not easily occur in terms of capacity, and it is easy to secure a sufficient capacity for the data. There is no problem even if the order of the mask data and the transparent color data is reversed. If the capacity for both data is extremely small, it is necessary to raise the priority.

Note that the priority may be dynamically changed instead of being fixed. For example, the current capacity of each buffer block 42, 43, 44, 45, 46 is monitored, and each buffer block 42, 43, 44, 45, 4 is monitored.
The time until 6 becomes full or empty is calculated. In this calculation, the number of cycles to be full or empty is calculated based on the amount of data handled in one cycle, and an approximate time can be obtained from the numerical value. By changing the priority according to this time, dynamic response is possible.

Each of the priority control sections 55 and 57 outputs a priority selection signal (PriSel) for determining a priority. Based on the signal, the memory timing generators 56 and 58 receive a predetermined address signal or the like among the input signals, and at a predetermined timing, the CPU 21, the memory 23, and the VR.
Access to AM26. The memory timing generators 56 and 58 send out various control signals in order to ensure consistency with the higher-order arbitration unit. These signals are of the same type as when the control target is an SRAM.

Data input from the memory 23 or the VRAM 26 to the memory control unit 41 is output from the memory timing generation units 56 and 58 to the multiplexer circuit 54. Then, a bus selection signal from the access arbitration unit 51
(BusSel) and output to the buffer block that issued the read request. The access arbitration unit 51 outputs a read request reception notification signal (RDRACK) in response to the read request signal (RDReq), and outputs a read data transmission notification signal (RDDACK) to each buffer block 42 prior to data output. , 43, 44, 45.

Note that the byte mask signal (MASKD) is used only for writing. This byte mask signal is
A mask control signal used when writing to the memory 23 or the VRAM 26. The mask data (MASK Data)
Is different from The function of this byte mask signal will be described based on the signal configuration in this embodiment. As shown in FIG. 9, one word (W) is 4 bytes
In the structure (B), there is a case where it is desired to overwrite a 16-bit to 31-bit portion by using the original data as it is for the 0-15 bit portion in one word. In such a case, the mask control signal “110” as shown in FIG.
The object can be achieved by setting it to 0 ". As described above, in this embodiment, writing control can be performed byte by byte by using the mask control signal.

As described above, only a predetermined area can be overwritten by using the 1-bit byte mask signal (MASKD). When this byte mask signal is not used, and when it is desired to keep the original data, it is necessary to temporarily store all the original data in the memory. Then, after the processing, a process of returning the stored data is required.

In this embodiment, the data to be written is only the data (= DATAD) from the final drawing image buffer block 46, but a plurality of data can be handled.

The inside of the original drawing image buffer block 42 is as shown in FIG. The other buffer blocks 43, 44, and 45 have the same configuration. The inside of the final drawing image buffer block 46 is
As shown in FIG. In FIG. 11, signals from the memory access optimization processing unit 48 are omitted.

Each of the buffer blocks 42 to be read,
43, 44, 45 are respectively a buffer control unit 61,
Two buffers 62 and 63 and a multiplexer circuit 64
It is composed of The final drawing image buffer block 46 for writing includes a buffer control unit 65 and 2
It is composed of two buffers 66 and 67 and a multiplexer circuit 68. Here, the buffers 62 and 63 and the multiplexer circuit 64 constitute a double buffer circuit 69, and the buffers 66 and 67 and the multiplexer circuit 68 constitute a double buffer circuit 70.

As described above, each of the buffer blocks 42, 4
Reference numerals 3, 44, 45, and 46 are for reading and writing, and have different buffer capacities, but are double buffers of the same system. In the double buffer system, control is simpler than in a conventional ring buffer in which data is sequentially written into a vacant space one after another, and data written first is used in order. In the double buffer system, one can be used for writing and the other for processing (data movement). When one of the buffers becomes full by writing, the process proceeds to processing. Specifically, the status of the first buffer and the second
Control unit (not shown) that controls the status of each buffer
When it becomes empty, writing to the buffer starts. When full, the data is flushed and emptied.

When the ejection takes time and the other buffer becomes full, writing into the buffer becomes impossible, and the user must wait until the ejection operation is completed. On the other hand, when the ejection is completed, if the other is not yet full, the ejection operation becomes impossible, and the user has to wait until it is full. Dedicated graphics LSI
To take full advantage of the computational power of 22, it is preferred that one buffer be full while the other is flushing. For this purpose, it is necessary to appropriately set the capacity, the number of processing bits, and the like. As a result, the dedicated graphics LSI 22 performs arithmetic processing and the like one after another and reduces the waiting time of the buffer. If the necessary data has been fetched before the data becomes full, extra (= wasteful) data is read or the data amount is counted, and when a predetermined amount of data is fetched, the data becomes full. Even if it is not, a full signal can be output to start the stripping operation. In this embodiment, the latter is adopted.

In FIG. 10 and FIG.
“fWrAD” is a signal indicating the addresses of the two buffers 62 and 63. Further, “BufWrEn” is formed in the buffer block 42 and the like based on the read data transmission notification “RDDACK”, and in the buffer block 46, “DI
These are signals that are formed based on "DATAEn" and enable data to be read into the corresponding address. Further, “BufRdAD” in FIG. 10 is a signal for instructing which data of which buffer is to be read and transmitted to the data processing unit 47. Original drawing image data (= Source Ime
ge) is composed of a signal of “SIDATA” as data itself and a signal of “SIDATAEn” for validating the data.

“BufRdAD” in FIG. 11 is a signal for instructing which address of which buffer data is to be read and transmitted to the memory controller 41. Also,
Data sent from the data processing unit 47 (= Draw Ima
ge) is composed of a signal of “DIDATA” as the data itself and a signal of “DIDATAEm” for validating the data.

In this embodiment, one word is 32 bits, and the buffers 62, 63, 66, and 67 each have a capacity of 8 words (8 × 32 bits). As the buffers 62, 63, 66, and 67,
Other numerical values such as 2 words and 16 words may be used.
However, if the size is too large, the time for which other buffer blocks continue to wait increases, which is unfavorable, the memory capacity increases, and the cost becomes severe. On the other hand, if it is too small, the number of overwrites will be too large. Therefore, 4
Preferably ~ 16 words, most preferably 8 words. In this embodiment, since the image to be handled is represented by 2 bytes per pixel, processing for 16 pixels with 8 words is performed.

The data processing unit 47 has a function of detecting a transparent color from the transparent color data and outputting a signal “TDet”, a function of outputting a signal “CDet” indicating clip processing described later, Has a function of outputting a signal "MDet" indicating that mask processing is performed from
An overwrite detection unit 71 that receives these signals and detects whether or not overwrite is necessary is provided. The overwrite detecting section 71 is activated when any of the three signals “TDet”, “CDet”, and “MDet” is turned on.

The data processing section 47 further has a function of performing a blending process described later. In this embodiment, in order to efficiently generate and draw the final image generated by the blending process, a signal “Det” indicating the necessity of overwriting detected by the overwriting detection unit 71 is input and various signals for synthesis are input. Is provided. This memory access optimization processing unit 48 does not necessarily need to be provided. The signal "De
"t" indicates whether or not overwriting is performed on a pixel-by-pixel basis. The overwrite detecting section 71 and the memory access optimizing section 48 constitute an overwriting necessity judging section.

The memory access optimization processing unit 48 includes an overwrite control unit buffer 72, a processing pixel number detection unit 73, a write mask detection unit 74, and an access request control unit 75.

In this embodiment, in the overwrite control buffer 72, the buffer blocks 42 to 46 have eight words (32 words).
Since a buffer having a capacity of (.times.8 bits) is provided and data for 16 pixels can be handled at a time, a signal "Det" for controlling overwriting is also accumulated for 16 pixels. That is, the capacity is the same as that of one buffer in the double buffer. At this time, in this embodiment, since the signal “Det” is represented by one bit per pixel, the signal “Det” becomes a buffer for two bytes. Thereby, 8-word transfer is realized. In the blend mode, the overwriting control buffer 72 determines whether or not to perform a blending process by checking the contents of the data “Det” stored in the inside. That is, if all the pixels in the eight words are prohibited from being overwritten, no overwriting is performed (= skipped). Specifically, 8
The word is divided into two words of four words, and if there is a signal requiring overwriting in four words, the overwriting process, that is, the background data is read, fetched, and the original drawing image is superimposed. When all four words are prohibited from being overwritten, the processing for the next four words is not performed but the processing for the next four words is performed. If the four words are not overwritten, the blending process is skipped in the blend mode, and the process proceeds to the next eight words. When the blending is off, if the four words need to be overwritten, they are immediately overwritten, and the next four words are checked and processed.

As described above, the processing efficiency can be improved by dividing the data into four words and determining whether to overwrite or skip, and by transferring eight words.

The data for eight words is sent from the overwriting control buffer 72 to the number-of-pixels-to-be-processed detection section 73. The processing pixel number detection unit 73 sends a burst signal (BGBURST) indicating whether the number of pixels to be processed is 4 words or 8 words to the background image buffer block 45 and outputs a similar burst signal (DI
BURST) to the final drawing image buffer block 46. These two signals (BGBURST, DIBURST) are sent to the memory 23 and the VRAM 26 via the memory control unit 41. On the other hand, a background procedure length (= DProcLen), which is a signal having the same properties as these signals, is used to control the buffer control units 61 and 65, and is also input to the access request control unit 75 to be described later. Used for generating signals and skip signals.

When skip processing is not performed, that is, when overwriting or blending processing is performed, the write mask detecting section 74 performs a byte mask signal (MASK) for performing transparent color processing, clip processing, or mask processing only on predetermined pixel portions. Used to get. This byte mask signal is output to the final drawing image buffer block 46. As a result, writing to the memory 23 and the VRAM 26 is prohibited.

An active signal “BGActi” for taking in the background image data from the access request control unit 75 to the background image buffer block 45 is provided.
ve "and a skip signal" BGSkip "for skipping without taking in the data. The same active signal “DIActive” and a skip signal “DISkip” are output to the final drawing image buffer block 46.

Next, a read operation of the image processing apparatus 1 having the above-described configuration will be described with reference to FIG. FIG. 13 shows a standardized access procedure when reading (reading) the VRAM 26 or the like. FIG. 13 shows a case where the priority control units 55 and 57 give priority to the exchange with any one of the buffer blocks 42, 43, 44 and 45 and access the VRAM 26. Host side memory 23 or C
The loading from the PU 21 is the same, so the description is omitted.

Here, “CLK” is a clock signal for synchronizing each signal, HIGH is VDD (power supply voltage), and LOW is
VGND (ground voltage). First, the read request “RDREQn” becomes HIGH, and at the same time, the access arbitration unit 51 sends the address signal “ADRSn” and the burst signal “BURSTn” indicating the number of transfer words to each of the buffer blocks 42 and 4.
Receive from 3,44,45. If the timing is acceptable, a read request acceptance signal “RDRACKn” is returned. The symbol “n” is used for each of the buffer blocks 42, 43, 4
4 and 45.
This is the same in the following description.

The read request acceptance notification “RDRACKn”
Although not necessary, this signal is transmitted to the buffer block that has issued the read request, so that the read request “RDREQn” is set to LOW to the buffer block that has issued the read request.
Can be encouraged. As a result, the memory control unit 41 can receive the next read request or the next write request, and can receive a signal request from another buffer block or the same buffer block. That is, the memory interface unit 56,
58, the access arbitration unit 51
Can accept other requests. This enables a so-called parallel processing operation. That is, V
It is possible to fully use the capacity of the RAM 26.

The read request acceptance notification “RDRACKn” is output, and the read request “RDREQn” is transmitted to the priority control unit 57.
Are selected according to the priorities shown above.
Based on the selected signal, the memory timing generation unit 58 outputs memory signal control signals VCS, VOE, and the like to the VRAM 26, and the VRAM 26 enters an operation state.

Via a connection bus to the VRAM 26,
In this example, four addresses are transmitted to the VRAM 26,
Reading (reading) is performed four times from the corresponding address. The four data Data0 to Data3 are V
The information is transmitted to the memory interface unit 53 on the RAM 26 side. Thereafter, the data is fetched into a predetermined buffer block via the memory interface unit 53 as read data “DATAOUT”. At this time, the read data transmission notification “RDDACKn” is transmitted from the access arbitration unit 51 to the buffer block, and the above-described capture is turned on.

The memory control unit 41 knows the state in the memory 23 and the VRAM 26, and adjusts the read request reception notification “RDRACKn” and the read data transmission notification “RDDACKn” in accordance with the processing stages of the memory 23 and the VRAM 26. I try to send. For example, when the data of the requested address is not immediately returned due to the VRAM 26, the read request acceptance notification “RDRACKn” and the read data transmission notification “RDDACKn” are not transmitted, so that each buffer block 42, The next processing of 43, 44, 45 can be made to wait, and the memory 23, the VRAM 26
Also, the cut edges of the buffer blocks 42, 43, 44, and 45 can be easily aligned. The read request acceptance notification “RDRACKn” enables advance acceptance. This enables so-called pipeline processing.

Assuming that there is no signal of the read request acceptance notification “RDRACKn”, the read request “RDREQn” remains HIGH and goes low only when the read data “DATAOUT” enters a predetermined buffer block. Becomes For this reason, signal processing from another buffer block cannot be performed during this time. The priority of the buffer blocks 42, 43, 44, and 45 with respect to the read request is highest in the background buffer block 45 as described above. However, when a write request is issued from the final drawing image buffer block 46 to be described later, the request is given the first priority.

Each of the buffer blocks 42, 43, 44, 4
For each of the requests from Nos. 5 and 46, a fixed order or a dynamic response can be considered as described above. As the dynamic response, a method of calculating which buffer block 42, 43, 44, 45, or 46 a request has been received in addition to grasping the buffer capacity, and lowering the priority of a request having a larger number of times of reception has been adopted. is there. It is also possible to prepare one such as a so-called ticket, such as a token ring, to rotate the ticket, and to accept a request when the ticket is accepted.

Next, the writing operation of the image processing apparatus 1 will be described with reference to FIG. FIG. 14 shows the VRAM2
6 shows a standardized access procedure at the time of writing (writing) to the memory 23. In this embodiment, the write operation is performed only on the final drawing image buffer block 46. However, even when another buffer block is added, the write operation is performed by this access procedure. The hatched portions in FIG. 14 mean indefinite as in FIG. In FIG. 14,
Although the case of writing to the VRAM 26 is shown, the same applies to the case of writing to the memory 23.

The signal [CLK] has the same role as in the read operation. First, the write request “WRREQn” is set to HIG.
H, the request is detected by the access arbitration unit 51.
At the same time, the write address “AD
RSn "and burst signal" BURSTn "indicating the number of words to be transferred
And the data "DATAn" to be written and the byte mask signal "MASKn" indicating a place where writing is not desired are received from the final drawing image buffer block 46.

Note that the byte mask signal is the mask control signal (= MASKD) shown above, and as described above,
When data to be written in one write process is considered in units of 1 byte (= 8 bits), this specifies whether or not to write each byte. If the data to be written is indicated by 1 bit, and the data to be written at a time is 4 bytes (= 32 bits), the byte mask signal is 4 bits. That is, each bit of the byte mask signal specifies whether to write each corresponding byte of the write data. For a byte specified not to be written by the byte mask signal, the value already stored in the VRAM 26 is held as it is. The data written in one write process is not limited to 4 bytes, but may be another bit or another byte. When the function of masking the write data is not used, the byte mask signal and all the circuits associated therewith may be omitted. Further, the signal for writing or not may be represented by 2 bits instead of 1 bit.

The write request acknowledgment "WRRACKn" has the same function as the previous read request acknowledgment "RDRACKn". With this signal, pipeline processing becomes possible, and the function of the VRAM 26 can be used up 100%. When the byte mask signal “MASKn” is unnecessary, this function can be prevented from being used by always defining 4-byte writing. Such selection of use or non-use is the same for other signals.

The write request acceptance notification “WRRACKn” requests that the write request signal “WRREQn” of the final drawing image buffer block 46 be changed from HIGH to LOW,
Thereby, the memory control unit 41 can receive another request signal. On the other hand, memory signal control signals CS, OE, WR, AD, and DB are output from the memory control unit 41 based on the signal at the address “ADRSn” and the like.
Is in the operating state. As a result, the four data Data0
3 and four mask control signals Mask0 to Mask3 as byte mask signals are transmitted to the VRAM 26 and written.

Note that the write data “DATAn” and the byte mask signal “MASKn” are not output simultaneously with the write request “WRREQn”, and the write data “DATAn” and the byte mask are output after the write request acknowledgment “WRRACKn” is output. The signal `` M
ASKn ”may be output. However, outputting at the same time is advantageous in terms of processing speed. That is, it is possible to receive data in advance.

When the memory control unit 41 receives the first write data Data0 and the byte mask signal Mask0 from the final drawing image buffer block 46, a write data reception notification “WRDACKn” is output from the memory control unit 41 to the buffer block 46. Is done. The final drawing image buffer block 46 receives the first write data reception notification “WRDA
When receiving "CKn", it outputs the next write data Data1 and byte mask signal Mask1. In this way, data and byte mask signals are sent one after another.

In the example of FIG. 14, two write data reception notices “WRDACKn” are continuously output, and then two more are output after a short time. Note that VR
Depending on the use of the AM 26 or the timing of the memory timing generation unit 58, four consecutive or intermittent write data reception notifications “WRDACKn” may be transmitted. Write data “DATAn” and byte mask signal “MASKn” sent from the final drawing image buffer block 46
Are sequentially written to the VRAM 26 as described above.

Next, the processing flow of the image processing section 37 of the dedicated graphics LSI 22 will be described.

The processing flow of the image processing section 37 is as shown in FIG. That is, a transparent image extracting process (step S101) is performed on the decoded image (hereinafter referred to as an original drawing image) transmitted from the decoding unit 36.
I do. Next, a transparent color replacement process (step S102) for giving the RGB values of the transparent color to the transparent color portion is performed. After that, an enlargement / reduction process (step S103) is performed, and after a transparent color is detected (step S104), a portion to be overwritten on the original image is detected by the overwrite detection unit 41.

The data for clip processing (step S105) and mask processing (step S106) are input to the overwrite detecting section 71, and after these processings are performed, blend processing (step S107) is performed. The processing such as the enlargement / reduction processing S103, the clip processing S105, and the blending processing S107 is not performed unless the processing is specified. The data subjected to the enlargement / reduction processing is input to the multiplexer 77 and docked with the data of the clip processing S105 and the like, and if necessary, the blend processing S1
07 is performed. When the painting function (details will be described later) is on, the painting process is performed using the data from the color register 78. The data in that case is also subjected to a blending process S107 after that, and sent to the liquid crystal display interface 39 as a final drawing image.

Next, the display function of the network display 1 will be described. Note that the phrase “sprite” used hereinafter refers to a component of an image in one frame 20 of the animation, and each is represented by a rectangle for the reason described later. For example, [A] [B]
Characters such as "C", pictures such as apples and persimmons, and geometric figures such as triangles and squares correspond to sprites. The “sprite screen” refers to a screen that displays such a “sprite”.

In general, each frame 20 which becomes each screen in the animation is composed of a plurality of sprite screens. Each sprite has 16 bits per pixel (R:
G: B = 5 bits: 6 bits: 5 bits) is a natural image in RGB format and is a natural image sprite. Each sprite is rendered in cooperation with the CPU 21, the dedicated graphics LSI 22, the memory 23, and the like.

The animation screen of this embodiment is
When these sprites overlap, the sprite that comes to the foreground is preferentially displayed. However, since the two specific colors are transparent, the color of the screen on the rear side can be displayed using the “transparency”.

The screen serving as the display unit 11 is an area for displaying an animation movie and serves as a display screen. This network display 1 is shown in FIG.
Has a display screen 80 with a display size of 320 × 240 pixels. Also,
A movie screen 81 having a maximum size of 1023 pixels in width and 511 pixels in height from a minimum size of 1 pixel (pixel) × 1 pixel in height (pixel) can be supported. The origin (upper left) of the animation movie screen (movie screen 51)
Is the origin (upper left end) P of the display screen 80. In addition, the display screen 80 of the network display 1 is set to 5
It may be 12 × 240 pixels or 640 × 480 pixels.

Here, if the size of the movie screen 81 (described later in detail) is larger than the display screen 80,
A part of the movie screen 81 will be displayed. Conversely, when the size of the movie screen 81 is smaller than the display screen 80, a blank portion is generated at the right end or lower end of the display screen 80. The margin is displayed with the background color of the display screen 80. The background color of the display screen 80 is specified by an RGB value of 16 bits / pixel.

A space for drawing frames of the animation (see FIG. 16) is called a movie screen space 82. This space 82 is a kind of virtual space and has a virtual RAM.
It can be said that. This space 82 has a width (horizontal) of -1024 pixels to 1023 pixels,
In the height direction (vertical direction), from -512 pixels to 511
Although it has a spread of pixels, it is a partial area in the space 82 that the image is actually drawn. This actually drawn area is called a movie screen 81. The movie screen 81 always has the origin P (0, 0) as a base point. Its size varies from movie to movie. Origin P at maximum
A rectangular area (including a boundary) having (0, 0) and (1023, 511) as diagonals becomes the movie screen 81.

As described above, each animation movie can have a movie screen 81 with a minimum size of 1 pixel wide × 1 pixel high and a maximum size of 1023 pixels wide × 511 pixels high. The sprite drawn in the movie screen space 82 is
Only the part included in the movie screen 81 is actually drawn. The portion outside the movie screen 81 is not drawn. This movie screen 8
A transfer destination image (drawing image) 83 is drawn on a predetermined portion of the image data.

The image drawn on the movie screen 81 is not an original drawing image, but is actually an original drawing image and a transparent mask image 86 which becomes transparent color data. The original drawing image is an image obtained by compressing the transfer rectangular image 85 as shown in FIG. The transparent color data also becomes a transparent mask image, and the transparent rectangular image 86 is compressed and stored in the memory 2.
3 is expanded and formed. Each image 5
5, 56 is the maximum size, width 1023 pixels × height 5
It is 11 pixels and the same size.

As described above, the transparent rectangular image 86 is formed because a specific color in a natural image is assigned as a transparent color. This is because a transparent color cannot be preserved. When the image data and the transparent color data are separated and compressed in this manner, the processing is simplified and the compression efficiency is improved. The transparent rectangular image 86 is a simple bitmap image in which “1” or “0” bits are assigned to a transparent color portion therein, and “0” or “1” bits are assigned to an opaque portion. .

A color defined as a transparent color may occur in a portion of the decoded transfer rectangular image 85 that should not be transparent. For this reason, first of all, as mentioned above,
A transparent color extracting process S101 is performed. Next, the transparent data of the transparent rectangular image 86 is docked. At this time, a transparent color replacement process S102 for assigning a predetermined transparent color to a transparent portion of the docked original drawing image is performed. In this embodiment, the RGB values are (31, 62, 3).
The colors 1) and (31, 63, 31) are transparent.

In the enlargement / reduction processing S103, data of the width and height of the transfer rectangular image 85, which is the image, is input, and the data is enlarged or reduced to a predetermined size. At this time, since the transparent color processing has already been performed, the data of the width and height of the transparent rectangular image 85 is not required. However, you may make it input. The enlarged / reduced data is subjected to transparent color detection processing S104 for overwriting. Before or after this processing, data may be created for clip processing S105 or mask processing S106. It is preferable that the processing is performed in the order of the mask processing and the clip processing.

As shown in FIG. 17, the clip processing S105 is performed on the drawing image 83 with respect to the clip window 91.
, A predetermined portion of the drawing image 83 is cut out. The maximum size of the clip window 91 is 1023 pixels in width and 511 pixels in height. The clip window 91 can be freely arranged in the movie screen space 82.

The clip processing S105 is divided into two types. One is for drawing an image in the clip window 91 as shown in FIG. 18A (the shaded area is a drawing area), and the other is for drawing a clip as shown in FIG. Instead of drawing the image in the window 91, a portion (hatched portion) located outside the clip window 91 in the display screen 80 serving as an effective display area is drawn. In the clip processing S105, an offset value and a size of the clip window 91 are input. The offset value is located at the center of the movie screen space 82 and becomes a base point P of the drawing screen, that is, X
Y indicates a deviation from the position of (0, 0).

As described above, in the clip processing S105,
The clipping process can be performed by designating the clip window 91 of an arbitrary size specified by the register for the clip window 91 as an arbitrary window start position. In addition, by specifying the clip window mode,
The processing method of the clip window 91 can be any of FIG. 18A or FIG. 18B.

As shown in FIG. 19, the mask processing S106 applies a mask 92 to the drawing image 83, and performs a type of blindfolding. The portion where the mask 92 is applied is not displayed. In this embodiment, a tiling method is used for forming the mask 92.
That is, the mask processing S106 is realized by laying the mask pattern 93 of an arbitrary size specified by the width and the height on the tiling rectangular area serving as the mask 92. Note that the width, height, and start position of the mask 92 can be arbitrarily specified.

The enlarged / reduced data is input to the multiplexer circuit 77 together with the position data. At this time, the normal mode or the next filling process is switched according to the BD mode signal for switching the two modes. The BD mode signal is “0” (or “1”) when performing normal pasting work after enlarging / reducing, and becomes “1” (or “0”) during filling processing. When filling, color register 7
The painting process is performed with the color from 8 onward. The function for filling the rectangle is originally intended for this network display 1
The function is a little different, while the function is attached. This is processing for painting a predetermined rectangular area 94 (see FIG. 20) with an arbitrary color designated by the color register 78. This function is applied to screen initialization and rectangular / straight line drawing processing.

This rectangle filling function has a maximum of 102 functions.
The function is to fill a rectangular area 94 having a size of 3 × 511 pixels with a single color. The specification of the filled area 94 can be made at any position in both the horizontal (−1024 to 1023 pixels) and vertical (−512 to 511 pixels) directions. The color of the rectangle drawing is specified by the color register 43, the width and the height are specified by the width and height specifying register (not shown), and the drawing start position is specified by the drawing offset register (not shown). I have.

After the various processes as described above are performed, finally, a blend process S107 is performed.

In the blending process S107, as shown in FIG. 21, when the transfer source image 95 composed of the transfer rectangular image 85 and the transparent rectangular image 86 is drawn by a predetermined drawing method, the color of its own opaque pixel and the background image are drawn. This is a process of mixing a background color (background image) 98 of the drawing page 96 with a specified blend ratio to obtain a transfer image 97. The blend ratio is specified in a range of 0 to 100%, in this embodiment, in 32 levels. When the value is 100%, the color of the own opaque pixel is completely overwritten on the sketch.
When the value is 50%, the color of its own opaque pixel and the color of the underlying pixel are mixed by 1/2 each. When the value is 0%, the color of the sketch is stored as it is.

The blend ratio is an attribute of the transfer source image 95 and is specified as a part of scenario data described later. After the transparent pixels and the opaque pixels are determined according to the drawing method of the transfer source image 95, the blending process is performed on the opaque pixels.

This blending process is specifically described in FIG.
As shown in (1), the background image 98 already written on the drawing page 96 is mixed with the transfer source image 95, and the blended image is drawn in the rectangular area specified by the register (not shown) of the transfer destination image position. Things.
The blending coefficient can be arbitrarily specified for each of the transfer source image 95 and the background image 98 by a predetermined register from 0.0 to 1.0 in units of 1/32.
The value of each color component of RGB is set to 6 by the blending process.
If the bit exceeds “63”, it is clipped to “63”.

When the blending process S107 is completed, VR
After being drawn on the AM 26, the liquid crystal display interface 39 reads the drawn final image from the VRAM 26 and outputs it to the display unit 11 such as a liquid crystal display.

If only a part of the image is displayed on the network display 1 instead of the entire image, it is not necessary to decode the entire image, and the display memory can be reduced. The size of the display memory and the size of the display panel may be changed depending on each network display 1. For example, one network display 1 can display “ABCD”, another network display 1 can display “AB”, and another network display 1 can display only “A”. It may be large.

In the above embodiment, the clip processing S1
Since the blend processing S107 is not performed on the pixel subjected to the mask processing 05 or the mask processing S106, the calculation amount of the CPU 21, the dedicated graphics LSI 22, and the like is reduced, and high-speed drawing can be performed. Further, since the blending process is the last process, there is no disadvantage that unnecessary colors remain.

Although the above-described embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. is there. For example, each buffer block 42,
The access order of 43, 44, 45, 46 is determined by the CPU 21.
And access to the memory 23 and access to the VRAM 26 may be different. Furthermore, although a double buffer is shown as an example of the ring buffer, a normal first-in first-out ring buffer may be used.

In the above-described embodiment, all the two buffers in each of the buffer blocks 42, 43, 44, and 45 are the same. However, one pair of the two buffers is the same, and the other pair is the same. The buffer may have a different size. Each of the buffer blocks 42, 43, 4
All two buffers of 4, 45 and 46 may be the same.

In this embodiment, the RGB values are (31,
Although two colors, 62, 31) and (31, 63, 31), are transparent, only one color may be assigned as a transparent color, or three or more colors may be made transparent. The transparent color is preferably white as described above, but may be another color.

Further, in addition to the blending process S107 and the clipping process S105, other processes such as a sprite automatic moving process can be performed. After performing the blending process S107, the color defined as the transparent color may be replaced with another color. This is suitable when reusing the image subjected to the blending process S107.

[0132]

The present invention can be applied to a device that does not have a server like the network display 1 and does not have a server but simply reproduces animations and images. Further, the above-described processing steps may be programmed and recorded on a computer-readable information recording medium. In this case, a hard disk or the like in the host server may be used as the medium in addition to a medium such as a CD-ROM or a floppy disk. When the program is recorded on a hard disk or the like of the host server, the program can be transmitted using a communication network such as the Internet or wireless communication such as a television broadcast.

[0133]

As described above, in the image processing apparatus according to the first to fifth aspects, the overwriting process can be performed without imposing a load on the CPU or the like. Further, in the image processing apparatus according to the sixth aspect, the processing of the mask applied to the image can be efficiently performed. Furthermore, in the image processing apparatus according to the seventh to tenth aspects, a multifunctional image processing apparatus can be configured at a low price without complicating.

The information recording medium according to the eleventh to thirteenth aspects includes a step of detecting whether overwriting is required, a step of masking an image, and a step of selecting a plurality of modes. Or have been. When such an information recording medium is read and executed by a computer, overwriting processing can be performed without imposing a load on a CPU or the like, processing of a mask applied to an image can be efficiently performed, and Choose the two modes appropriately,
You can do it.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of an Internet system to which a network display incorporating an image processing apparatus according to an embodiment of the present invention is connected.

FIG. 2 is a perspective view showing an overview of the network display of FIG. 1;

FIG. 3 is a block diagram showing a circuit configuration of the network display of FIG. 1;

FIG. 4 is a block diagram showing a circuit configuration of a dedicated graphics LSI in the network display of FIG. 1;

FIG. 5 is a memory 2 in the network display of FIG. 3;
FIG. 3 is a diagram for explaining the role of a scenario stored in the third scenario.

FIG. 6 is a diagram for explaining a basic operation of an image processing unit in a dedicated graphics LSI used for the network display of FIG. 1;

7 is a circuit block diagram illustrating an internal configuration of an image processing unit of the dedicated graphics LSI of FIG.

8 is a circuit block diagram illustrating an internal configuration of a memory control unit in the image processing unit of FIG.

9 is a diagram illustrating a case where the dedicated graphics LSI of FIG.
FIGS. 7A and 7B are diagrams for explaining the structure of data exchanged with the VRAM 26 and the byte mask signal, wherein FIG. 9A shows data for one word, FIG. It is a figure which shows the example of the byte mask signal in case of B).

FIG. 10 is a circuit block diagram showing an internal configuration of an original drawing image buffer block in the image processing unit of FIG. 7;

11 is a circuit block diagram illustrating an internal configuration of a final drawing image buffer block in the image processing unit of FIG. 7;

12 is a circuit block diagram illustrating an internal configuration of a memory access optimization processing unit in the image processing unit of FIG. 7;

FIG. 13 is a diagram showing the lapse of time of each signal handled by the memory control unit in the image processing unit of FIG. 7, where the buffer block is VR
It is a figure showing the situation at the time of reading (reading) data from AM.

FIG. 14 is a diagram showing the lapse of time of each signal handled by a memory control unit in the image processing unit of FIG. 7, in which a buffer block is VR
FIG. 3 is a diagram illustrating a situation when data is written to an AM.

FIG. 15 is a diagram for explaining a processing order of enlargement / reduction processing performed by the dedicated graphics LSI of FIG. 4;

FIG. 16 is a diagram for explaining the principle of transparent color processing performed by the dedicated graphics LSI of FIG. 4;

FIG. 17 is a diagram illustrating the contents of clip processing performed by the dedicated graphics LSI of FIG. 4;

18A and 18B are diagrams showing two methods at the time of the clip processing of FIG. 17, wherein FIG. 18A shows a method of drawing the inside of a clip window, and FIG. 18B shows a portion other than the clip window. It shows the method.

FIG. 19 is a diagram for explaining the contents of a mask process performed by the dedicated graphics LSI of FIG. 4;

20 is a diagram for explaining the content of a painting process performed by the dedicated graphics LSI of FIG. 4;

FIG. 21 is a diagram for describing the content of a blending process performed by the dedicated graphics LSI of FIG. 4;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 network display (device incorporating an image processing device) 2 Internet 3 LAN (local area network) 6 WWW server (HTTP server) 11 display unit 21 CPU 22 dedicated graphics LSI (display processing means) 23 memory 26 VRAM 36 decoding Unit 37 image processing unit 41 memory control unit 42 original drawing image buffer block 43 transparent color data buffer block 44 mask data buffer block 45 background image buffer block 46 final drawing image buffer block 47 data processing unit (overwrite necessity determination unit) 48 Memory access optimization processing unit (overwrite necessity determination unit) 51 access arbitration unit 61 buffer control unit 62, 63 buffer 69, 70 double buffer unit 71 overwrite detection unit 72 Overwrite control buffer 80 Display screen 81 Movie screen 82 Movie screen space 83 Transfer destination image (drawing image) 85 Transfer source image (transfer rectangular image) 86 Transparent mask image (transparent rectangular image)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 5/38 H04N 1/387 H04N 1/387 G06F 15/62 340D F-term (Reference) 5B050 BA08 CA05 CA08 EA09 EA17 EA19 EA22 EA24 FA02 FA05 5C023 AA02 AA11 AA32 AA38 AA40 BA02 BA11 CA01 DA04 DA08 5C076 AA02 AA12 AA17 AA21 AA22 AA36 BA03 BA04 BA06 CA09 CA12 CB02 5C082 BA43 BB01 CA32 CA56 CA59 CA63 CB01 DA49 DA54 DA87 MM

Claims (13)

[Claims] An image processing apparatus that generates display data by superimposing a plurality of images by a display processing unit that performs image display processing detects whether or not overwriting is necessary for each predetermined block. An image processing apparatus, comprising: a determination unit, wherein when overwriting is unnecessary, the next block is processed without performing overwriting. 2. The overwriting necessity judging section includes an overwriting detecting section for detecting necessity of overwriting, an overwriting control buffer for storing a detected signal by a predetermined amount, and a processing pixel number detecting section for detecting the number of processing pixels. 2. The image processing apparatus according to claim 1, further comprising: a write mask detecting unit that supplies a byte mask signal to a portion that does not need to be overwritten. 3. The overwriting control buffer has a capacity capable of storing 16 pixels, and transfers the data to the next processing unit in units of 16 pixels.
The image processing apparatus according to any one of the preceding claims. 4. The image processing apparatus according to claim 1, wherein said overwriting necessity judging unit judges the necessity of overwriting with eight pixels as one block. 5. When at least one of the pixels in the predetermined block needs to be overwritten, the entire block is subjected to overwrite processing. When overwriting is not required for all the pixels in the predetermined block, the overwrite processing is performed. 5. The image processing apparatus according to claim 1, wherein the image processing is not performed. 6. A mask for setting a mask area for dividing a mask into an image to be displayed on a display unit in an image processing apparatus for processing a predetermined image by display processing means for performing image display processing and generating display data. Provide setting means,
The image processing apparatus according to claim 1, wherein the mask area is formed by repeatedly laying a predetermined mask pattern a plurality of times like a tile. 7. An image processing apparatus for generating display data by superimposing a plurality of images by a display processing means for performing image display processing, wherein a specific area is added to a predetermined area in addition to an attaching mode for attaching an image forming sprite to a predetermined area. An image processing apparatus characterized in that the filling mode for filling with a single color is performed by the same circuit that performs the processing of the sticking mode. 8. The image processing apparatus according to claim 7, wherein in the pasting mode, at least an overwriting process, a blending process, and a transparent color process are performed. 9. The image processing apparatus according to claim 7, wherein the specific area is a rectangular area. 10. The image processing apparatus according to claim 7, wherein each of the images is a natural image represented by 4 to 8 bits of RGB. 11. An overwrite judging step of detecting whether or not overwriting is necessary for each predetermined block, a step of performing the next block processing without performing overwriting processing when overwriting is unnecessary, and a display processing means. Computer-readable information recording medium recording a program for executing the steps of processing an image for each block and generating display data. 12. A step of setting a mask area for masking an image to be displayed on a display unit, a step of forming the mask area by repeatedly laying a plurality of predetermined mask patterns like tiles, and a display process. And a computer-readable information recording medium on which a program for executing a step of processing an image including the mask area by the means and generating display data is executed. 13. A mode in which a mode in which an image forming sprite is pasted to a predetermined area and a mode in which a specific area is filled with a predetermined single color can be selected alternatively, and an image is displayed in a mode selected by the display processing means. Computer-readable information medium having recorded thereon a program for executing the steps of processing and generating display data.