JP2000022510A - Rc delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dispersion in delay time even when the absolute values of the threshold of a PMOS transistor and an NMOS transistor tend to disperse in mutually opposite directions in a RC delay circuit. SOLUTION: This circuit is composed of at least one set of delay circuits composed by serially connecting a first delay circuit 11 and a second delay circuit 12. The first delay circuit 11 is provided with a first RC circuit 110 and a first CMOS inverter circuit IV2 connected to the output side, and the second delay circuit 12 is provided with a second RC circuit 120 and a second CMOS inverter circuit IV2 connected to the output side. The transition direction of the input potential of the first CMOS inverter circuit accompanying the transition of the logic level of the input signals of the first delay circuit 11 and the transition direction of the input potential of the second CMOS inverter circuit are opposite to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a MOS structure.
C delay circuit, for example, DRAM, SRAM
It is used for memories, logic gates, CPUs and the like.

[0002]

2. Description of the Related Art FIGS. 13 and 16 show a conventional example 1 and a conventional example 2 of an RC delay circuit using a CMOS inverter formed in an integrated circuit having a MOS structure.

<Conventional Example 1> The RC delay circuit shown in FIG. 13 has a plurality of (two in this example) delay circuits 131 connected in series, and this delay circuit 131 has a two-stage CMO.
RC circuit 130 between stages between S inverters IV1 and IV2
Is inserted. In this case, the CMOS inverters IV1 and IV2 are respectively connected as shown in FIG.
PMOS transistor TP, NMOS transistor TN
Are connected to each other, and the gates are connected to each other.

In the RC circuit 130, a resistance element R and an NMOS capacitor C are connected in series, one end of the resistance element is connected to the output node of the preceding CMOS inverter IV1, and the other end of the resistance element is connected to the next node. Dan CM
It is connected to the input node of OS inverter IV2.
That is, one end of the resistance element is connected to the drain of an NMOS transistor (not shown) of the CMOS inverter IV1 in the previous stage, and the other end of the resistance element is connected to the CMO of the next stage.
It is connected to the gate of a PMOS transistor (not shown) of the S inverter IV2.

<Conventional Example 2> The RC delay circuit shown in FIG. 16 has a plurality of (two in this example) delay circuits 161 connected in series, and this delay circuit 161 has a two-stage CMO.
RC circuit 160 between stages between S inverters IV1 and IV2
Is inserted. In this case, in the RC circuit 160, a resistance element R and a PMOS capacitor C are connected in series, one end of the resistance element is connected to the output node of the preceding CMOS inverter IV1, and the other end of the resistance element is connected to the next CMOS inverter. It is connected to the input node of inverter IV2. That is, one end of the resistance element is connected to the drain of a PMOS transistor (not shown) of the preceding CMOS inverter IV1, and the other end of the resistance element is connected to the next stage C
It is connected to the gate of an NMOS transistor (not shown) of the MOS inverter IV2.

However, the RC delay circuit of the first conventional example shown in FIG. 13 and the RC delay circuit of the second conventional example shown in FIG. 16 have the absolute value and NM of the threshold value of the PMOS transistor of the CMOS inverter due to a variation in the manufacturing process.
When the absolute values of the threshold values of the OS transistors vary in opposite directions, there is a problem that the delay time also varies, which will be described in detail below.

With respect to the RC delay circuits shown in FIGS. 13 and 16, (a) the threshold value VTP of the PMOS transistor is equal to the design value (eg, -0.6 V) and the threshold value VTN of the NMOS transistor is equal to the design value (eg, 0.5 V). Case and (b)
When the absolute value | VTP | of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value | VTN | of the threshold value of the NMOS transistor decreases by, for example, 0.2 V due to process variation (VTP is -0.8 V, VTN is 0) .3V) and
(C) When the absolute value | VTP | of the threshold value of the PMOS transistor decreases by 0.2 V and the threshold value of the NMOS transistor increases by, for example, 0.2 V due to process variation (VTP
Are −0.4 V and VTN is 0.7 V), the simulation result of the input / output voltage waveform and the main node voltage waveform when the input signal voltage is changed from “L” level to “H” level is shown. FIG. 14, FIG. 15, FIG. 17, FIG.
FIG.

FIGS. 14 (a), 14 (b), and 14 (c) show FIG.
In the case where the threshold value of the MOS transistor of the RC delay circuit according to the conventional example 1 shown in (a) is the above-mentioned (a) design value, it fluctuates as shown in (b), or it fluctuates as shown in (c) above About the input voltage Vin2 and the output voltage Vo
The simulation waveform of ut2 is shown.

FIGS. 15 (a), (b) and (c) show FIG.
In the case where the threshold value of the MOS transistor of the RC delay circuit according to the conventional example 1 shown in (a) is the above-mentioned (a) design value, it fluctuates as shown in (b), or it fluctuates as shown in (c) above About the main node voltage Vin2, V1
5, simulation waveforms of V16, V18, and V19 are shown. Here, t5 is the voltage of the intermediate node from the input voltage Vin2.
The signal transmission time till V16, t6 indicates the signal transmission time from the intermediate node voltage V16 to the intermediate node voltage V19.

That is, in the RC delay circuit of the conventional example 1 shown in FIG. 13, as can be seen from FIGS. 14A, 14B and 14C, the absolute value of the threshold value of the PMOS transistor and the NMOS
When the absolute value of the threshold value of the transistor varies in the opposite direction, the input / output waveform (input / output characteristics) fluctuates greatly. The reason will be described below.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 131 at the preceding stage in FIG. 13 decreases, and the delay of the signal transmission time t5 increases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 131 at the middle stage also decreases, and the signal transmission time t6 as shown in FIG.
Also increases the delay. Therefore, the signal transmission time t
The sum of 5, t6 is larger than when the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 131 at the preceding stage in FIG. 13 rises, and the delay of the signal transmission time t5 decreases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 131 in the middle stage also increases, and the signal transmission time t6 as shown in FIG.
Is also reduced. Therefore, the signal transmission time t
The sum of 5, t6 is smaller than when the threshold is a design value.

On the other hand, FIGS. 17 (a), (b) and (c)
The threshold value of the MOS transistor of the RC delay circuit of the conventional example 2 shown in FIG. 16 varies as shown in (a) in the case of the above (a) design value, and as described in the above (c). Input voltage Vin3, output voltage
The simulation waveform of Vout3 is shown.

FIGS. 18A, 18B, and 18C show FIGS.
In the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 2 shown in (a) is the above-described (a) design value, the above-mentioned (b) varies, and the above-mentioned (c) varies. About the main node voltages V21, V2
3, simulation waveforms of V24, V26, and V27 are shown. Here, t7 is the voltage of the intermediate node from the input voltage Vin3.
The signal transmission time from V24 to t24 indicates the signal transmission time from the voltage V24 at the intermediate node to the voltage V27 at the intermediate node.

That is, in the RC delay circuit of the conventional example 2 shown in FIG. 16, as can be seen from FIGS. 17A, 17B and 17C, the absolute value of the threshold value of the PMOS transistor and the NMOS
When the absolute value of the threshold value of the transistor varies in the opposite direction, the input / output waveform (input / output characteristics) fluctuates greatly. The reason will be described below.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold value of the inverter IV2 of the delay circuit 161 at the preceding stage in FIG. 16 decreases, and the delay of the signal transmission time t7 decreases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 161 at the latter stage in the middle also decreases, and the signal transmission time t8 as shown in FIG.
Is also reduced. Therefore, the signal transmission time t
The sum of 7, t8 is smaller than when the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 161 at the preceding stage in FIG. 16 rises, and the delay of the signal transmission time t7 increases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 161 in the latter stage also increases, and the signal transmission time t8 as shown in FIG.
Also increases the delay. Therefore, the signal transmission time t
The sum of 7 and t8 is larger than when the threshold is a design value.

FIGS. 19 and 22 show Conventional Examples 3 and 4 of RC delay circuits using a modified CMOS inverter formed in an integrated circuit having a MOS structure.

<Conventional Example 3> The RC delay circuit shown in FIG. 19 has a plurality (two in this example) of delay circuits 191 connected in series. This delay circuit 191 is composed of a PMOS transistor TP and an NMOS transistor. A modified CMOS inverter IV1a in which a resistance element R is inserted between the drains of TN and their gates are connected, an NMOS capacitor C connected between the drain of the PMOS transistor TP and a ground node, and the PMOS transistor TP Next stage CMO with input node connected to the drain of
And an S inverter IV2. In this case, the modified CMO
An RC circuit is formed by the resistance element R of the S inverter IV1a and the NMOS capacitor C.

That is, one end of the resistance element R of the RC circuit is connected to the NMOS of the preceding modified CMOS inverter IV1a.
The other end of the resistance element R is connected to the drain of the transistor TN.
It is connected to the gate of an S transistor (not shown).

<Conventional Example 4> The RC delay circuit shown in FIG. 22 has a plurality of (two in this example) delay circuits 221 connected in series. This delay circuit 221 is composed of a PMOS transistor TP and an NMOS transistor. A modified CMOS inverter IV1a in which a resistance element R is inserted between the drains of TN and their gates are connected, a PMOS capacitor C connected between the drain TN of the NMOS transistor and a VCC node, and the NMOS transistor TN Next stage CMO with input node connected to the drain of
And an S inverter IV2. In this case, the modified CMO
An RC circuit is formed by the resistance element R of the S inverter IV1a and the PMOS capacitor C.

That is, one end of the resistance element R of the RC circuit is connected to the PMOS of the preceding modified CMOS inverter IV1a.
The other end of the resistor R is connected to the NMO of the next-stage CMOS inverter IV2.
It is connected to the gate of an S transistor (not shown).

However, in the RC delay circuit of Conventional Example 3 shown in FIG. 19 and the RC delay circuit of Conventional Example 4 shown in FIG.
When the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor of the inverter vary in opposite directions, there is a problem that the delay time also varies. This will be described in detail below.

FIGS. 20 (a), 20 (b) and 20 (c) show FIGS.
In the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 3 shown in (a) is the above-mentioned (a) design value, it fluctuates as shown in (b) above, and if it fluctuates as shown in (c) above About the input voltage Vin2 and the output voltage Vo
The simulation waveform of ut2 is shown.

FIGS. 21 (a), 21 (b) and 21 (c) show FIG.
In the case where the threshold value of the MOS transistor of the RC delay circuit of the conventional example 3 shown in (a) is the above-mentioned (a) design value, it fluctuates as shown in (b) above, and if it fluctuates as shown in (c) above About the main node voltage Vin2, V1
7 shows simulation waveforms of 0, V11, V12, and V13. Here, t5 is the voltage of the intermediate node from the input voltage Vin2.
The signal transmission time from V11 to t11 indicates the signal transmission time from the voltage V11 at the intermediate node to the voltage V13 at the intermediate node.

That is, in the RC delay circuit of the conventional example 3 shown in FIG. 19, as can be seen from FIGS. 20 (a), (b) and (c), the absolute value of the threshold value of the PMOS transistor and the NMOS
When the absolute value of the threshold value of the transistor varies in the opposite direction, the input / output waveform (input / output characteristics) fluctuates greatly. The reason will be described below.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 191 at the preceding stage in FIG. 19 decreases, and the delay of the signal transmission time t5 increases as shown in FIG. 21B. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 191 in the middle stage also decreases, and as shown in FIG.
The delay of t6 also increases. Therefore, the above signal transmission time
The sum of t5 and t6 is larger than when the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 191 in the preceding stage in FIG. 19 rises, and the delay of the signal transmission time t5 decreases as shown in FIG. FIG.
The circuit threshold of the inverter IV2 of the delay circuit 191 in the latter stage also increases, and the signal transmission time t6 as shown in FIG.
Is also reduced. Therefore, the signal transmission time t
The sum of 5, t6 is smaller than when the threshold is a design value.

On the other hand, FIGS. 23 (a), (b) and (c)
The threshold value of the MOS transistor of the RC delay circuit of the conventional example 4 shown in FIG. 22 varies as shown in FIG. Input voltage Vin3, output voltage
The simulation waveform of Vout3 is shown.

FIGS. 24 (a), 24 (b) and 24 (c) show the state shown in FIG.
In the case where the threshold value of the MOS transistor of the RC delay circuit according to the conventional example 4 shown in (a) is the above-mentioned (a) design value, the above-mentioned (b) varies, and the above-mentioned (c) varies. About the main node voltage V15, V1
6, V17, V18, and V19 are shown. Here, t7 is the voltage of the intermediate node from the input voltage Vin3.
A signal transmission time from V17 to t17 indicates a signal transmission time from the voltage V17 at the intermediate node to the voltage V19 at the intermediate node.

That is, in the RC delay circuit of the conventional example 4 shown in FIG. 22, as can be seen from FIGS. 23A, 23B and 23C, the absolute value of the threshold value of the PMOS transistor and the NMOS
When the absolute value of the threshold value of the transistor varies in the opposite direction, the input / output waveform (input / output characteristics) fluctuates greatly. The reason will be described below.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The threshold value of the inverter IV2 of the delay circuit 221 at the preceding stage in FIG. 22 decreases, and the delay of the signal transmission time t7 decreases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 221 in the latter stage also decreases, and the signal transmission time t8 as shown in FIG.
Is also reduced. Therefore, the signal transmission time t
The sum of 7, t8 is smaller than when the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 221 at the preceding stage in FIG. 22 rises, and the delay of the signal transmission time t7 increases as shown in FIG. FIG.
The circuit threshold value of the inverter IV2 of the delay circuit 221 in the latter stage also increases, and the signal transmission time t8 as shown in FIG.
Also increases the delay. Therefore, the signal transmission time t
The sum of 7 and t8 is larger than when the threshold is a design value.

[0042]

As described above, in the conventional RC delay circuit, when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in directions opposite to each other, However, there is a problem that the delay time varies.

The present invention has been made in order to solve the above-mentioned problem. Even when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in directions opposite to each other, the delay can be reduced. An object of the present invention is to provide an RC delay circuit with less time variation.

[0044]

According to a first aspect of the present invention, there is provided an RC delay circuit comprising at least one set of unit delay circuits each having a first delay circuit and a second delay circuit connected in series. A first RC circuit including a first input circuit, a first resistor element and a first capacitor connected in series to an output node of the first input circuit; A first CMOS inverter circuit having an input node connected to a series connection node of a first resistor element and a first capacitor, and the second delay circuit has a second delay circuit.
And an output node of the second input circuit
A second RC circuit in which a second resistance element and a second capacitor are connected in series;
A second CMOS inverter circuit in which an input node is connected to a series connection node of a capacitor of the second type, and a transition direction of an input potential of the first CMOS inverter circuit in accordance with a transition of a logic level of an input signal and the second CMOS inverter circuit. The input potential of the CMOS inverter circuit is opposite to the transition direction.

According to a second aspect of the present invention, there is provided an RC delay circuit comprising at least one set of unit delay circuits each including a first delay circuit and a second delay circuit connected in series. , A first PMOS transistor and a first NM
A first resistance element is inserted between the drains of the OS transistor, and the first PMOS transistor and the first N
A first input circuit in which the gates of the MOS transistors are connected to each other, and a drain connected to the drain of the first PMOS transistor and a discharge potential node to form a first RC circuit together with the first resistance element; A first CMOS inverter circuit having an input node connected to a drain of the first PMOS transistor, wherein the second delay circuit includes a second PMOS transistor and a second NMOS transistor A second input circuit in which a second resistance element is inserted between the drains of the second NMOS transistor and the gates of the second PMOS transistor and the second NMOS transistor are connected to each other; A second capacitor connected between the second node and a potential node to form a second RC circuit with the second resistance element; When the second CMO input node to the drain of the second NMOS transistor is connected
And an S inverter circuit.

The RC delay circuit according to a third aspect of the present invention is provided with at least one set of unit delay circuits each having a first delay circuit and a second delay circuit connected in series, wherein the first delay circuit is , A first PMOS transistor and a first NM
A first resistance element and a second resistance element are inserted in series between the drains of the OS transistor, and the first PM
A first input circuit in which the gates of the OS transistor and the first NMOS transistor are connected to each other; and a second input circuit connected between a series connection node of the first resistance element and the second resistance element and a discharge potential node. A first capacitor, a second capacitor connected between a series connection node of the first resistance element and the second resistance element and a charging potential node, and the first resistance element and the second resistance element A first CMOS inverter circuit having an input node connected to a series connection node of the first and second transistors, and the second delay circuit includes a third resistance element between a drain of a second PMOS transistor and a drain of a second NMOS transistor. And a second input circuit in which a fourth resistance element is inserted in series, and gates of the second PMOS transistor and the second NMOS transistor are connected to each other; A third capacitor connected between a series connection node of the third resistance element and the fourth resistance element and a discharge potential node; and a series connection node of the third resistance element and the fourth resistance element. A fourth capacitor connected between the third node and the charging potential node; and a second CMOS inverter circuit having an input node connected to a series connection node of the third resistor and the fourth resistor. Features.

A RC delay circuit according to a fourth aspect of the present invention is an RC delay circuit in which a resistance element and a capacitor are connected in series in an integrated circuit.
A first delay circuit and a second delay circuit including a C circuit are provided in series, and with the transition of the logic level of the input signal,
The potential of a connection node between the resistance element and the capacitor of the RC circuit in the first delay circuit and the potential of the connection node between the resistance element and the capacitor of the RC circuit in the second delay circuit transition in opposite directions. It is characterized by becoming.

[0048]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows an RC delay circuit according to a first embodiment of the present invention.

The RC delay circuit shown in FIG. 1 is a delay circuit in which two types of delay circuits 11 and 12 are connected in series via an odd-number (one in this example) CMOS inverter circuit 13 in an integrated circuit. At least one set of circuits (1 in this example)
Pairs) are provided.

First delay circuit 11 in the above delay circuit
Has a first RC circuit 110 inserted between the two stages of CMOS inverters IV1 and IV2. in this case,
In the CMOS inverters IV1 and IV2, for example, as shown in FIG. 25, the source-drain of the PMOS transistor TP and the drain-source of the NMOS transistor TN are connected in series between the VCC node and the ground node. PMOS transistor TP and NMOS
It has a normal configuration in which the gates of the transistor TN are connected to each other.

In the first RC circuit 110, a resistance element R and an NMOS capacitor Cn are connected in series, and one end of the resistance element R is connected to the CMOS inverter IV1 in the preceding stage.
And the other end of the resistance element R is connected to the input node of the next-stage CMOS inverter IV2.

That is, one end of the resistance element R is connected to the NMOS transistor TN of the preceding CMOS inverter IV1.
The other end of the resistance element R is connected to the PMOS transistor T of the next-stage CMOS inverter IV2.
It is connected to the gate of P.

The second delay circuit 12 in the delay circuit has a second RC circuit 120 inserted between the two stages of CMOS inverters IV1 and IV2. In this case, the second RC circuit 120 includes the resistance element R and the PM
An OS capacitor Cp is connected in series, and the resistance element R
Is connected to the output node of the preceding CMOS inverter IV1, and the other end of the resistance element R is connected to the next-stage CMOS inverter IV1.
It is connected to the input node of S inverter IV2.

That is, one end of the resistance element R is connected to the PMOS transistor TP of the preceding CMOS inverter IV1.
The other end of the resistance element R is connected to the NMOS transistor T2 of the next-stage CMOS inverter IV2.
It is connected to the N gate.

Here, the R according to the first embodiment shown in FIG.
Regarding the C delay circuit, (a) a case where the threshold value VTP of the PMOS transistor is a design value (for example, -0.6 V) and a threshold value VTN of the NMOS transistor is a design value (for example, 0.5 V); The absolute value of the threshold value of the transistor | VTP |
The absolute value of the threshold value of the S transistor | VTN |
V (when VTP is -0.8 V and VTN is 0.3 V), and (c) the absolute value | VTP |
For example, when the threshold value of the NMOS transistor increases by 0.2 V (when VTP is −0.4 V and VTN is 0.7 V), the input when the input signal voltage is changed from “L” level to “H” level Simulation results of the output voltage waveform and the voltage waveform of the main node are shown in FIGS.

FIGS. 2A, 2B, and 2C show the case where the threshold value of the MOS transistor of the RC delay circuit of the first embodiment shown in FIG. 1 is the aforementioned (a) design value. (B)
The simulation waveforms of the input voltage Vin0 and the output voltage Vout0 are shown for the case of the variation as shown in FIG.

FIGS. 3 (a), 3 (b) and 3 (c) show the case where the threshold value of the MOS transistor of the RC delay circuit of the first embodiment shown in FIG. (B)
In the case of the variation as shown in (c), the voltages Vin0, V1, V2,
7 shows simulation waveforms of V3, V5, and V6.

Here, t1 is the signal transmission time from the input voltage Vin0 to the intermediate node voltage V2, and t2 is the intermediate node voltage V3
5 shows the signal transmission time from the signal V1 to the intermediate node voltage V6.

When the result of the simulation of the RC delay circuit of the first embodiment is compared with the result of the simulation of the RC delay circuit of the first conventional example, the absolute value of the threshold value of the PMOS transistor and the NMOS of the RC delay circuit of the first conventional example are compared. Although the input / output characteristics greatly fluctuate when the absolute value of the threshold value of the transistor varies in the opposite direction, the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor in the RC delay circuit of the first embodiment. The input / output characteristics are shown in FIG.
(B) and (c) show little change.

The reason will be described.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 11 in FIG. 1 decreases, and the delay of the signal transmission time t1 increases as shown in FIG. 3B. In contrast, FIG.
The circuit threshold value of the inverter IV2 of the middle second delay circuit 12 also decreases, and the delay of the signal transmission time t2 decreases as shown in FIG. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 11 in FIG. 1 rises, and the delay in the signal transmission time decreases as shown in FIG. 3 (c). On the other hand, the circuit threshold of the inverter IV2 of the second delay circuit 12 in FIG. 1 also increases, and the delay of the signal transmission time t2 increases as shown in FIG. 3C. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold is a design value.

That is, the RC delay circuit of the first embodiment is
In the integrated circuit, RC circuits 110 and 1 each having a resistance element R and a capacitor Cn or Cp connected in series are provided.
A first delay circuit 11 and a second delay circuit 12, each of which includes a second delay circuit 20, are provided in series.

Then, with the transition of the logic level of the input signal to the RC delay circuit, the potential of the connection node between the resistance element R and the capacitor Cn of the RC circuit 110 of the first delay circuit 11 (the first node in this example). CMOS of delay circuit 11
Input potential of inverter circuit IV2) V1 and resistance element R and capacitor C of RC circuit 120 of second delay circuit 12
The potential VS of the connection node with the p (in this example, the second delay circuit 1
(The input potentials of the two CMOS inverter circuits IV2) transition in the opposite direction.

In this case, the two transitions of the logic level of the input signal of the second delay circuit 12 are opposite to the transition direction of the logic level of the input signal of the first delay circuit 11. Odd-numbered inverter circuit 13 between delay circuits
Is inserted.

With such a configuration, even when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in opposite directions, the delay time of the two delay circuits 11 and 12 is reduced. Changes cancel each other, and variations in delay time can be suppressed as a whole.

The circuit on the input side of the first delay circuit 11 is not limited to the CMOS inverter IV1, but has an NMOS transistor connected between the resistance element R of the first RC circuit 110 and the discharge potential node. Any input circuit may be used, and a CMOS logic circuit (for example, a NAND circuit or a NOR circuit) that performs logical processing on a plurality of input signals may be used.

Similarly, the circuit on the input side of the second delay circuit 12 is not limited to the CMOS inverter IV1 but may be the second circuit.
The input circuit may be any input circuit having a PMOS transistor connected between the resistance element R of the RC circuit 120 and the charging potential node, and may be a CMOS logic circuit that logically processes a plurality of input signals.

The capacitor in the first RC circuit 110 is not limited to the NMOS capacitor Cn used by short-circuiting the drain and source of the NMOS transistor as described above, but may be a capacitor having another configuration. NMOS capacitors are desirable from the viewpoint of simplification of design and process.

Similarly, the capacitor in the second RC circuit 120 is not limited to the PMOS capacitor Cp used by short-circuiting the drain and source of the PMOS transistor as described above, but may be a capacitor having another configuration. However, in terms of design and process simplification, PMOS
Capacitors are preferred. The above NMOS,
It goes without saying that the PMOS and the capacitor may have a so-called MIS structure in which the gate insulating film is formed of an insulating film other than an oxide film, and the same applies to the following.

Further, in the RC delay circuit of the first embodiment, the first delay circuit 11 having the first RC circuit 110
Is provided in the first stage, and the second delay circuit 12 including the second RC circuit 120 is provided in the second stage.
Alternatively, the configuration may be such that the order of the second delay circuit 12 is reversed.

In order to cancel the variation in the delay time of the first delay circuit 11 and the variation in the delay time of the second delay circuit 12, the resistance value of the resistance element R in the first delay circuit 11 and the capacitor Cn capacitance value and CMOS
The product of the sum of the input gate capacitance value of the inverter IV2 and the sum of the resistance value of the resistance element R in the second delay circuit 12, the capacitance value of the capacitor Cp, and the input gate capacitance value of the CMOS inverter IV2. It is desirable, but there is no problem if both are imbalanced within the allowable range.

However, the resistance element R of the first delay circuit 11
And the resistance value of the resistance element R of the second delay circuit 12 are set to be substantially equal, and the capacitance value of the capacitor Cn of the first delay circuit 11 and the capacitance value of the capacitor C of the second delay circuit 12 are set.
The first delay circuit 11 is set so that the capacitance value of the first delay circuit 11 and the size of the PMOS transistor of the second delay circuit 12 are substantially equal to each other. It is particularly desirable to set the size of the NMOS transistor 11 and the size of the NMOS transistor of the second delay circuit 12 to be substantially equal from the viewpoint of simplification of design.

<Second Embodiment> FIG. 4 shows an RC delay circuit according to a second embodiment.

The RC delay circuit shown in FIG. 4 is different from the RC delay circuit of the first embodiment shown in FIG. 1 in that: (1) the resistance element R and the NMOS capacitor Cn in the first delay circuit 41;
That the PMOS capacitor Cp is additionally connected between the connection node of the second delay circuit 42 and the ground node between the resistance node R and the PMOS capacitor Cp in the second delay circuit 42. NMOS capacitor C
n is additionally connected, and the others are the same.

FIGS. 5A, 5B, and 5C show the case where the threshold value of the MOS transistor of the RC delay circuit of the second embodiment shown in FIG. 4 is the aforementioned (a) design value. (B)
The simulation waveforms of the input voltage Vin1 and the output voltage Vout1 are shown for the case of the variation as shown in FIG.

FIGS. 6A, 6B, and 6C show the case where the threshold value of the MOS transistor of the RC delay circuit of the second embodiment shown in FIG. 4 is the aforementioned (a) design value. (B)
In the case of the variation as shown in (c), the voltages Vin1, V8, V9,
The simulation waveforms of V10, V12, and V13 are shown. Here, t3 is the voltage V9 of the intermediate node from the input voltage Vin1.
T4 indicates the signal transmission time from the intermediate node voltage V10 to the intermediate node voltage V13.

When the result of the simulation of the RC delay circuit of the second embodiment is compared with the result of the simulation of the RC delay circuit of the second prior art, the absolute value of the threshold value of the PMOS transistor and the NMOS of the RC delay circuit of the second prior art are compared. Although the input / output waveform (input / output characteristics) greatly fluctuates when the absolute value of the threshold value of the transistor fluctuates in the opposite direction, the absolute value of the threshold value of the PMOS transistor and the NMOS value are different in the RC delay circuit of the second embodiment. Even when the absolute values of the threshold values of the transistors vary in the opposite directions, FIG.
As shown in (a), (b), and (c), the input / output waveform (input / output characteristics) hardly changes.

The reason will be described.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 41 in FIG. 4 decreases, and the delay of the signal transmission time t3 increases as shown in FIG. 6B. In contrast, FIG.
The circuit threshold of the inverter IV2 of the middle second delay circuit 42 also decreases, and the delay of the signal transmission time t4 decreases as shown in FIG. 6B. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 41 in FIG. 4 rises, and the delay of the signal transmission time t3 decreases as shown in FIG. 6C. In contrast, FIG.
The circuit threshold value of the inverter IV2 of the middle second delay circuit 42 also increases, and the delay of the signal transmission time t4 increases as shown in FIG. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.

Therefore, like the RC delay circuit of the first embodiment, the RC delay circuit of the second embodiment differs from the RC delay circuit of the first embodiment in that the absolute value of the threshold value of the PMOS transistor and the NMO
Even when the absolute value of the threshold value of the S transistor varies in the opposite direction, the changes in the delay time of the two delay circuits cancel each other out, and the variation in the delay time can be suppressed as a whole.

Further, the RC delay circuit of the second embodiment differs from the RC delay circuit of the first embodiment in that the input signal voltage changes from "L" level to "H" level, When the voltage changes from the "H" level to the "L" level, almost the same delay can be obtained, and even if the threshold voltage of the MOS transistor varies as described above, the overall delay time is almost the same.

The RC delay circuit of the second embodiment also has the same structure as the RC delay circuit of the first embodiment.
Various modifications can be made and appropriate constants can be set.

<Third Embodiment> FIG. 7 shows an RC delay circuit according to a third embodiment.

The RC delay circuit shown in FIG. 7 uses the first delay circuit shown in FIG.
The delay circuit differs from the RC delay circuit of the embodiment.

That is, in the RC delay circuit shown in FIG. 7, in the integrated circuit, two types of delay circuits 71 and 72 are connected in series via an odd-numbered (one in this example) CMOS inverter circuit 73. At least one set (in this example, one set) is provided.

First delay circuit 71 in the above delay circuit
The resistor R is inserted between the drains of the PMOS transistor TP and the NMOS transistor TN;
A modified CMOS inverter IV1a in which the gates of a MOS transistor and an NMOS transistor are connected to each other; an NMOS capacitor Cn connected between the drain of the PMOS transistor TP and a ground node;
It comprises a next-stage CMOS inverter IV2 in which the input node is connected to the drain of the OS transistor TP.

In this case, the modified CMOS inverter IV1
A third RC circuit is formed by the resistance element R and the NMOS capacitor Cn. That is, the third R
One end of the resistance element R of the C circuit is connected to the drain of the NMOS transistor TN of the preceding modified CMOS inverter IV1a, and the other end of the resistance element R is connected to the next CMOS.
The PMOS transistor of the inverter IV2 (T in FIG. 25)
P).

In the second delay circuit 72 of the delay circuit, a resistance element R is inserted between the drains of the PMOS transistor TP and the NMOS transistor TN.
Modified CMOS inverter IV1b in which the gates of the PMOS transistor and the NMOS transistor are connected to each other
And a PMOS capacitor Cp connected between the drain of the NMOS transistor TN and the Vcc node, and a CMOS inverter IV2 at the next stage having an input node connected to the drain of the NMOS transistor TN.

In this case, the modified CMOS inverter IV1
A fourth RC circuit is formed by the resistance element R of b and the PMOS capacitor Cn. That is, the fourth R
One end of the resistance element R of the C circuit is connected to the drain of the PMOS transistor TP of the preceding modified CMOS inverter IV1b, and the other end of the resistance element R is connected to the next CMOS.
The NMOS transistor of the inverter IV2 (T in FIG. 25)
N).

FIGS. 8A, 8B and 8C show the case where the threshold value of the MOS transistor of the RC delay circuit of the third embodiment shown in FIG. 7 is the aforementioned (a) design value. (B)
The simulation waveforms of the input voltage Vin0 and the output voltage Vout0 are shown for the case of the variation as shown in FIG.

FIGS. 9 (a), 9 (b) and 9 (c) show the case where the threshold value of the MOS transistor of the RC delay circuit of the third embodiment shown in FIG. (B)
In the case of the variation as shown in (c), the voltages Vin0, V0, V1,
7 shows simulation waveforms of V2, V3, and V4. Here, t1 indicates the signal transmission time from the input voltage Vin0 to the intermediate node voltage V1, and t2 indicates the signal transmission time from the intermediate node voltage V2 to the intermediate node voltage V4.

When the result of the simulation of the RC delay circuit of the third embodiment is compared with the result of the simulation of the RC delay circuit of the third conventional example, the absolute value of the threshold value of the PMOS transistor and the NMOS of the RC delay circuit of the third conventional example are compared. Although the input / output waveform (input / output characteristics) greatly fluctuates when the absolute value of the threshold value of the transistor fluctuates in the opposite direction, the absolute value of the threshold value of the PMOS transistor and the NMOS value are different in the RC delay circuit of the second embodiment. Even when the absolute values of the threshold values of the transistors vary in opposite directions, FIG.
As shown in (a), (b), and (c), the input / output waveform (input / output characteristics) hardly changes.

The reason will be described.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 71 in FIG. 7 decreases, and the delay of the signal transmission time t1 increases as shown in FIG. 9B. In contrast, FIG.
The circuit threshold value of the inverter IV2 of the second delay circuit 72 in the middle also decreases, and the delay of the signal transmission time t2 decreases as shown in FIG. 9B. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the first delay circuit 71 in FIG. 7 rises, and the delay of the signal transmission time t1 decreases as shown in FIG. 9C. In contrast, FIG.
The circuit threshold of the inverter IV2 of the second middle delay circuit 72 also increases, and the delay of the signal transmission time t2 increases as shown in FIG. 9C. In this case, the sum of the signal transmission times t1 and t2 is substantially equal to the case where the threshold is a design value.

Therefore, the RC delay circuit of the third embodiment, like the RC delay circuit of the first embodiment, has the absolute value of the threshold value of the PMOS transistor and the NMO of the PMOS transistor included in the circuit.
Even when the absolute value of the threshold value of the S transistor varies in the opposite direction, the changes in the delay time of the two delay circuits cancel each other out, and the variation in the delay time can be suppressed as a whole.

The RC delay circuit of the third embodiment also has the same structure as the RC delay circuit of the first embodiment.
Various modifications can be made and appropriate constants can be set.

<Fourth Embodiment> FIG. 10 shows an RC delay circuit according to a fourth embodiment.

The RC delay circuit of FIG. 10 differs from the RC delay circuit of the third embodiment shown in FIG. 7 in the delay circuit.

That is, in the RC delay circuit shown in FIG. 10, at least two (two in this example) delay circuits 100 are connected via odd-numbered (one in this example) CMOS inverter circuit 73 in the integrated circuit. At least one set of unit delay circuits (one set in this example) connected in series is provided.

The delay circuit 100 includes a modified CMOS inverter IV1c in which two resistance elements R1 and R2 are inserted between the drains of a PMOS transistor TP and an NMOS transistor TN, and whose gates are connected to each other.
An NMOS capacitor Cn connected between a series connection node of the resistance elements R1 and R2 and a ground node;
A PMOS capacitor Cp connected between a series connection node of the resistance elements R1 and R2 and a Vcc node;
It comprises a next-stage CMOS inverter IV2 in which an input node is connected to a series connection node of the resistance elements R1 and R2.

In this case, in the delay circuit 100 in the preceding stage, a third RC circuit is formed by one resistance element R2 of the modified CMOS inverter IV1c and the NMOS capacitor Cn. That is, one end of the resistance element R2 of the third RC circuit is connected to the modified CMOS inverter I of the preceding stage.
The other end of the resistance element R1 is connected to the gate of the PMOS transistor (TP in FIG. 25) of the next-stage CMOS inverter IV2.

In the delay circuit 100 at the subsequent stage, a fourth RC circuit is formed by one resistance element R1 of the modified CMOS inverter IV1c and the PMOS capacitor Cp. In other words, one end of the resistance element R1 of the fourth RC circuit is connected to the former modified CMOS inverter IV1c.
And the other end of the resistor R1 is connected to the next-stage CMOS inverter I.
It is connected to the gate of the NMOS transistor V2 (TN in FIG. 25).

FIGS. 11A, 11B, and 11C are diagrams of FIG.
The threshold value of the MOS transistor of the RC delay circuit according to the fourth embodiment shown in (a) varies as shown in (b) in the case of the above (a) design value, and as shown in (c) above. For the case, the input voltage Vin1 and the output voltage Vo
The simulation waveform of ut1 is shown.

FIGS. 12A, 12B, and 12C are diagrams of FIG.
The threshold value of the MOS transistor of the RC delay circuit according to the fourth embodiment shown in (a) varies as shown in (b) in the case of the above (a) design value, and as shown in (c) above. For the case, the main node voltage Vin1, V
5 shows simulation waveforms of V6, V7, V8, and V9. Here, t3 is from the input voltage Vin1 to the voltage V6 of the intermediate node.
T4 indicates a signal transmission time from the intermediate node voltage V7 to the intermediate node voltage V9.

When the result of the simulation of the RC delay circuit according to the fourth embodiment is compared with the result of the simulation of the RC delay circuit of the fourth prior art, the absolute value of the threshold value of the PMOS transistor in the RC delay circuit of the fourth prior art is NMO
When the absolute value of the threshold value of the S transistor fluctuates in the opposite direction, the input / output waveform (input / output characteristics) greatly fluctuates. However, in the RC delay circuit of the fourth embodiment, the absolute value of the threshold value of the PMOS transistor and the input / output waveform are different. Even when the absolute value of the threshold value of the NMOS transistor fluctuates in the opposite direction to each other, FIG.
As shown in (a), (b), and (c), the input / output waveform (input / output characteristics) hardly changes.

The RC delay circuit according to the fourth embodiment differs from the RC delay circuit of the third embodiment in that the input signal voltage changes from "L" level to "H" level, When the signal voltage changes from the "H" level to the "L" level, substantially equal delays can be obtained, and the overall delay time is substantially equal even if there is variation in the threshold voltage of the MOS transistor as described above. .

The reason will be described.

1) The case where the absolute value of the threshold value of the PMOS transistor increases by 0.2 V and the absolute value of the threshold value of the NMOS transistor decreases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 100 at the preceding stage in FIG. 10 decreases, and the delay of the signal transmission time t3 increases as shown in FIG. 12B. On the other hand, the inverter IV of the delay circuit 100 at the subsequent stage in FIG.
The circuit threshold value of No. 2 also decreases, and the delay of the signal transmission time t4 decreases as shown in FIG. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.

2) The case where the absolute value of the threshold value of the PMOS transistor decreases by 0.2 V and the absolute value of the threshold value of the NMOS transistor increases by 0.2 V.

The circuit threshold of the inverter IV2 of the delay circuit 100 at the preceding stage in FIG. 10 rises, and the delay of the signal transmission time t3 decreases as shown in FIG. On the other hand, the inverter IV of the delay circuit 100 at the subsequent stage in FIG.
The circuit threshold value of 2 also increases, and the delay of the signal transmission time t4 increases as shown in FIG. In this case, the sum of the signal transmission times t3 and t4 is substantially equal to the case where the threshold value is a design value.

Therefore, the RC delay circuit of the fourth embodiment, like the RC delay circuit of the first embodiment, has the absolute value of the threshold value of the PMOS transistor included in the circuit and the NMO.
Even when the absolute value of the threshold value of the S transistor varies in the opposite direction, the changes in the delay time of the two delay circuits cancel each other out, and the variation in the delay time can be suppressed as a whole.

Further, the RC delay circuit of the fourth embodiment is different from the RC delay circuit of the first embodiment in that the input signal voltage changes from "L" level to "H" level, When the voltage changes from the "H" level to the "L" level, substantially equal delays are selected, and the overall delay time is substantially equal even if there is variation in the threshold voltage of the MOS transistor as described above.

Note that the RC delay circuit of the fourth embodiment is also similar to the RC delay circuit of the first embodiment described above.
Various modifications can be made and appropriate constants can be set. In this case, in the delay circuit 100 of each stage, the resistance value of the resistance element R1 is substantially equal to the resistance value of the resistance element R2,
The capacitance value of the capacitor Cn is substantially equal to the capacitance value of the capacitor Cp, and the delay circuit 100 in the first stage and the delay circuit 10 in the second stage
It is particularly desirable from the viewpoint of simplification of design that the resistance value of the resistance element R1, the resistance value of the resistance element R2, the capacitance value of the capacitor Cn, and the capacitance value of the capacitor Cp are set to be substantially equal to zero. .

[0125]

As described above, according to the RC delay circuit of the present invention, even when the absolute value of the threshold value of the PMOS transistor and the absolute value of the threshold value of the NMOS transistor included in the circuit vary in the opposite directions, the delay can be reduced. Time variation can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an RC delay circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing waveforms of input / output voltages obtained by simulation in a case where a threshold value of a PMOS transistor and a threshold value of an NMOS transistor in the RC delay circuit in FIG.

3 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 1 when a threshold value of a PMOS transistor and a threshold value of an NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 4 is a circuit diagram showing an RC delay circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing waveforms of input / output voltages obtained by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 4 are designed values and when the threshold value is varied in two different directions.

FIG. 6 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 4 when the threshold value of a PMOS transistor and the threshold value of an NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 7 is a circuit diagram showing an RC delay circuit according to a third embodiment of the present invention.

8 is a diagram showing input / output voltage waveforms obtained by simulation in the RC delay circuit of FIG. 7 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

9 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 7 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 10 is a circuit diagram showing an RC delay circuit according to a fourth embodiment of the present invention.

11 is a diagram showing input / output voltage waveforms obtained by simulation in the RC delay circuit of FIG. 10 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

12 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 10 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 13 is a circuit diagram showing an RC delay circuit of Conventional Example 1.

14 is a diagram showing input / output voltage waveforms obtained by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 13 are designed values and when the threshold value is varied in two different directions.

FIG. 15 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 13 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 16 is a circuit diagram showing an RC delay circuit of Conventional Example 2.

FIG. 17 is a diagram showing waveforms of input / output voltages obtained by simulation in the RC delay circuit of FIG. 16 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 18 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 16 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 19 is a circuit diagram showing an RC delay circuit of Conventional Example 3.

20 is a diagram showing input / output voltage waveforms obtained by simulation when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor in the RC delay circuit of FIG. 19 are designed values and when the threshold value is varied in two different directions.

FIG. 21 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 19 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is scattered in two different directions.

FIG. 22 is a circuit diagram showing an RC delay circuit of Conventional Example 4.

23 is a diagram showing waveforms of input and output voltages obtained by simulation in the RC delay circuit of FIG. 22 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

24 is a diagram showing waveforms of voltages at main nodes in simulations in the RC delay circuit of FIG. 22 when the threshold value of the PMOS transistor and the threshold value of the NMOS transistor are designed values and when the threshold value is varied in two different directions.

FIG. 25 is a circuit diagram showing an example of a CMOS inverter used in a conventional example and an embodiment.

[Explanation of symbols]

 11: first delay circuit, 110: first RC circuit, 12: second delay circuit, 120: second RC circuit, 13, IV1, IV2: inverter circuit, R: resistance element, Cn: NMOS capacitor , Cp ... PMOS capacitor.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshiaki Takeuchi 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Semiconductor System Technology Center (reference) 5J001 AA05 BB10 BB11 BB12 BB17 CC03 DD01 DD04

Claims (15)

[Claims] At least one set of unit delay circuits each comprising a first delay circuit and a second delay circuit connected in series is provided, wherein the first delay circuit comprises: a first input circuit; A first RC having a first resistance element and a first capacitor connected in series to an output node of the first input circuit;
A first CMOS inverter circuit having an input node connected to a series connection node of the first resistance element and the first capacitor, wherein the second delay circuit has a second input circuit; A second RC having a second resistance element and a second capacitor connected in series to an output node of the second input circuit;
And a second CMOS inverter circuit having an input node connected to a series connection node of the second resistance element and the second capacitor, wherein the first CMOS circuit is connected to a transition of a logic level of an input signal.
The transition direction of the input potential of the inverter circuit and the second CM
An RC delay circuit having a direction opposite to a transition direction of an input potential of an OS inverter circuit. 2. The RC delay circuit according to claim 1, wherein said first input circuit has a first NMOS transistor connected between an output node thereof and a discharge potential node, and The input potential of the first CMOS inverter circuit transitions from “H” level to “L” level when discharged from the capacitor through the first resistance element and the first NMOS transistor, and the second input circuit Has a first PMOS transistor connected between its output node and a charging potential node, and is charged when charged from the second capacitor through the second resistance element and the first PMOS transistor. An RC delay circuit wherein the input potential of the second CMOS inverter circuit changes from "L" level to "H" level. 3. The RC delay circuit according to claim 2, wherein the first input circuit has a drain and a gate of a second PMOS transistor connected to a drain and a gate of the first NMOS transistor. CMOS inverter circuit or C for logically processing a plurality of input signals
A MOS logic circuit, wherein the second input circuit is a CMOS inverter circuit having a drain and a gate of a second NMOS transistor connected to a drain and a gate of the first PMOS transistor, or a plurality of input signals. C to logically process
An RC delay circuit, which is a MOS logic circuit. 4. At least one set of unit delay circuits each comprising a first delay circuit and a second delay circuit connected in series is provided, wherein the first delay circuit comprises a first PMOS transistor and a second PMOS transistor. A first input circuit in which a first resistance element is inserted between drains of the first NMOS transistor and a gate of the first PMOS transistor and a gate of the first NMOS transistor are connected to each other; A first capacitor connected between the drain of the first PMOS transistor and a discharge potential node to form a first RC circuit together with the first resistance element; and a first capacitor having an input node connected to the drain of the first PMOS transistor. A second CMOS inverter circuit, and the second delay circuit includes a drain of a second PMOS transistor and a second NMOS transistor. A second input circuit in which a second resistance element is inserted between the gates and the gates of the second PMOS transistor and the second NMOS transistor are connected to each other; a drain of the second NMOS transistor and a charging potential A second capacitor connected between the second resistor and a second resistor, the second capacitor forming a second RC circuit with the second resistance element; a second CMOS inverter circuit having an input node connected to a drain of the second NMOS transistor An RC delay circuit comprising: 5. A semiconductor device comprising: at least one set of unit delay circuits each including a first delay circuit and a second delay circuit connected in series; wherein the first delay circuit includes a first PMOS transistor and a second PMOS transistor. A first input circuit in which a first resistance element and a second resistance element are inserted in series between the drains of one NMOS transistor, and the gates of the first PMOS transistor and the first NMOS transistor are connected to each other A first capacitor connected between a series connection node of the first resistance element and the second resistance element and a discharge potential node; and a series connection of the first resistance element and the second resistance element A second capacitor connected between the node and a charging potential node; a first CM having an input node connected to a series connection node of the first resistance element and the second resistance element An S inverter circuit, wherein the second delay circuit includes a third resistance element and a fourth resistance element inserted in series between the drains of a second PMOS transistor and a second NMOS transistor; A second input circuit in which the gates of the second PMOS transistor and the second NMOS transistor are connected to each other, and a second input circuit connected between a series connection node of the third resistance element and the fourth resistance element and a discharge potential node A third capacitor connected between a series connection node of the third resistance element and the fourth resistance element and a charging potential node; a third capacitor connected to the third resistance element and the fourth resistance element; An RC delay circuit comprising a second CMOS inverter circuit having an input node connected to a series connection node of a resistance element. 6. The RC delay circuit according to claim 1, wherein the first delay circuit and the second delay circuit have an odd-numbered C delay circuit.
An RC delay circuit connected via a MOS inverter circuit. 7. The RC delay circuit according to claim 1, wherein the first capacitor is connected between one end node of the first resistance element and the discharge potential node. NMO
An RC delay circuit, which is an S capacitor, wherein the second capacitor is a PMOS capacitor connected between one end node of the second resistance element and a charging potential node. 8. The RC delay circuit according to claim 1, wherein a resistance value of said first resistance element, a capacitance value of a first capacitor, and an input gate of a first CMOS inverter circuit. The product of the capacitance value and the sum of the capacitance values is the resistance value of the second resistance element and the second resistance element.
An RC delay circuit substantially equal to the product of the capacitance value of the capacitor and the sum of the input gate capacitance values of the second CMOS inverter circuit. 9. The RC delay circuit according to claim 8, wherein a resistance value of said first resistance element is substantially equal to a resistance value of said second resistance element. 10. The RC delay circuit according to claim 8, wherein a capacitance value of the first capacitor is substantially equal to a capacitance value of the second capacitor. 11. The RC delay circuit according to claim 1, wherein said first capacitor is an NMOS capacitor connected between a node on one end of said first resistance element and a discharge potential node, and said first capacitor is A PMOS capacitor connected between one end node of the resistance element and a charging potential node, wherein the second capacitor is connected between the one end node of the second resistance element and the charging potential node PMO
An RC delay circuit comprising an S capacitor and an NMOS capacitor connected between one end node of the second resistance element and the discharge potential node. 12. The RC delay circuit according to claim 5, wherein the third capacitor is connected to a node between the one end node of the third resistance element and the discharge potential node.
An RC delay circuit, wherein the RC capacitor is an S capacitor, and the fourth capacitor is a PMOS capacitor connected between one end node of the fourth resistance element and a charging potential node. 13. The RC delay circuit according to claim 3, wherein a size of the first PMOS transistor and a second PM are set.
An RC delay circuit, wherein the size of the OS transistor is substantially equal to the size of the OS transistor. 14. The RC delay circuit according to claim 3, wherein a size of the first NMOS transistor and a second NM are set.
An RC delay circuit, wherein the size of the OS transistor is substantially equal to the size of the OS transistor. 15. A first delay circuit and a second delay circuit each including an RC circuit in which a resistive element and a capacitor are connected in series are provided in series in an integrated circuit. The potential of the connection node between the resistance element and the capacitor of the RC circuit in the first delay circuit and the potential of the connection node between the resistance element and the capacitor of the RC circuit in the second delay circuit transition in opposite directions. An RC delay circuit comprising: