JP2000020562A - Simulation test bench generation method and its generation device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable the generation of a simulation test bench that compresses test pattern files of a plurality of input signal lines into one test pattern file and reduces the occupation amount of the test pattern file in a recording medium. A digital LSI having a plurality of input signal lines
When generating a simulation test bench for a circuit, a test pattern is created for each input signal line (step 10), and those having the same input timing for at least two or more input signal lines are joined by bit connection. Then, a data-compressed test pattern file is generated (step 11). Then, the test pattern file is read, and a simulation test bench for distributing bits and inputting to the corresponding input signal line is generated (step 12).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital LSI circuit design, and more particularly to a method for generating a simulation test bench for a digital LSI circuit designed using a hardware description language, and an apparatus for generating the simulation test bench.

[0002]

2. Description of the Related Art Conventionally, digital LS using a computer
Verilog H in a DA system with I-circuit design
Circuit design is performed using a hardware description language such as DL or VHDL. Here, as a verification of the logic of the designed digital LSI circuit, verification of the circuit operation is performed by a software simulator. In order to verify the circuit operation using a software simulator, the designed circuit data and a test bench for operating the circuit are required. The test bench includes a test pattern describing an input signal of circuit data and an operation description for inputting the test pattern to an input signal line.
It is described in a hardware description language such as logHDL or VHDL or in C language. Here, the test pattern is often filed in a text format or a binary format for each signal line, and is first read into a memory and then input to a circuit at a required timing.

As shown in FIG. 6, in the conventional simulation test bench generation method, in an LSI circuit having a plurality of input signal lines, a test pattern is created for each signal line, and a step 1 is performed. A step 2 of making a test pattern into a file and a step 3 of reading a test pattern file for each signal line into a memory for each signal line and creating an operation description to be input from the memory to a corresponding signal line are performed. On the other hand, a test bench with individual test pattern files was created.

[0004]

However, in the conventional simulation test bench generation method, specifically, as shown in FIG. 7, a test pattern file 12 is input to an input signal line (in0) 110 of a circuit block 100.
0, the input signal line (in1) 111 has a test pattern 1
21, a test pattern 122 is required for the input signal line (in2) 112, and a test pattern 123 is required for the input signal line (in3) 113. Since a test pattern is required for each signal line, the test pattern is long. In this case, there is a problem that the data occupation amount of the test pattern file in the recording medium is increased.

The problem to be solved by the present invention is (1)
To provide a technique of a simulation test bench generation method for performing data simulation by compressing test pattern files of a plurality of input signal lines into one test pattern file, and (2) testing a digital LSI circuit having a plurality of input signal lines. An object of the present invention is to provide a technique of a simulation test bench generation apparatus for compressing a pattern file into one test pattern file and performing a simulation.

[0006]

According to the present invention, there is provided a digital LSI having a plurality of input signal lines.
When creating a simulation test bench for a circuit, create a test pattern for each input signal line,
At least two or more input signal lines having the same input timing are joined by bit concatenation to generate a data-compressed test pattern file. Then, read the test pattern file,
Provided is a method of generating a simulation test bench for distributing bits and inputting to a corresponding input signal line.

According to the present invention, when a parallel simulation test bench for a digital LSI circuit having a plurality of input signal lines is generated, a test pattern is created for each input signal line for each simulation, and at least two or more test patterns are prepared. The input signal lines having the same input timing are connected by bit concatenation to generate a data-compressed test pattern file. The present invention also provides a method for generating a parallel simulation test bench that reads the test pattern file, distributes the bits, and inputs the test pattern file to a corresponding input signal line.

Further, according to the present invention, when a simulation test bench for a digital LSI circuit having a plurality of input signal lines is generated, a test pattern is created for each input signal line, and the test patterns are formed into at least two or more input signal lines. Are connected at the same input timing by bit concatenation to generate a data-compressed test pattern file. Then, the present invention provides a simulation test bench generation device which reads the test pattern file, distributes the bits, and inputs the bits to the corresponding input signal lines.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a flowchart of a simulation model generation method for explaining a first embodiment of a simulation test bench generation method of the present invention, and FIG.
It is explanatory drawing which shows the specific example of embodiment.

In the first embodiment, Verilog HDL
Veril that has the circuit information designed in the above as input and has a data-compressed text-format test pattern file
ogHDL test bench is generated.

As shown in FIG. 1, the simulation test bench generation method of the first embodiment generates a test bench having a data-compressed test pattern file for a digital LSI circuit having a plurality of input signal lines.

In FIG. 1, at step 10 a test pattern to be input to each input signal line is generated, and at step 11
Then, at least two or more input signal lines of the test pattern generated in step 10 are connected by the bit connection at the same input timing. Then, data compression is performed to generate a test pattern file.
Then, in step 12, the test pattern file generated in step 11 is read into the memory, the test pattern is bit-distributed, and a test bench to be input to the corresponding input signal line is generated.

A specific example shown in FIG. 2 for generating a test bench having a data-compressed test pattern file for a digital LSI circuit having four 1-bit input signal lines will be described with reference to the flowchart of FIG. .

That is, in Step 10, the test pattern 130 of the input signal line (in0) 110, the test pattern 131 of the input signal line (in1) 111, the test pattern 132 of the input signal line (in2) 112, and the input signal line (in3) ) 113 test pattern 133 is generated.

In step 11, the input signal line (in
0) 110 from the test pattern 130 to the input signal line (i
n3) The test pattern 133 of 113 is bit-connected to form a test pattern 134. Then, the test pattern 134 is expressed in hexadecimal notation, and the data is compressed into a file to form a test pattern file 135
Generate

In step 12, the test pattern file 135 filed is converted into a 4-bit signal in [3:
0] 114, and is distributed to four 1-bit input signals from the input signal lines (in0) 110 to (in3) 113 to generate a test bench to be input to the circuit block 100.

As described above, by concatenating the test patterns and compressing the data into a file, the data occupation amount of the test pattern in the recording medium can be reduced.

FIG. 3 is a flowchart of a simulation model generation method for explaining a second embodiment of the simulation test bench generation method of the present invention, and FIG.
It is explanatory drawing which shows the specific example of embodiment.

In the simulation model generation method of the second embodiment, circuit information designed in Verilog HDL is input, and a test bench for parallel simulation of Verilog HDL having a data-compressed text-format test pattern file is generated.

As shown in FIG. 3, the simulation test bench generation method of the second embodiment generates a test bench having a data-compressed test pattern file for a digital LSI circuit having a plurality of input signal lines.

In FIG. 3, in step 20, a test pattern to be input to each input signal line is generated for each simulation. In step 21, the test pattern generated in step 20 is input to all input signal lines for each simulation. Those having the same timing are joined by bit connection. Then, data compression is performed to generate one test pattern file. In step 22, the test pattern file generated in step 21 is read into the memory for each simulation, and the test pattern is bit-distributed to generate a test bench to be input to the corresponding input signal line.

When performing two parallel simulations on a digital LSI circuit having four 1-bit input signal lines, a specific example shown in FIG. 4 for generating a test bench having a data-compressed test pattern file is shown in FIG. This will be described with reference to the flowchart of FIG.

That is, in step 20, the first simulation test pattern 140 of the input signal line (in0) 110, the first simulation test pattern 141 of the input signal line (in1) 111, and the input signal line (i)
n2) 112 of the first simulation test pattern 142, the input signal line (in3) 113 of the first simulation test pattern 143, and the input signal line (in
0) 110 second simulation test pattern 1
50, the second simulation test pattern 151 of the input signal line (in1) 111, the input signal line (in2) 1
Twelve second simulation test patterns 152,
A second simulation test pattern 153 for the input signal line (in3) 113 is generated.

In step 21, the input signal line (in
0) First simulation test pattern 1 of 110
From 40, the first simulation test pattern 143 of the input signal line (in3) 113 is bit-connected to form a test pattern 144. Then, the first simulation test pattern file 145 is generated by compressing the test pattern 144 into data in hexadecimal notation and converting it into a file. Similarly, the input signal line (in
0) 110 second simulation test pattern 1
From 50, the second simulation test pattern 153 of the input signal line (in3) 113 is bit-connected to form a test pattern 154. Then, the test pattern 154 is expressed in hexadecimal notation, and the data is compressed and filed to generate a second simulation test pattern file 155.

At step 22, the first simulation test pattern file 145 and the second simulation test pattern file 155 are
n [3: 0] 114 as a test pattern,
The circuit block 1 is distributed to four 1-bit input signals from the input signal lines (in0) 110 to (in3) 113.
Generate a test bench to input to 00.

As described above, by concatenating the test patterns and compressing the data into a file, the occupation amount of the test patterns in the recording medium during the parallel simulation can be reduced.

FIG. 5 is a block diagram for explaining an embodiment of a simulation test bench generation apparatus according to the present invention. In this embodiment, circuit information designed in Verilog HDL is input and a data compressed text format is used. Verilog HDL with test pattern file
Is to generate a test bench.

As shown in FIG. 5, the simulation test bench generation device is roughly divided into test pattern generation means 30 for each input signal line, test pattern file generation means 40 for compressing test patterns, and simulation test bench generation means. 50.

Then, the test pattern generating means 30
The test pattern information 31 of each input signal line is generated based on the circuit information 61.

The test pattern file generating means 40
Based on the test pattern information 31 and the test pattern file generation information 62, a test pattern is input to at least two or more input signal lines at the same input timing by bit concatenation to form a data compressed text format or binary format. Of the test pattern file information 41 is generated.

The test bench generation means 50 generates a test bench 51 based on the test bench generation conditions 60 and the simulator information 70.

Here, the test bench generation condition 60 includes circuit information 61 which is information of a circuit to be simulated,
It is composed of test pattern file generation information 62 which is information for compressing a test pattern to generate a test pattern file, simulator selection information 63 for performing a simulation, and simulation condition information 64 such as simulation time and probe settings. .
When there are a plurality of simulators for performing a simulation, the simulator information 70 includes command information specific to each simulator.
1. Simulator (2) Command information 72 is provided for each simulator.

With such a configuration, the test pattern can be data-compressed and the test bench corresponding to the simulator can be automatically generated as in the simulation test bench generation method, and the test bench generation efficiency can be improved. it can.

[0035]

As described above, according to the present invention,
When simulating the circuit operation using a software simulator, a simulation test that can reduce the data occupancy of the test pattern file in the recording medium by using a test bench that compresses the bit-connected test pattern data and creates a file A bench generation method and a simulation test bench generation device can be provided.

[Brief description of the drawings]

FIG. 1 is a flowchart of a simulation model generation method for explaining a first embodiment of a simulation test bench generation method of the present invention.

FIG. 2 is an explanatory diagram showing a specific example of the first embodiment of the present invention.

FIG. 3 is a flowchart of a simulation model generation method for explaining a simulation test bench generation method according to a second embodiment of the present invention;

FIG. 4 is an explanatory diagram showing a specific example of the second embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating an embodiment of a simulation test bench generation device according to the present invention.

FIG. 6 is a flowchart of a conventional simulation test bench generation method.

FIG. 7 is an explanatory diagram showing a specific example of the generation method in FIG. 6;

[Explanation of symbols]

Reference Signs List 30 test pattern generation means 31 test pattern information 40 test pattern file generation means 41 test pattern file information 50 test bench generation means 51 test bench 60 test bench generation conditions 61 circuit information 62 test pattern file generation information 63 simulator selection information 64 simulation condition information 70 Simulator information 71 Simulator (1) command information 72 Simulator (2) command information 100 Circuit block 110 to 113 Input signal line 114 Signal line in [3: 0] 120 to 123 Test pattern file 130 to 134 Test pattern 134 All input signals Line test pattern 135 Test pattern files 140 to 143 for all input signal lines Test pattern 1 for input signal lines for first simulation 4 Test Pattern of All Input Signal Lines of First Simulation 145 Test Pattern File of All Input Signal Lines of First Simulation 150 to 153 Test Pattern of Input Signal Line of Second Simulation 154 All Input Signals of Second Simulation Line test pattern 155 Test pattern file for all input signal lines of the second simulation

Continued on the front page F term (reference) 2G032 AA07 AB01 AC04 AC08 AC09 AD05 AG02 AG04 AG10 AK01 AK02 AK14 5B046 AA08 BA09 JA04

Claims (3)

[Claims] 1. A method for generating a simulation test bench for a digital LSI circuit having at least two or more input signal lines, wherein a first test pattern is generated for each input signal line in the digital LSI circuit. And the test pattern is at least 2
A second step of connecting the same input timing to more than one input signal line by bit concatenation to generate a data-compressed text-format or binary-format test pattern file; and storing the test pattern file in a memory. And a third step of distributing the test pattern into bits for each corresponding input signal line and generating an input operation description. 2. A method for generating a simulation test bench for performing a parallel simulation of a digital LSI circuit having at least two or more input signal lines, wherein a test pattern of an input signal line of the digital LSI circuit is generated for each simulation. The first step generated for each input signal line and the test pattern required for one simulation are connected to all input signal lines at the same input timing by bit concatenation, and the data is compressed text. Generating a test pattern file as a test pattern file in a binary or binary format, reading the test pattern file into a memory for each simulation, distributing bits for the test pattern for each corresponding input signal line, and generating an operation description to be input Third
A method for generating a simulation test bench, comprising the steps of: 3. An apparatus for generating a simulation test bench for simulating a digital LSI circuit having at least two or more input signal lines, comprising: means for generating a test pattern for each signal line; For at least two or more input signal lines,
It comprises means for joining the same input timing by bit concatenation and generating a data-compressed text-format or binary-format test pattern file, and means for generating a test bench using the test pattern file. Characteristic simulation test bench generation device.