JP2000020153A - Constant voltage circuit - Google Patents

Abstract

(57) [Problem] To provide a constant voltage circuit capable of realizing high-precision constant voltage output by compensating for temperature dependency of an output constant voltage, while making both differential pair transistors the same size and the same shape. provide. A constant voltage circuit includes a reference voltage source 14 connected, the reference voltage V _ref of the reference voltage source 14 generates is supplied to the non-inverting input terminal 17 between input terminal 11 and the GND terminal 12 The differential amplifier circuit 15 includes a differential amplifier circuit 15 and a constant voltage output unit 19 to which an output of the differential amplifier circuit 15 is input and which outputs an output to an inverting input terminal 18 of the differential amplifier circuit 15. The differential amplifier circuit 15 includes a differential amplifier and a current mirror circuit for transmitting the output of the differential amplifier. The current mirror circuit includes a diode D1 that applies an offset voltage to the differential amplifier in response to a temperature change. Have.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a constant voltage circuit, and more particularly, to a constant voltage circuit formed on a MOS integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a constant voltage circuit, a bandgap reference circuit constituted by using a bipolar transistor has been generally used, but a constant voltage circuit constituted by using a MOS transistor is also known. . MOS
Transistors have large manufacturing deviations and their temperature characteristics are non-linear, unlike bipolar transistors.
In a MOS type constant voltage circuit, how to compensate for these effects becomes a problem.

FIG. 6 is a circuit diagram showing a conventional constant voltage circuit formed on a MOS integrated circuit. The constant voltage circuit includes a reference voltage source 24 connected between the power supply terminal 21 and the GND terminal 22 and an output of the reference voltage source 24 connected to the non-inverting input terminal 27.
In addition, a constant voltage output section 29 and a differential amplifier circuit 25 having a constant voltage output negative feedback input connected to an inverting input terminal 28 are provided. The constant voltage output unit 29 includes a pass transistor M1 composed of a PchMOS transistor having a drain connected to the power supply terminal 21, a gate connected to the output 26 of the differential amplifier circuit 25, and a source connected to the output terminal 23;
Split resistors R1 and R2 connected in series with the terminal 22
And A connection node between the split resistors R1 and R2 is negatively fed back to the inverting input terminal 28 of the differential amplifier circuit 25.

The differential amplifier circuit 25 has a differential amplifier and a current mirror circuit. The differential amplifier has a constant current source Io1 having one end connected to the power supply terminal 21 and a source other than the constant current source Io1. Non-inverting input terminal 2
7 and a PchMOS transistor M3 whose source is connected to the other end of the constant current source Io1 and whose gate is connected to the inverting input terminal 28. PchMOS transistors M2 and M3 forming a differential pair have the same size and the same shape. The differential amplifier further includes an NchMOS transistor M having a drain and a gate commonly connected to the source of the PchMOS transistor M2 and a source grounded.
4 and an NchMOS transistor M5 whose drain and gate are commonly connected to the source of the PchMOS transistor M3 and whose source is grounded.

The current mirror circuit comprises NchMOS transistors M6 and M7 forming first and second current mirrors respectively from NchMOS transistors M4 and M5;
And PchMOS transistors M8 and M9 forming a current mirror of The gate of the NchMOS transistor M4 is connected to the gate of the NchMOS transistor M6 whose drain is connected to the drain of the PchMOS transistor M8 and whose source is connected to the GND terminal 22. The drain is output to the gate of the NchMOS transistor M5 (amplifier output)
26 connected to GND terminal 22 and connected to GND terminal 22
The gate of the chMOS transistor M7 is connected. Also,
The power supply terminal 21 and the drain of the NchMOS transistor M6 are connected to the source and drain of a PchMOS transistor M8 whose gate and drain are connected to each other.
The power supply terminal 21 and the output 26 have a gate connected to the gate of the PchMOS transistor M8.
9 are connected to the source and the drain, respectively.

The output constant voltage V of the above-mentioned conventional constant voltage circuit
_OUT is a reference voltage _Vref which is an output of the reference voltage source 24;
It is given by the following equation (1) using the divided resistors R1 and R2. V _OUT = V _ref × ｛(R1 + R2) / R1｝ (1) Therefore, the temperature characteristic of the output constant voltage V _OUT is as follows: ∂V _OUT / ∂T = (∂V _ref / ∂T) × ｛(R1 + R2) /R1｝...(2)

Normally, in order to compensate for the temperature dependency of the output constant voltage V _OUT, a band gap reference circuit having a small temperature dependency (∂V _ref / ∂T) of the reference voltage Vref is used as the reference voltage source 24. However, actually, even in this case, the output of the constant voltage circuit often has a temperature characteristic of about (+100 μV / ° C.). That is, (2) from _{equation, ∂V OUT / ∂T = (+} 100μ / ℃) × {(R1 + R2) / R1} ...... (3) , and the considerable temperature dependence on the output constant voltage V _OUT of the constant voltage circuit There is.

A constant voltage circuit for compensating the above-mentioned temperature dependence has been proposed, for example, in Japanese Patent Laid-Open No. 5-143181.
FIG. 7 is a circuit diagram showing a constant voltage circuit described in this publication. In the figure, circuit elements having the same functions as those of the constant voltage circuit of FIG. 6 are denoted by the same reference numerals.

The constant voltage circuit includes a reference voltage source 24, a differential amplifier circuit 35, and a constant voltage output unit 39 including a pass transistor M1, a split resistor R1 and a split resistor R2.
The differential amplifier circuit 35 includes an active load including NchMOS transistors M20 and M21 forming a differential pair, a constant current source Io2, and PchMOS transistors M22 and M23 forming a current mirror, a transistor M24 including an NchMOS transistor and a constant load. A level shift circuit including a current source Io3. The differential amplifier circuit 35 further includes a power supply terminal 21
A PchMOS transistor M25 and an NchMOS transistor M26 connected in series with the GND terminal 22, a resistor R3 having one terminal connected to a connection node of each current path of the transistors M25 and M26, and the other terminal of the resistor R3. PchM
A capacitor C1 connected to the gate of the OS transistor M25.

Here, the differential pair transistors M20, M2
1, the ratio of the gate width to the gate length is 1: K1, and the differential pair transistors M22 and M23 forming an active load
The ratio between the gate width and the gate length in both cases is set to 1: K2, and the input offset voltage Vos is given to the differential pair.

According to the above publication, the following equation is obtained: dV _OUT / dT = (1 + R5 / R4) (dV _REF / dT + dV _OS / dT) (where, V _OUT : constant output voltage, T: absolute temperature, V _REF : reference voltage) ) Holds. The temperature characteristic of the output constant voltage V _OUT is given by the following equation: ΔV _OUT / ΔT = (ΔV _ref / ΔT + ΔVos / ΔT) × {(R1 + R2) / R1} (4) Vos is expressed by the following equation Vos = 1 / (μ _n ) ^0.5 × (2I _o1 / C _ox ) ^0.5 × 1 / (W / L) ₁ ^0.5 × ｛K ₂ /
From (K ₂ +1)｝ ^0.5 × ｛1-1 / (K ₁・ K ₂ ) ^0.5 Vo, Vos = (Io2 / β1) ^0.5 × ｛K2 / (K2 + 1)｝ ^0.5 × ｛1-1 / (K1 ・K2)｝ ^0.5 is given by (5).

Further, Vos = (2I _o1 / C _ox ) ^0.5 × 1 / (W / L) ₁ ^0.5 × {K ₂ / (K ₂ +1)} ^0.5
× ｛1-1 / (K ₁・ K ₂ ) ^0.5 ｝ × ｛1 / (μ _n (T ₀ )) ^0.5 ｝ × (T / T ₀ )
^3/4 dVos / dT ≒ ^3/4 × (1 / T ₀ ) × (2I _o1 / C _ox ) ^0.5 × 1 / (W / L) ₁ ^0.5 ×
｛K ₂ / (K ₂ +1)｝ ^0.5 × ｛1-1 / (K ₁・ K ₂ ) ^0.5 ｝ × ｛1 / (μ
_n (T ₀ )) ^0.5 、, Vos = (∂Vos / ∂T) × (4/3) × T0 × (T / T0) ^-3/4 (6) (where β1: differential pair (T0: absolute temperature at normal temperature, T: absolute temperature at a certain time).

Here, assuming that a band gap reference circuit is used as a reference voltage source, +100 μm
In order to eliminate the temperature characteristic of V / ° C., ΔVos / ΔT = −100 [μV / ° C.] is required from the equation (4). When the input offset voltage Vos of the differential pair M20 and M21 at T = T0 = 300K (normal temperature) is calculated from the equation (6), Vos (Ta = 25 ° C.) = 40 [mV].

Here, using a process in which the conductivity coefficient β1 is 50 μA / V ² , ² μA is supplied to the constant current source Io2 shown in FIG. 7, and PchMOS transistors M22 and M23 as active loads are applied.
Assuming that the ratio between the gate width and the gate length of the transistor M1 is 1: K2 = 1: 1, the gate length L of the transistor M20 is 2 μm, and the gate width W of the transistor M21 is 5 μm, Vos (Ta =
(25 ° C.) = 40 [mV] According to the equation (5), the gate length and the gate width of the transistor M21 forming a differential pair with the transistor M20 are as follows: gate length L = 2 [μm] gate width W = 5 × 2.14 [μm]

[0015]

However, in the current manufacturing process, the differential pair transistors M20 and M21 are not made symmetrical, the element size is not made the same size and the same shape, and the gate length L of M20 is reduced to M21. Gate length L = 1: 1 M20 gate width W: M21 gate width W = 1: 2.1
4, it is difficult to accurately maintain Vos = 40 [mV]. That is, the technique that compensates for this temperature dependency is not suitable for temperature compensation of a high-precision constant voltage circuit using a band gap as a reference voltage source.

In view of the above, it is an object of the present invention to provide a high-precision constant-voltage output by compensating for the temperature dependence of an output constant voltage while making both differential pair transistors the same size and the same shape. It is intended to provide a circuit.

[0017]

In order to achieve the above object, a constant voltage circuit according to the present invention comprises: a reference voltage generating circuit connected between a first power supply and a second power supply; A differential amplifier circuit to which a reference voltage generated by the generator circuit is supplied to a non-inverting input terminal; and a constant voltage output to which an output of the differential amplifier circuit is input and an output is fed back to an inverting input terminal of the differential amplifier circuit. And a constant voltage circuit comprising a unit, wherein the differential amplifier circuit includes a differential amplifier and a current mirror circuit that transmits an output of the differential amplifier, and the current mirror circuit includes:
It is characterized by including a leak current means for applying an offset voltage to the differential amplifier in response to a temperature change.

In the constant voltage circuit according to the present invention, the leak current means causes a negligible leak current to flow at room temperature and increases the leak current to a non-negligible level at a high temperature, so that the temperature of the input offset of the differential amplifier circuit is reduced. Dependencies can be provided. For this reason, it is possible to realize high-precision constant-voltage output by compensating for the temperature dependence of the output constant voltage while making both the differential pair transistors the same size and the same shape.

Here, the differential amplifier circuit includes first and second differential amplifier circuits.
A differential pair of PchMOS transistors, wherein each gate and each drain are commonly connected to each drain of the first and second PchMOS transistors between the differential pair and the second power supply; First and second NchMOS transistors connected to the second power supply are provided, and the first and second NchMOS transistors are provided.
A third PchMOS transistor and a third NchMOS transistor connected in series are inserted in this order between the second power supply and the second power supply, and a fourth PchM transistor connected in series with each other is provided.
An OS transistor and a fourth NchMOS transistor are inserted in this order, a gate and a drain of the third PchMOS transistor are commonly connected to a drain of the third NchMOS transistor, and a gate of the third PchMOS transistor is connected to a gate of the fourth PchMOS transistor. Preferably they are connected.

Further, it is preferable that the leak current means comprises a diode having a cathode connected to the first power supply and an anode connected to the gate of the third PchMOS transistor. Thereby, the first and second Pc forming a differential pair
While both the hMOS transistors have the same size and the same shape, the temperature dependency of the output constant voltage can be compensated only by connecting the diode to a predetermined position.

Alternatively, it is preferable that, instead of the above, the leak current means comprises a fifth PchMOS transistor whose source is connected to the first power supply and whose drain and gate are commonly connected to the gate of the third PchMOS transistor. It is an aspect. Thus, the area required for the leakage current means on the MOS integrated circuit can be reduced.

Also, the gate of the third NchMOS transistor is connected to the gate of the first NchMOS transistor, the source is connected to the second power supply, respectively, and the fourth NchMOS transistor is connected to the second power supply.
It is preferable that a gate of the transistor is connected to a gate of the second NchMOS transistor, and a gate is connected to the second power supply.

In a preferred embodiment, the leak current means comprises a diode having an anode connected to the second power supply and a cathode connected to the gate of the fourth NchMOS transistor. Thus, the temperature dependency of the output constant voltage can be compensated for by simply connecting the diode to a predetermined position while making both the PchMOS transistors M2 and M3 forming the differential pair the same size and the same shape.

Alternatively, instead of the above, it is preferable that the leak current means comprises a fifth PchMOS transistor whose source is connected to the gate of the fourth NchMOS transistor and whose drain and gate are commonly connected to the second power supply. It is an aspect. Thus, the area required for the leakage current means on the MOS integrated circuit can be reduced.

[0025]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a circuit diagram showing a constant voltage circuit according to the first embodiment of the present invention. The constant voltage circuit includes a reference voltage source 1 connected between the power supply terminal 11 and the GND terminal 12.
4 and the output of the reference voltage source 14
A constant voltage output section 19 is provided with a differential amplifier circuit 15 whose negative feedback input of a constant voltage output is connected to an inverting input terminal 18 respectively.

The constant voltage output section 19 has a drain connected to the power supply terminal 11 and a gate connected to the output 16 of the differential amplifier circuit 15.
PchMOS whose source is connected to the output terminal 13
It includes a pass transistor M1 composed of a transistor, and divided resistors R1 and R2 connected in series between the output terminal 13 and the GND terminal 12. The pass transistor M1 is a voltage passing element, and the divided resistors R1 and R2 constitute a resistance voltage dividing circuit located between the source of the pass transistor M1 and the GND terminal 12. The connection node between the divided resistors R1 and R2 is negatively fed back to the inverting input terminal 18 of the differential amplifier circuit 15.

The differential amplifier circuit 15 has a differential amplifier and a current mirror circuit. The differential amplifier has a constant current source Io1 whose one end is connected to the power supply terminal 11, and a source other than the constant current source Io1. Non-inverting input terminal 1
7, and a PchMOS transistor M3 whose source is connected to the other end of the constant current source Io1 and whose gate is connected to the inverting input terminal 18. The PchMOS transistors M2 and M3 forming the differential pair have the same size and the same shape. The PchMOS transistor M2 receives the reference voltage _Vref generated by the reference voltage source 14, and the PchMOS transistor M3 receives the divided resistors R1 and R2. The constant voltage output V _OUT of the constant voltage output unit 19 divided by the above is applied respectively.
The differential amplifier further includes an NchMOS transistor M4 having a drain and a gate commonly connected to the source of the PchMOS transistor M2 and a source connected to the GND terminal 12, a drain and a gate commonly connected to the source of the PchMOS transistor M3, and a source connected to the NchMOS transistor M3. NchMOS connected to GND terminal 12
And a transistor M5. NchMOS transistor M4
And M5 have their gates and drains connected, respectively.

The current mirror circuit includes NchMOS transistors M6 and M7 respectively forming first and second current mirrors from NchMOS transistors M4 and M5;
And PchMOS transistors M8 and M9 forming a current mirror of The drain of the gate of the NchMOS transistor M4 is connected to the drain of the PchMOS transistor M8.
The gates of the NchMOS transistors M6 whose sources are connected to the GND terminal 12, respectively, are connected. NchMOS transistor M
The drain of the gate 5 is an output (amplifier output) 16
Is connected to the gate of the NchMOS transistor M7 whose source is connected to the GND terminal 12, respectively.

A PchMOS transistor M8 inserted between the power supply terminal 11 and the drain of the NchMOS transistor M6
Has a source connected to the power supply terminal 11, a gate and a drain commonly connected to the drain of the NchMOS transistor M6. A PchMOS is provided between the power supply terminal 11 and the output 16.
A transistor M9 is provided. PchMOS transistor M
Reference numeral 9 denotes a source connected to the power supply terminal 11, a drain connected to the output 16, and a gate connected to the gate of the PchMOS transistor M8.

A diode D1 is inserted between the power supply terminal 11 and the gate of the PchMOS transistor M8.
The diode D1 has a cathode connected to the power supply terminal 11, an anode connected to the gate of the PchMOS transistor M8, and a reverse voltage applied.

FIG. 2 is a graph showing the measured results of the temperature characteristics of the leakage current when the diode is reverse biased in the embodiment. The vertical axis in the graph indicates the change in the leak current Ileak, and the horizontal axis indicates the temperature change. In the constant voltage circuit, PchMOS transistors M2 and M
3 are mutually symmetrical, mutually the same size and the same shape. At normal temperature, the leakage current in the diode D1 can be ignored, so that the input offset voltage Vos of the differential amplifier circuit 15 at normal temperature (Ta = 25 ° C.)
And Vos (Ta = 25 ° C.) ≒ 0 (7)

However, at a high temperature, as can be seen from the graph, the leakage current Ileak of the diode D1 increases,
The value cannot be ignored. In this case, Ids (M2) = (1/2) · (I0 + Ileak) (8) Ids (M3) = (1/2) · (I0−Ileak) (9) Vgs (M2) = [｛ 2 · Ids (M2) · L｝ / (β · W)] ^0.5 + VT… (10) Vgs (M3) = [{2 · Ids (M3) · L} / (β · W)] ^0.5 + VT …… (11) Here, Ids (M2): drain-source current of M2, Ids (M3): drain-source current of M3, Io: constant current of constant current source Io1, Vgs (M2): gate-source voltage of M2 , Vgs (M3): Gate-source voltage of M3, L: M
2, M3 gate length, W: M2, M3 gate width, β: M2, M3
, VT: threshold voltage of M2, M3.

From equations (8) to (11), the following equation (12) is obtained.
A high-temperature input offset Vos (T: high temperature) occurs as shown in FIG. Vos (T: at high temperature) = Vgs (M2) −Vgs (M3) = {2Ids (M2) −2Ids (M3)} ^0.5 × (L / W · β) ^0.5 = ｛[I0 + Ileak] ^0.5 − [I0−Ileak ] ^0.5 ｝ × ｛L / (W · β)｝ ^0.5 …… (12)

From the equations (7) and (12), the temperature characteristic of the input offset is as follows: ∂Vos / ∂T = − ｛[I0 + Ileak] ^0.5- [I0-Ileak] ^0.5 ｝ × ｛L / (W · K)｝ ^0.5 / ΔT (13)

The temperature characteristic of the output constant voltage V _OUT of the constant voltage circuit is given by the following equation (2): ∂V _OUT / ∂T = (∂V _ref / ∂T) × ｛(R1 + R2) / R1｝ 2) Since there is an input offset at high temperature for
(14). ∂V _OUT / ∂T = (∂V _ref / ∂T + ∂Vos / ∂T) × ｛(R1 + R2) / R1｝ …… (14) Therefore, ∂Vos / ∂T = −∂V _ref / ∂T If ∂Vos / ∂T is determined so as to satisfy (15), a constant voltage circuit in which the output constant voltage _VOUT has no temperature dependency can be realized.

Hereinafter, a specific description will be given using numerical values. As a reference voltage source, as in the conventional example, ΔV _ref / ΔT = + 10
When a bandgap reference circuit of 0 [μV / ° C.] is used, in order to realize a high-precision power supply having no temperature dependency in the output constant voltage V _OUT , it is necessary to obtain ΔVos / ΔT = −100 [μV / ° C.] (16)

Here, suppose that a constant current: IO = 1 [μA] is applied to Io1 using a process of β = 20 [μA / V ² ], and the gate length L of each of the differential pair transistors M2 and M3 is 2 μm.
m, each gate width W is 10 μm, and when the high temperature is 150 ° C., from the expression (13), ∂Vos / ∂T = 100 × ｛(1μ + Ileak) ^0.5- (1μ-Ileak) ^0.5 ｝ / 125 [V / ° C.] (17) In order to satisfy the expression (16), Ileak (150 ° C.) = 125 [nA] is obtained from the expression (17).

As described above, according to the constant voltage circuit of this embodiment, the diode D1 whose value increases at high temperatures
, The offset can be provided between the differential pair transistors M2 and M3 when the temperature is higher than a predetermined temperature. For example, when the current on the PchMOS transistor M2 side increases due to a change in the reference voltage _Vref of the reference voltage source 14 at a high temperature, the PchMOS transistors M8 and Nc
Since the current flows to the hMOS transistor M6, the fluctuation on the PchMOS transistor M2 is absorbed. For this reason, the variation of the differential amplifier circuit due to the temperature variation of the reference voltage _Vref is reduced, and the constant voltage is output from the output terminal 13 with high accuracy.

The graph shown in FIG. 2 is 10 μm × 10
It is an actual measurement result of a temperature characteristic of a diode leak current Ileak when a reverse bias of 1 V is applied between an anode and a cathode of 10 μm (hereinafter referred to as 10 μ □). The graph shows that Ileak (150 ° C.) = 10 nA / 10 μ □. Ileak is proportional to area. Therefore, if the area of the diode D1 in FIG. 1 is 50 × 25 [μm ² ], the expression (16) is satisfied, and the output constant voltage has no temperature dependency.

Next, a constant voltage circuit according to a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of the constant voltage circuit according to the present embodiment.

In this embodiment, a diode-connected PchM is used instead of the diode D1 in the first embodiment.
The OS transistor M10 (active load) is provided, and as a result, the area is reduced. The source of the PchMOS transistor M10 is connected to the power supply terminal 11, and the drain and the gate are commonly connected to the gate of the PchMOS transistor M8. In the present embodiment, the circuit elements other than the PchMOS transistor M10 and the connection state are the same as those of the first embodiment, and the same elements are denoted by the same reference numerals and description thereof will be omitted.

Hereinafter, a specific description will be given using numerical values. FIG. 4 shows a Pc having a gate length L of 10 μm and a gate width W of 2 μm.
FIG. 9 is a graph showing actual measurement results of temperature characteristics of current Iweak when a weak inversion operation is performed by biasing 1 V between a gate and a source of an hMOS transistor.

The vertical axis in the graph indicates the change in the current Iweak,
The horizontal axis indicates the temperature change. From the graph, Iweak 150
[° C.] = 100 [nA] can be understood. Since the current Iweak is proportional to the area, the expression (16) is satisfied and the output constant voltage V _OUT
In order to eliminate the temperature dependency, the size of the PchMOS transistor M10 may be set to L = 10 μm and W = 2.5 μm. As described above, according to the active element (M10) in the present embodiment, the size (50 × 25 [μm ² ]) of the diode D1 in the first embodiment is
The area can be significantly reduced.

Next, a third embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a configuration of the constant voltage circuit according to the present embodiment. In the present embodiment, the diode D1 in the first embodiment is eliminated, and the diode D1 is connected between the gate of the NchMOS transistor M7 and the GND terminal 12.
This is an example in which 2 is inserted. In the present embodiment, since the elements other than the diode D2 and the connection state are the same as those of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is omitted.

The diode D2 has a cathode connected to each gate of the NchMOS transistors M7 and M5, and an anode connected to the GND terminal 12. In both the first and second embodiments, the case where ∂V _ref / ∂T (temperature fluctuation) is positive is dealt with, but in the present embodiment, when ∂V _ref / ∂T is negative, the constant Temperature dependence can be eliminated from the output constant voltage V _OUT of the voltage circuit.

As described above, even with the constant voltage circuit of this embodiment, the input offset of the differential amplifier circuit 15 has temperature dependency by utilizing the leakage current of the diode D2 whose value increases at high temperatures. Can be made. Thereby, the temperature dependency of the reference voltage source output can be reduced, and the temperature dependency of the output constant voltage can be compensated.

The diode D according to the present embodiment is
The same effect can be obtained by using a diode-connected PchMOS transistor like the PchMOS transistor M10 in the second embodiment in place of 2. In this case, the source of the PchMOS transistor is commonly connected to the gates of the NchMOS transistors M5 and M7, and the drain and the gate are commonly connected to the GND terminal 12.

Although the present invention has been described based on the preferred embodiment, the constant voltage circuit of the present invention is not limited to the configuration of the above-described embodiment, but rather the configuration of the above-described embodiment. Various modifications and changes of the constant voltage circuit are also included in the scope of the present invention.

[0049]

As described above, the constant voltage circuit of the present invention compensates for the temperature dependency of the output constant voltage while providing both differential pair transistors of the same size and the same shape, thereby achieving high precision. A constant voltage output can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a constant voltage circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing actual measurement results of leak current temperature characteristics at the time of diode reverse bias in the first embodiment.

FIG. 3 is a circuit diagram showing a configuration of a constant voltage circuit according to a second embodiment of the present invention.

FIG. 4 is a graph showing actual measurement results of temperature characteristics of a weak inversion current of a PchMOS transistor according to a second embodiment.

FIG. 5 is a circuit diagram showing a configuration of a constant voltage circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a conventional constant voltage circuit.

FIG. 7 is a circuit diagram showing another configuration example of a conventional constant voltage circuit.

[Explanation of symbols]

 11: Power supply terminal 12: GND terminal 13: Output terminal 14: Reference voltage source 15: Differential amplifier circuit 16: Output 17: Non-inverting input terminal 18: Inverting input terminal D1, D2: Diode Io1: Constant current source M1: Pass Transistors M2, M3, M8, M9, M10: PchMOS transistors M4 to M7: NchMOS transistors R1, R2: split resistors

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AV04 AZ08 BB04 BB05 EZ20 5H420 NA31 NB02 NB22 NB25 NC02 NC03 NE23 5H430 BB05 BB09 BB11 EE04 HH03 LA21

Claims (7)

[Claims] 1. A reference voltage generation circuit connected between a first power supply and a second power supply, and a differential amplifier circuit to which a reference voltage generated by the reference voltage generation circuit is supplied to a non-inverting input terminal. And a constant voltage output unit to which an output of the differential amplifier circuit is input and for feeding back an output to an inverting input terminal of the differential amplifier circuit, wherein the differential amplifier circuit includes a differential amplifier. And a current mirror circuit for transmitting an output of the differential amplifier, wherein the current mirror circuit includes a leak current means for applying an offset voltage to the differential amplifier in response to a temperature change. circuit. 2. The differential amplifier has a differential pair composed of first and second PchMOS transistors, and each drain of the first and second PchMOS transistors is provided between the differential pair and the second power supply. A first and a second NchMOS transistor, each having a gate and a drain connected in common and a source connected to the second power supply, are disposed between the first and second power supplies; A third PchMOS transistor and a third NchMOS transistor connected in series are inserted in this order, and a fourth PchMOS transistor and a fourth NchMOS transistor connected in series are inserted in this order. The gate and drain of the third PchMOS transistor are Commonly connected to the drain of the third NchMOS transistor,
The gate of the third PchMOS transistor is connected to the fourth PchMOS transistor.
2. The constant voltage circuit according to claim 1, wherein the constant voltage circuit is connected to a gate of the PchMOS transistor. 3. The constant voltage circuit according to claim 2, wherein said leakage current means comprises a diode having a cathode connected to said first power supply and an anode connected to the gate of said third PchMOS transistor. . 4. The leak current means has a source connected to the first power supply and a drain and a gate connected to the third Pc.
Fifth PchMOS commonly connected to the gate of the hMOS transistor
3. The constant voltage circuit according to claim 2, comprising a transistor. 5. The third NchMOS transistor has a gate connected to the gate of the first NchMOS transistor, a source connected to the second power supply, and a gate of the fourth NchMOS transistor connected to a gate of the second NchMOS transistor. 3. The constant voltage circuit according to claim 2, wherein each of said constant voltage circuits is connected to said second power supply. 6. The constant voltage circuit according to claim 5, wherein said leak current means comprises a diode having an anode connected to said second power supply and a cathode connected to the gate of said fourth NchMOS transistor. . 7. The fifth PchMOS having a source connected to the gate of the fourth NchMOS transistor and a drain and a gate commonly connected to the second power supply.
6. The constant voltage circuit according to claim 5, comprising a transistor.