JP2000012836A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate filed-effect transistor, which has good switching characteristic and a high current drive power. SOLUTION: A semiconductor device is constituted into a structure, wherein high concentration impurity implanted regions (source and drain diffused layers 28 and 29) of an insulated gate field-effect transistor 1 are formed in a semiconductor substrate 11, and thereafter impurity implanted regions (a first impurity implanted region 31 and second impurity implanted regions 34) for contributing to the switching characteristics of the transistor 1 are formed in the substrate 11. The region 31 is formed in the part, which is located directly under a gate electrode 22, of the substrate 11 and the regions 34 have concentration of the same degree as that of the region 31 and are respectively formed in the vicinity of the end part in the depth direction of each element isolation region 12, via each low concentration region 13 in the depth direction of the substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a characteristic in an impurity implantation region of an insulated gate field effect transistor and a method of manufacturing the semiconductor device.

[0002]

2. Description of the Related Art A MOS field effect transistor (hereinafter referred to as M
OSFETs) are miniaturized according to the so-called scaling law in the manufacture of semiconductor devices, and technically difficult problems arise. In other words, the short channel effect becomes significant as the device is miniaturized. In particular, in order to suppress the punch-through current from increasing, it is effective to form the source and drain diffusion layers shallowly and to increase the channel impurity concentration. However, since the channel impurity is usually implanted over the entire surface of the semiconductor substrate before the gate electrode is formed, the channel impurity is also implanted at a high concentration also in the vicinity of the junction region between the source and drain diffusion layers. As a result, the junction capacitance of the source and drain diffusion layers increases,
The current driving capability of the FET decreases.

Here, a process flow of a conventional channel impurity implantation method will be described with reference to manufacturing process diagrams shown in FIGS.

As shown in FIG. 8A, an element isolation region 112 made of an insulating film is formed on the surface of a semiconductor substrate 111 of a first conductivity type. Channel impurities made of, for example, impurities of the first conductivity type are implanted into the entire surface of the semiconductor substrate 111 of the first conductivity type separated by the element isolation region 112.
In the channel impurity implantation region 113, a low concentration region 114 is formed on the substrate surface side, and a high concentration region 11
5 are formed. As described above, at the time of channel impurity implantation, the high-concentration region 115 which is a high-concentration channel impurity implantation region for suppressing a short channel effect is formed, and the channel formation region on the surface of the semiconductor substrate 111 has a low impurity concentration. The low-concentration region 114 is maintained at a low concentration. Thereby, it is possible to suppress a decrease in mobility due to impurity scattering in the channel portion and to suppress generation of punch-through current. This steep channel impurity distribution can be achieved by performing ion implantation a plurality of times while changing the implantation energy and implantation amount.

[0005] As shown in FIG. 8 (2), a semiconductor substrate 111 of the first conductivity type separated by the element isolation region 112 is provided.
A gate electrode 122 is formed on the surface of the substrate through a gate insulating film 121 by a normal process. Thereafter, impurities of the second conductivity type are implanted into the semiconductor substrate 111 using the gate electrode 122 as a mask to form shallow source and drain regions 123 and 124. At that time, the above shallow sauce,
Crystal defects are introduced into the semiconductor substrate 111 by ion implantation for forming the drain regions 123 and 124.

[0008] Next, as shown in FIG. 8 C, a side wall spacer 125 is formed on the side wall of the gate electrode 122 to serve as a mask when ions are implanted into the semiconductor substrate 111. The left drawing of FIG. 8 (3) is smaller than the other drawings and is shown without hatching. At the time of the thermal process (CVD process) for forming the side wall spacers 125, channel impurities are diffused and redistributed. Since the diffusion at this time is accelerated by crystal defects, channel impurities are re-emitted in the direction of diffusion of the defects (substrate surface, in the substrate (depth direction), source and drain regions) indicated by arrows in the enlarged view. Distribute. As a result, the impurity concentration of the channel forming region 131 immediately below the gate electrode 122 (substrate surface) increases, and the concentration of the high-concentration region 115, which has been heavily doped to suppress punch-through current, decreases. become.

Next, as shown in FIG. 9D, a second conductivity type impurity is implanted into the semiconductor substrate 111 using the gate electrode 122 and the side wall spacer 125 as a mask, and the shallow source region 123 is inserted through the gate electrode 122 side. In addition to forming a deep source region 126, a shallow drain region 124 is formed on the side of the gate electrode 122 to form a deep drain region 127. In addition, a crystal defect is also formed at this time.

[0009] Thereafter, as shown in FIG. 9 (5), an activation heat treatment is performed to form a source diffusion layer 128 by the shallow source region 123 and the deep source region 126, and to form the shallow drain region 124 and the deep drain The drain diffusion layer 129 is formed with the region 127. At that time, the channel impurity causes further redistribution. Finally, as shown in FIG. 9 (5), the gate electrode 122 which is a channel formation region
The impurity concentration immediately below (substrate surface) is further increased to form a high-concentration region 131, and the impurity concentration in a slightly deeper region (region through which a punch-through current flows) decreases. Therefore, if the entire substrate impurity concentration is set high in order to suppress the punch-through current, the current driving capability is significantly reduced. At this time, the substrate concentration near the junction between the source / drain diffusion layers 128 and 129 also increases, so that the junction capacitance increases and the element characteristics further deteriorate.

To solve the problem of reducing the junction capacitance of the source and drain diffusion layers, the means is, for example, disclosed in
-43787, JP-A-62-141778, JP-A-8-213600, and the like.

Japanese Patent Publication No. 3-43787 discloses that a high concentration channel impurity is implanted only into a channel region by using a photolithography process to prevent a junction capacitance between a source / drain diffusion layer and a substrate from increasing. Is disclosed. That is, the substrate concentration in the channel region is increased to suppress the punch-through current, but the junction concentration of the source and drain diffusion layers is not increased so that the substrate concentration below the source and drain diffusion layers is prevented from increasing. I have.

Japanese Patent Application Laid-Open No. 62-141778 discloses that high-concentration channel impurities are implanted over the entire surface of a semiconductor substrate, and then the source and drain diffusion layers and the semiconductor substrate are formed only below the source and drain diffusion layers. It is disclosed that a semiconductor layer having an impurity concentration intermediate between these two is formed to reduce the junction capacitance of the source / drain diffusion layers.
Specifically, high-concentration channel impurity implantation is performed on the entire surface of the semiconductor substrate. A gate electrode, source and drain diffusion layers are formed, and a contact hole is opened after an interlayer insulating film is deposited. Here, an impurity of a conductivity type opposite to that of the semiconductor substrate is implanted only into the opening of the contact hole using the interlayer insulating film and the gate electrode as a mask, and the source and drain diffusions are formed only below the source and drain diffusion layers. A semiconductor layer having an impurity concentration intermediate between the layer and the semiconductor substrate is formed. With this method, there is no increase in the number of photolithography steps, and there is no misalignment during impurity implantation.

[0012] Japanese Patent Application Laid-Open No. Hei 8-213600 discloses that
The high-concentration channel impurity is implanted over the entire surface of the semiconductor substrate, and then an impurity of a conductivity type opposite to that of the semiconductor substrate is implanted only below the source and drain regions using an ion implantation method utilizing channeling. , Reduce the effective semiconductor substrate impurity concentration in this region,
It is disclosed that the junction capacitance of the drain diffusion layer is reduced. Specifically, after high-concentration channel impurity implantation is performed on the entire surface of the semiconductor substrate, a gate electrode is formed, and source and drain impurities are implanted using the gate electrode as a mask. At this time, similarly, using the gate electrode as a mask, an impurity having a conductivity type opposite to that of the semiconductor substrate is ion-implanted at an implantation angle perpendicular to the semiconductor substrate surface and at which channeling occurs. Utilizing channeling with little spread in the lateral direction with respect to the implantation direction, an impurity of a conductivity type opposite to that of the semiconductor substrate is implanted only below the source and drain diffusion layers. Can keep the semiconductor substrate concentration high and reduce the junction capacitance of the source and drain diffusion layers. Further, in this method, since the same mask as that used when forming the source and drain is used, impurities can be implanted into the entire lower surface of the source and drain regions, and compared with the method disclosed in Japanese Patent Application Laid-Open No. 62-141778. As a result, the effect of reducing the junction capacitance between the source and drain diffusion layers increases.

Although the channel impurity concentration in the region where the punch-through current flows easily, that is, the region relatively deep from the gate insulating film, is increased, the switching characteristics (sub-threshold swing characteristics) of the MOSFET and the current driving capability are improved. For this purpose, it is desirable to lower the concentration of channel impurities in a shallow region near the gate-insulating film. That is, it is necessary to make the channel impurity concentration below the gate electrode a steep concentration distribution in the depth direction. To cope with this, it is possible to obtain a sharp concentration distribution in the depth direction by dividing the channel impurity into a plurality of times.

For the purpose of improving the switching characteristics of the MOSFET, there is a method of implanting an impurity only in the vicinity of the junction region between the source and drain diffusion layers using the gate electrode as a mask to alleviate an increase in junction capacitance. For the same reason, channel impurities are redistributed by ion implantation of high-concentration impurities for forming source and drain diffusion layers.

To solve the problem of suppressing the redistribution of channel impurities and forming a steep concentration distribution, for example, there is a means for solving the problem, for example, Symposium on VLSI Technology Digest of Technic.
al Papers (USA), (1996) l. Su et al., p. 12-13, and IEDM (Internatinal Electron Devices Meeting)
96 Tech.Digest (USA), (1996) M. Rodder et al., P.563
-566.

The above Symposium on VLSI Technology Diges
t of Technical Papers (USA), (1996) l.Su et al., p.1
2-13 discloses that indium (In) or antimony (Sb) is used as a channel impurity as a solution. That is, for example, boron (B) or phosphorus (P) has been used as a conventional impurity, but these are elements having a high diffusion coefficient. In particular, boron is an element having an interstitial silicon (Si) atom in a semiconductor substrate. Anomalous diffusion (enhanced diffusion) is caused by forming a pair. That is, high-concentration ion implantation during the formation of the source and drain diffusion layers causes crystal destruction of the semiconductor silicon substrate, and the generated interstitial Si atoms cause abnormal diffusion of boron.
Also, in a process involving a high temperature such as an activation heat treatment for the source and drain diffusion layers, boron and phosphorus as channel impurities also cause thermal diffusion at the same time, and a steep concentration distribution at the time of channel impurity implantation is lost due to redistribution. Become. In contrast, by using indium or antimony, which has a smaller diffusion coefficient than boron or phosphorus, as a channel impurity, thermal diffusion is less likely to occur even in a process involving high temperatures, and a steep concentration distribution at the time of implantation is maintained. ing.

The IEDM 96 Tech. Digest (USA), (19)
96) M. Rodder et al., P. 563-566, proposes to introduce a rapid temperature rise heat treatment to recover crystal defects immediately after the impurity implantation step. That is, the interstitial Si atoms formed at the time of the impurity implantation cause the accelerated diffusion of boron. This accelerated diffusion is achieved by, for example, a CVD (Chemical Vapor Deposition) process of an insulating film.
It appears remarkably in a process in which a heat load of several tens of minutes is applied at 00 ° C to 800 ° C. In contrast, immediately after the impurity implantation step, high-temperature, short-time rapid temperature rise heating is performed to eliminate interstitial Si atoms generated by the impurity implantation, so that the subsequent heat, for example, in the insulating film CVD step, is removed. Accelerated diffusion of impurities in the accompanying process is prevented.

[0018]

However, the method disclosed in Japanese Patent Publication No. 3-43787 as a means for reducing the junction capacitance of the source / drain diffusion layers uses a photolithography step, so that the manufacturing cost is reduced. In addition, there is a problem that misalignment during lithography cannot be tolerated due to the increase in size and miniaturization.

In the method disclosed in Japanese Patent Application Laid-Open No. 62-141778, the formation of the semiconductor layer having an intermediate impurity concentration is limited to the opening of the contact hole, and the opening region of the contact hole is also formed by the source and the source. In order to compensate for misalignment with the drain region, it must be smaller than the source and drain regions. As a result, the junction capacitance of the source and drain diffusion layers other than the opening region of the contact hole cannot be reduced, and even with this method, the increase in the junction capacitance cannot be eliminated yet.

Further, in the method disclosed in Japanese Patent Application Laid-Open No. 8-213600, channeling at the time of ion implantation is used, so that the process margin with respect to the ion implantation angle is small, and the amount of impurity implanted below the source and drain regions. Is difficult to control. That is, when channeling is caused at the time of ion implantation, for example, when a semiconductor substrate having a plane orientation (100) is used,
It varies greatly with the implantation angle with respect to the normal to the surface of the semiconductor substrate. Since the effect of reducing the junction capacitance of the source / drain diffusion layers largely depends on the amount of impurities implanted below the source / drain regions, the junction capacitance of the source / drain diffusion layers is effectively reduced even with this method. Difficult to do.

In these methods for reducing the junction capacitance,
Since the channel impurity is implanted before the formation of the source and drain diffusion layers, redistribution due to enhanced diffusion cannot be avoided.

On the other hand, even if the channel impurity concentration below the gate electrode is formed to have a steep concentration distribution in the depth direction, a high concentration impurity ion implantation in the subsequent formation process of the source and drain diffusion layers may cause Many defects are formed. Then, when a process involving heat is performed thereafter, channel impurities are diffused at an increased speed, and it becomes impossible to maintain a sharp concentration distribution in the depth direction.

Further, even in the method using In (indium) or Sb (antimony) as the channel impurity,
Thermal diffusion accompanying the formation of the source and drain diffusion layers cannot be completely prevented, and an increasingly steep channel impurity distribution is desired due to miniaturization of the element. However, this has not been achieved.

Even with the above-mentioned method of introducing a rapid temperature rise heat treatment for the purpose of recovering crystal defects, it is not possible to completely prevent the thermal diffusion accompanying the formation of the source and drain diffusion layers, and to miniaturize the element. Thus, an increasingly steep channel impurity distribution is desired, but this has not been achieved.

[0025]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing a semiconductor device which have been made to solve the above problems.

In a semiconductor device, an element isolation region is formed in a semiconductor substrate, and an insulated gate field effect transistor is provided in a portion of the semiconductor substrate separated by the element isolation region. A first impurity-implanted region formed in the semiconductor substrate immediately below the gate electrode, and a source having a concentration substantially equal to that of the first impurity-implanted region,
A second impurity-implanted region formed in the depth direction of the drain diffusion layer near the end in the depth direction of the element isolation region via the semiconductor substrate region.

In the above-described semiconductor device, the first impurity-implanted region that contributes to the switching characteristics of the transistor is formed in the semiconductor substrate immediately below the gate electrode.
The generation of punch-through current is suppressed. A second impurity-implanted region having the same concentration as that of the first impurity-implanted region is formed in the depth direction of the source / drain diffusion layer and near the end in the depth direction of the element isolation region via the semiconductor substrate region. As a result, the junction capacitance of the source and drain diffusion layers is reduced, and the occurrence of a parasitic transistor around the element isolation region is suppressed.

In a method of manufacturing a semiconductor device, a high-concentration impurity-implanted region of an insulated-gate field-effect transistor is formed in a semiconductor substrate, and the impurity-implanted region contributing to the switching characteristics of the insulated-gate field-effect transistor is formed in the semiconductor substrate. This is a manufacturing method for forming.

In the above-described method for manufacturing a semiconductor device, after forming a high-concentration impurity-implanted region of an insulated-gate field-effect transistor in a semiconductor substrate, an impurity-implanted region that contributes to switching characteristics of the insulated-gate field-effect transistor is formed. Therefore, it is possible to form an impurity-implanted region that contributes to the switching characteristics after a heat treatment for recovering a defect accompanying the formation of the high-concentration impurity-implanted region is performed. Therefore, in the step of forming the impurity-implanted region that contributes to the switching characteristics, heat such as heat treatment for accelerated diffusion of channel impurities accompanying high-concentration impurity implantation such as source and drain impurity implantation and heat treatment for defect recovery is used. The diffusion of channel impurities in the accompanying process is avoided. As a result, the redistribution of channel impurities from the steep concentration distribution is suppressed, so that the channel impurity concentration distribution should be set to a steep concentration distribution in order to suppress the short channel effect that becomes more pronounced as the device is miniaturized. Becomes possible. Therefore, it is possible to form an insulated gate field effect transistor having good switching characteristics and high current driving capability.

Further, even when the source / drain diffusion layers serving as the high-concentration impurity implantation regions are formed shallowly and the channel impurity concentration is set high, a high current driving capability which does not increase the junction capacitance of the source / drain diffusion layers. Insulated gate field effect transistor can be formed.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment According to a Semiconductor Device of the Present Invention
Will be described with reference to the schematic configuration diagram of FIG.

As shown in FIG. 1, a semiconductor substrate 11 has an element isolation region 12 formed by embedding an insulating film in a trench, for example. The insulated gate field effect transistor 1 is formed on the semiconductor substrate 11 electrically separated by the element isolation region 12.

Hereinafter, the configuration of the insulated gate field effect transistor 1 will be described. A gate electrode 22 is formed on a semiconductor substrate 11 with a gate insulating film 21 interposed therebetween. The semiconductor substrate 11 on both sides of the gate electrode 22 has a shallow source,
Drain regions 23 and 24 are formed. A side wall spacer 25 is formed on the side wall of the gate electrode 22. Further, deep source / drain regions 26 are formed on the gate electrode 22 side via the shallow source / drain regions 23, and shallow source / drain regions 24 are formed on the gate electrode 22 side.
, Deep source and drain regions 27 are formed. The source / drain diffusion layer 28 is formed by the shallow source / drain region 23 and the deep source / drain region 26.
The shallow source / drain region 24 and the deep source / drain region 27 constitute a source / drain diffusion layer 29 which becomes a high-concentration impurity implantation region.

Further, on the semiconductor substrate 11 immediately below the gate electrode 22, a first impurity implantation region 31 which contributes to the switching characteristics of the transistor is formed. This first
Is formed of a low-concentration impurity implantation region 32 formed on the surface side of the semiconductor substrate 11 and a high-concentration impurity implantation region 33 formed below the low-concentration impurity implantation region 32. Both the implantation region 32 and the high-concentration impurity implantation region 33 have an impurity concentration higher than the substrate concentration of the semiconductor substrate 11.

The source / drain diffusion layers 28,
29, the low concentration impurity region 1 of the semiconductor substrate 11 is formed.
3 (for example, the semiconductor substrate itself or a well)
Is formed. The second impurity-implanted region 34 has approximately the same concentration as that of the first impurity-implanted region 31, and, like the first impurity-implanted region 31, has a low-concentration impurity-implanted region 35. And a high-concentration impurity implanted region 36 formed on the lower layer side. In the drawing, the first impurity implantation region 3
The first and second impurity implanted regions 34 are formed in a continuous state. Although not shown, the insulated gate field effect transistor 1 may be provided in a well formed in the semiconductor substrate 11 separated by the element isolation region 12.

In the semiconductor device including the insulated gate field effect transistor 1 described with reference to FIG. 1, since the first impurity implantation region 31 is formed in the semiconductor substrate 11 immediately below the gate electrode 22, a short channel The effect (particularly, punch-through current) is suppressed. Also source,
The semiconductor substrate 11 extends in the depth direction of the drain diffusion layers 28 and 29.
Since the second impurity-implanted region 34 is formed via the low-concentration impurity region 13, the junction capacitance of the source / drain diffused layers 28 and 29 is reduced, and the parasitic capacitance around the element isolation region 12 is reduced. Generation of a transistor is suppressed.

Next, a second embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG. FIG.
Here, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2, the insulated gate field effect transistor 1 is formed on a semiconductor substrate 11 which is electrically separated by an element isolation region 12 because of the same structure as that described with reference to FIG. The element isolation region 1
The second impurity implanted region 34 described with reference to FIG. Therefore, similarly to the second impurity implantation region, the extension of the second impurity implantation region 34 also includes the low concentration impurity implantation region 35 and the high concentration impurity implantation region 36 formed below this region. Have been.

In the configuration shown in FIG. 2, for example, when the gate electrode 22 is formed of polysilicon,
It is desirable that the depth of the element isolation region 12 of the trench element isolation structure be set to 0.9 to 1.0 of the height of the gate electrode 22. This value depends on the impurities to be implanted (for example, boron,
Since it is determined from the projected range distance of phosphorus and the like in silicon and silicon oxide, it is appropriately set according to the material and height of the gate electrode 22 and the element isolation region 12.

In the semiconductor device described with reference to FIG. 2, the second impurity implantation region 3 is located immediately below the element isolation region 12.
4, the generation of the parasitic transistor in the periphery of the element isolation region 12 is suppressed as compared with the configuration of FIG.

Next, a first embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 and 4, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, the semiconductor substrate 1
1 (eg, a silicon substrate), an element isolation region 12 is formed by, for example, a technique for forming a normal trench element isolation. The insulating film embedded in the trench is, for example, 300 nm.
It is formed with a film thickness of. A well (not shown) may be formed in the transistor formation region of the semiconductor substrate 11 separated by the element isolation region 12.

Next, a gate insulating film 21 having a thickness of, for example, 4 nm is formed on the surface of the semiconductor substrate 11 by thermal oxidation or the like.

Further, a gate material layer (for example, polysilicon) 41 is deposited on the gate insulating film 21 by, for example, a CVD method. The deposited film thickness is, for example, 150
nm.

Next, as shown in FIG. 3B, the gate material layer 41 is processed into a gate shape using lithography technology and dry etching technology to form a gate electrode 22.
To form At this time, the portion of the gate insulating film 21 that is not covered with the gate electrode 22 is also etched.

Next, as shown in FIG. 3C, ion implantation is performed using the gate electrode 22 as a mask to form shallow source and drain regions 23 and 24 in the semiconductor substrate 11 on both sides of the gate electrode 22. As an example of the ion implantation conditions, when an NMOS transistor is formed, arsenic (As) is used as a dopant and the implantation energy is set to 10 keV. When a PMOS transistor is formed, boron difluoride (B
The implantation energy was set to 10 keV using F ₂ ). The dose was set to about 10 ¹⁴ / cm ² in each case.

Next, R for recovering the defect of the semiconductor substrate is used.
TA (Rapid Thermal Annealing) is, for example, 1 ° C./s
At the above-mentioned heating rate, heating is performed by rapid heating at, for example, about 900 ° C. to 1200 ° C. Here, as an example, 1
RTA was performed for 10 seconds in a nitrogen atmosphere at 000 ° C.
This RTA can also serve as a heat treatment for activating the implanted impurities.

Next, as shown in FIG. 4D, an insulating film for forming a side wall spacer is formed so as to cover the gate electrode 22, and the insulating film is etched back to form a side wall of the gate electrode 22. The side wall spacer 25 is, for example, 0.1
It is formed with a width of about μm.

Further, as shown in FIG. 4 (5), source and drain ions are implanted into the semiconductor substrate 11 by ion implantation using the gate electrode 22 and the side wall spacer 25 as a mask, and a shallow gate electrode 22 is formed. Deep source / drain region 26 via source / drain region 23
And a deep source / drain region 27 is formed on the gate electrode 22 side with a shallow source / drain region 24 interposed therebetween. As an example, the ion implantation condition is such that when an NMOS transistor is formed, arsenic (A) is used as a dopant.
The implantation energy was set to 50 keV using s).
In the case of forming a PMOS transistor, implantation energy was set to 20 keV using boron difluoride (BF ₂ ) as a dopant. The dose was set to about 10 ¹⁵ / cm ² in each case.

Then, activation heat treatment for the ion-implanted impurities (source and drain impurities) is performed. The activation heat treatment is performed, for example, in a nitrogen atmosphere at 1000 ° C. for 1 hour.
Performed by RTA for 0 seconds. As a result, a source / drain diffusion layer 28 composed of a shallow source / drain region 23 and a deep source / drain region 26 and a source / drain diffusion layer 29 composed of a shallow source / drain region 24 and a deep source / drain region 27 are formed. Be activated.

Next, as shown in FIG. 4 (6), channel impurity implantation (well implant, channel stop implant, punch-through implant, threshold voltage (Vth) adjustment implant, etc.) is performed on the surface of the semiconductor substrate 11. Through the gate electrode 22 and the side wall spacer 25 at a vertical angle to the impurity implantation region 30 in the semiconductor substrate 11.
1 (corresponding to the first and second impurity-implanted regions 31 and 34 in FIG. 1) is formed on the upper layer side with the low-concentration impurity-implanted region 37 and on the lower layer side with the high-concentration impurity-implanted region 38. As a result, the impurity implantation region 30 is
The semiconductor substrate 11 is formed in a shallow region directly below the semiconductor substrate 11 due to the thickness of the element isolation region 12, and directly under the source / drain diffusion layers 28 and 29 via the low-concentration impurity region 13 which is a part of the semiconductor substrate 11. 11 is formed in a deep region. In addition, an implantation is an abbreviation of ion implantation.

For example, the ion implantation conditions for a well implanter are, for example, when an NMOS transistor is formed, boron (B) is used as a dopant, the implantation energy is 280 keV, and the dose is 1 × 10 ¹³ / cm ² . Set. When forming a PMOS transistor, the implantation energy was set to 700 keV and the dose was set to 1 × 10 ¹³ / cm ² by using phosphorus (P) as a dopant.

For example, the ion implantation conditions of the channel stop implantation are as follows. For example, when an NMOS transistor is formed, boron (B) is used as a dopant, the implantation energy is 110 keV, and the dose is 4 × 10 ¹² /.
cm ² . In the case of forming a PMOS transistor, the implantation energy is 320 keV and the dose is 4 × 10 ¹² / cm by using phosphorus (P) as a dopant.
Set to ² .

For example, the ion implantation conditions of the punch-through implantation are as follows. For example, when forming an NMOS transistor, boron (B) is used as a dopant, the implantation energy is 80 keV, and the dose is 5 × 10 ¹² / cm ^2.
８8 × 10 ¹² / cm ² . When a PMOS transistor is formed, phosphorus (P) is used as a dopant.
With an implantation energy of 220 keV and a dose of 1
× 10 ¹³ / cm ² was set.

The threshold voltage (Vth) adjustment implant can be used also as a punch-through implant here, and is omitted here. The channel stop implant can also serve as a well implant, a punch-through stop implant, or the like.

Next, activation annealing of the ion-implanted impurities (channel impurities) is performed by heating at a rapid rate of, for example, about 900 ° C. to 1200 ° C. at a rate of, for example, 1 ° C./s or more. Here, as an example, 10
RTA was performed in a nitrogen atmosphere at 00 ° C. for 10 seconds. Thus, the insulated gate field effect transistor 1 is formed.

Although not shown, an interlayer insulating film, a contact, a wiring, and the like are formed by a conventional method. Salicide (Self-Aligned Silicidation: SALI)
In the case of forming CIDE), a salicide process is performed before forming an interlayer insulating film.

In the method of manufacturing a semiconductor device described above, after forming the source and drain diffusion layers 28 and 29 to be the high-concentration impurity implantation regions of the insulated gate field effect transistor 1, heat treatment for defect recovery is performed like RTA. Since the crystal defects are recovered by high-temperature treatment of rapid temperature rise and heating, thermal diffusion of impurities (source and drain impurities in this case) already implanted can be minimized, and the short channel effect effect In this case, it is possible to form a shallow source / drain, which is effective for suppressing the occurrence of the problem. Moreover, the above R
In addition to TA, after performing a thermal process such as a process of forming the element isolation region 12, a process of forming the gate electrode 22, and a process of forming the sidewall spacer, channel impurities are implanted to form the impurity implanted region 30. Accelerated diffusion of channel impurities due to high-concentration impurity implantation such as source and drain impurity implantation, and channel impurity diffusion in a process involving heat such as heat treatment for defect recovery are avoided. Therefore, redistribution of channel impurities from the steep concentration distribution is suppressed. As described above, preventing the redistribution of the channel impurity can be achieved by setting the impurity concentration of the channel formation region to be low and controlling the carrier mobility of the channel portion even when the channel impurity concentration is set high to suppress the punch-through current. To keep you high. Therefore, an insulated gate field effect transistor having high current driving capability can be obtained.

Therefore, in order to suppress the short channel effect (especially punch-through current) which becomes more remarkable as the device is miniaturized, the concentration distribution of the channel impurity can be set to a steep concentration distribution, and the switching characteristics are improved. ,
The insulated gate field effect transistor 1 having high current driving capability is obtained.

The semiconductor substrate 1 is placed on the gate electrode 22 from above.
Since the channel impurity is implanted perpendicularly to the surface of the gate electrode 22, the channel impurity implanted from the formation regions of the source / drain diffusion layers 28 and 29 is deeper than the channel impurity implanted below the gate electrode 22. Will be done. Therefore, the source and drain diffusion layers 28 and 29
The substrate concentration in the vicinity of the junction does not increase, and the junction capacitance does not increase even if a channel impurity having a sufficient concentration for suppressing the punch-through current is implanted. In addition, the RTA for recovering crystal defects can simultaneously activate the impurities, so that the activation rate can be increased.

Although not shown, even when the source and drain diffusion layers 28 and 29 serving as the high-concentration impurity implantation regions are formed shallowly and the channel impurity concentration is set high, the source and drain diffusion layers 28 and 29 may be formed. An insulated gate field effect transistor having a high current driving capability that does not increase the junction capacitance is formed.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to a manufacturing process diagram of FIG. In FIG. 5, the same components as those described with reference to FIGS. 3 and 4 are denoted by the same reference numerals.

As shown in FIG. 5, a state where an offset insulating film (not shown) is provided on the gate electrode 22 is formed by a process of forming a gate electrode structure having a normal offset insulating film provided thereon. A shallow source / drain region 23 and a shallow source / drain region 24 are formed. Thereafter, sidewall spacers 25 are formed on the sidewalls of the gate electrode 22 and the offset insulating film. Next, deep source / drain regions 26 and deep source / drain regions 27 are formed to form source / drain diffusion layers 28 and 29. Next, after removing the offset insulating film,
By performing a salicide process, the silicide layer 6 is formed on the gate electrode 22 and the source / drain diffusion layers 28 and 29.
1 and silicide layers 62 and 63 are formed by a normal salicide process.

Thereafter, channel impurity implantation is performed at an angle perpendicular to the surface of the semiconductor substrate 11 and at the gate electrode 22.
And through the side wall spacer 25, the semiconductor substrate 11
Impurity implantation region 30 serving as a channel impurity implantation region therein
1 (corresponding to the first and second impurity-implanted regions 31 and 34 in FIG. 1) is formed on the upper layer side with the low-concentration impurity-implanted region 37 and on the lower layer side with the high-concentration impurity-implanted region 38. In this case, the impurity implantation region 30 is
Is formed in a shallow region through the low-concentration impurity region 14 of the semiconductor substrate 11 immediately below the gate electrode 22 and immediately below the gate electrode 22 in the vicinity of the surface of the semiconductor substrate 11 immediately below the sidewall spacer 25. Is done. Also source,
Immediately below the drain diffusion layers 28 and 29, a deep region of the semiconductor substrate 11 is formed via the low-concentration impurity region 13 which is a part of the semiconductor substrate 11.

According to the above-described manufacturing method, a punch-through current can be suppressed and the source / drain diffusion layers 28 and 29 can be suppressed even in a method of manufacturing a semiconductor device to which a salicide process is applied.
It is possible to apply a process of forming an impurity implanted region 30 which becomes a channel impurity implanted region having a structure in which the junction capacitance is suppressed.

Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process chart of FIG. 6, the same components as those described with reference to FIGS. 3 and 4 are denoted by the same reference numerals.

In the first embodiment relating to the method of manufacturing a semiconductor device, the channel impurity is implanted into the semiconductor substrate 11.
6, the channel impurity is implanted into the semiconductor substrate 11 below the gate electrode 22 obliquely from the surface of the semiconductor substrate 11 as shown in FIG. In the step described in (1), the thickness of the polysilicon to be deposited is set to, for example, 200 nm. In the step described in (6) in FIG. From (injection direction in the plane of the semiconductor substrate 11 is 1
For example, the implantation angle is 45 degrees with respect to the surface of the semiconductor substrate 11 (divided into two times with a shift of 80 degrees) to form the channel impurity implantation region 39. For example, the implantation conditions of the punch-through stop implant in the channel impurity implantation are as follows.
As an example, when forming an NMOS transistor having a gate length of, for example, 0.1 μm, boron (B) is added for 50 ke.
When V is implanted to form a PMOS transistor, phosphorus (P) is implanted at about 120 keV.

In the manufacturing method described in the third embodiment, the channel impurity is implanted obliquely below the surface of the semiconductor substrate 11 and below the gate electrode 22, so that the source and drain diffusion layers 28 and The impurity concentration of the substrate in the vicinity of the junction 29 can be set to about の of the impurity concentration below the gate electrode 22 (when the implantation direction is changed by 180 degrees and the implantation is performed twice in total, the gate electrode 22 becomes a mask. Therefore, only one impurity implantation can be performed on the source / drain diffusion layers 28 and 29). As a result, even if channel impurities are implanted under the gate electrode 22 at a concentration sufficient to suppress the punch-through current, the junction capacitance of the source / drain diffusion layers 28 and 29 does not increase significantly.
Therefore, the junction capacitance between the source / drain diffusion layers 28 and 29 and the semiconductor substrate 11 can be reduced as compared with the conventional structure. Therefore, even with this manufacturing method, it is possible to provide an insulated gate field effect transistor having high current driving capability and stable operation characteristics.

As described above, the method of implanting channel impurities obliquely below the surface of the semiconductor substrate 11 below the gate electrode 22 is performed when the gate length becomes smaller than the height of the gate electrode 22. It is valid. At this time,
In contrast to the method of implanting channel impurities perpendicularly to the surface of the semiconductor substrate 11 from above the gate electrode 22, the implantation depth can be made smaller, so that the dispersion of impurities at the time of implantation can be reduced.

It is also possible to form a stacked diffusion layer on the source and drain regions described in the above embodiments. As an example, the case where a stacked diffusion layer is formed in the first embodiment according to the manufacturing method is described in a fourth embodiment.
An embodiment will be described with reference to FIG. FIG. 7 shows a case where a stacked diffusion layer is formed in the manufacturing method described with reference to FIGS.
Components similar to those described with reference to FIG. 4 are denoted by the same reference numerals.

As shown in FIG. 7, after the side wall spacers 25 are formed on the side walls of the gate electrode 22, as described with reference to FIG. 4 (5), for example, on silicon (on the shallow source / drain regions 23 and 24). Only), silicon is selectively epitaxially grown. As a growth method, as an example, the pressure of the epitaxial growth atmosphere is set to 133P.
a, the substrate temperature is set to 620 ° C., and disilane (Si ₂ H ₆ ) is flowed at a flow rate of 10 sccm for 12 seconds in the film formation atmosphere to selectively epitaxially grow silicon only on silicon. After that, 1 sc of chlorine (Cl ₂ )
The silicon is grown on the insulating film such as the element isolation region 12 and the side wall spacer 25 by etching at a flow rate of 15 cm for 15 seconds to remove the silicon. At this time, the surface layer of the epitaxial growth layer on the silicon is also removed, but the epitaxial growth layer on the silicon is thinner than the epitaxial growth layer on the insulating film, so that the epitaxial growth layer on the silicon remains. By repeating silicon epitaxial growth and silicon etching 20 times continuously, a silicon layer of an epitaxially grown layer having a thickness of 50 nm is formed.
This silicon layer becomes the stacked diffusion layers 71 and 72. At this time, the stacked diffusion layers 71, 7 are also formed on the gate electrode 22.
A silicon layer 73 similar to that of No. 2 is formed. Thereafter, as described with reference to FIG. 4 (6), deep source and drain regions are formed in the semiconductor substrate 11, and further steps are performed. The stacked diffusion layers 71, 71
The thickness of 72 can be changed as appropriate.

In the fourth embodiment of the method for manufacturing a semiconductor device according to the present invention, the stacked diffusion layers 71 and 72 are formed before forming the channel impurity implantation region (not shown) which contributes to the switching characteristics of the transistor. So
There is no redistribution of impurities in the channel impurity implantation region. Therefore, the same operation and effect as described in the first embodiment relating to the above manufacturing method are accumulated, and the diffusion layer 7 is stacked.
It is possible to obtain even if 1, 72 are formed.

The method of manufacturing a semiconductor device described above can be applied to a method of manufacturing a transistor without a sidewall spacer, for example, a memory cell transistor of a DRAM. In this case, after forming the gate electrode without forming the side wall spacer, the source and drain diffusion layers are formed by one ion implantation. afterwards,
Ion implantation for forming a channel impurity implantation region may be performed.

Also in the case of the above-described manufacturing method, it is possible to obtain the same operational effects as those described in the first embodiment relating to the above-mentioned manufacturing method.

The energy values of the various implants described in the above embodiments are not limited to the above values.
It is set appropriately in accordance with the desired transistor characteristics. The structure of the gate electrode is not limited to a single polysilicon layer, but may be another structure such as a polycide structure. Also, the height of the gate electrode is not limited to the above numerical example, but is appropriately set according to desired transistor characteristics. In the case where an impurity is implanted into the gate electrode, a film for forming the gate electrode may be formed in advance so as to contain the impurity.

[0076]

As described above, according to the semiconductor device of the present invention, since the first impurity-implanted region which contributes to the switching characteristics of the transistor is formed in the semiconductor substrate immediately below the gate electrode, punch-through is achieved. Generation of current can be suppressed. A second impurity-implanted region having the same concentration as that of the first impurity-implanted region is formed in the depth direction of the source / drain diffusion layer and near the end in the depth direction of the element isolation region via the semiconductor substrate region. Therefore, the junction capacitance between the source and drain diffusion layers can be reduced, and the occurrence of a parasitic transistor around the element isolation region can be suppressed.

According to the method of manufacturing a semiconductor device of the present invention,
After forming a high-concentration impurity-implanted region of an insulated-gate field-effect transistor in a semiconductor substrate, an impurity-implanted region that contributes to switching characteristics of the insulated-gate field-effect transistor is formed. This can be performed after heat treatment for recovering defects due to the formation of the impurity-implanted region. Therefore, it is possible to avoid accelerated diffusion of channel impurities due to high-concentration impurity implantation such as source and drain impurity implantation and diffusion of channel impurities in a step involving heat such as heat treatment for defect recovery. As a result, redistribution of channel impurities from a steep concentration distribution can be suppressed,
By setting the concentration distribution of the channel impurity to a steep concentration distribution, the short channel effect can be suppressed. Therefore, it is possible to form an insulated gate field effect transistor having good switching characteristics and high current driving capability. Further, according to the manufacturing method of the present invention, since the manufacturing can be performed using the conventional semiconductor line, the above-described effects can be obtained without a significant increase in cost.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment according to a semiconductor device of the present invention.

FIG. 2 is a schematic configuration diagram showing a second embodiment according to the semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram showing a first embodiment according to a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a manufacturing step diagram (continued) showing the first embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a manufacturing process diagram showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a manufacturing process diagram showing a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a manufacturing process diagram showing a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a manufacturing process diagram showing a process flow of a channel impurity implantation method according to a conventional technique.

FIG. 9 is a manufacturing step diagram (continued) showing a process flow of a channel impurity implantation method according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulated gate field effect transistor, 11 ... Semiconductor substrate, 12 ... Element isolation region, 22 ... Gate electrode, 28,
29: source and drain diffusion layers, 31: first impurity implantation region, 34: second impurity implantation region

Claims (41)

[Claims] An element isolation region formed in a semiconductor substrate;
A semiconductor device provided with an insulated gate field effect transistor provided on the semiconductor substrate portion separated by the element isolation region, wherein the insulated gate field effect transistor contributes to switching characteristics, A first impurity-implanted region formed in the semiconductor substrate immediately below a gate electrode of the effect transistor; and a source and drain diffusion region of the insulated gate field-effect transistor having a concentration substantially equal to that of the first impurity-implanted region. A second impurity-implanted region formed in the depth direction of the layer near the end in the depth direction of the element isolation region via the semiconductor substrate region. 2. The semiconductor device according to claim 1, wherein said second impurity-implanted region is formed to extend immediately below said element isolation region. 3. After forming a high-concentration impurity implantation region of an insulated gate field effect transistor in a semiconductor substrate, forming an impurity implantation region contributing to switching characteristics of the insulated gate field effect transistor in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 4. The method for manufacturing a semiconductor device according to claim 3, wherein the high-concentration impurity-implanted region is formed by an ion implantation method, and then an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed. Before you do
A method for manufacturing a semiconductor device, comprising a step of performing a heat treatment for defect recovery. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the heat treatment for recovering the defects is performed by rapid heating. 6. The method for manufacturing a semiconductor device according to claim 3, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulation is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
A step of forming a source region and a drain region serving as the high-concentration impurity-implanted region by injecting a conductive-type impurity at a high concentration and performing a heat treatment, and thereafter, a switching characteristic of the insulated gate field-effect transistor in the semiconductor substrate; A method of forming an impurity-implanted region that contributes to a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 4, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulation is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
A step of forming a source region and a drain region serving as the high-concentration impurity-implanted region by injecting a conductive-type impurity at a high concentration and performing a heat treatment; A method of forming an impurity-implanted region that contributes to a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 5, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulating is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
A step of forming a source region and a drain region serving as the high-concentration impurity-implanted region by injecting a conductive-type impurity at a high concentration and performing a heat treatment, and thereafter, a switching characteristic of the insulated gate field-effect transistor in the semiconductor substrate; A method of forming an impurity-implanted region that contributes to a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 3, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulation is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
Forming a shallow source region and a shallow drain region by implanting a conductive impurity at a high concentration; forming a sidewall spacer serving as a mask at the time of ion implantation on a sidewall of the gate electrode; Forming a deep source region and a deep drain region serving as the high-concentration impurity-implanted region by injecting a second-conductivity-type impurity at a high concentration into the semiconductor substrate using the sidewall spacer as a mask; Performing activation and a heat treatment step for recovering crystal defects in the semiconductor substrate, and thereafter performing a step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 10. The method for manufacturing a semiconductor device according to claim 4, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulation is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
Forming a shallow source region and a shallow drain region by implanting a conductive impurity at a high concentration; forming a sidewall spacer serving as a mask at the time of ion implantation on a sidewall of the gate electrode; Forming a deep source region and a deep drain region serving as the high-concentration impurity-implanted region by injecting a second-conductivity-type impurity at a high concentration into the semiconductor substrate using the sidewall spacer as a mask; Performing activation and a heat treatment step for recovering crystal defects in the semiconductor substrate, and thereafter performing a step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 11. The method for manufacturing a semiconductor device according to claim 5, wherein an element isolation region is formed in a semiconductor substrate of a first conductivity type, and a gate insulation is provided on a surface of the semiconductor substrate separated by the element isolation region. And a step of forming a gate electrode through a film. Then, a second step is performed in the semiconductor substrate using the gate electrode as a mask.
Forming a shallow source region and a shallow drain region by implanting a conductive impurity at a high concentration; forming a sidewall spacer serving as a mask at the time of ion implantation on a sidewall of the gate electrode; Forming a deep source region and a deep drain region serving as the high-concentration impurity-implanted region by injecting a second-conductivity-type impurity at a high concentration into the semiconductor substrate using the sidewall spacer as a mask; Performing activation and a heat treatment step for recovering crystal defects in the semiconductor substrate, and thereafter performing a step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 12. The method for manufacturing a semiconductor device according to claim 6, wherein before the step of forming an impurity-implanted region contributing to switching characteristics of the insulated gate field effect transistor, the semiconductor device is stacked on the source region and the drain region. A method for manufacturing a semiconductor device, comprising a step of forming a diffusion layer. 13. The method for manufacturing a semiconductor device according to claim 7, wherein before the step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor, the semiconductor device is stacked on the source region and the drain region. A method for manufacturing a semiconductor device, comprising a step of forming a diffusion layer. 14. The method of manufacturing a semiconductor device according to claim 8, wherein before the step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor, the semiconductor device is stacked on the source region and the drain region. A method for manufacturing a semiconductor device, comprising a step of forming a diffusion layer. 15. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming an impurity-implanted region contributing to switching characteristics of the insulated gate field-effect transistor comprises: Forming a stacked diffusion layer on the semiconductor device. 16. The method for manufacturing a semiconductor device according to claim 10, wherein before the step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor, the deep source region and the deep drain region are formed. Forming a stacked diffusion layer on the semiconductor device. 17. The method for manufacturing a semiconductor device according to claim 11, wherein before the step of forming an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor, on the deep source region and the deep drain region. Forming a stacked diffusion layer on the semiconductor device. 18. The method of manufacturing a semiconductor device according to claim 6, wherein an impurity is implanted into an impurity implantation region contributing to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 19. The method of manufacturing a semiconductor device according to claim 7, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 20. The method of manufacturing a semiconductor device according to claim 8, wherein an impurity is implanted in a direction perpendicular to a surface of the semiconductor substrate into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 21. The method for manufacturing a semiconductor device according to claim 9, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 22. The method of manufacturing a semiconductor device according to claim 10, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 23. The method of manufacturing a semiconductor device according to claim 11, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 24. The method of manufacturing a semiconductor device according to claim 12, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 25. The method of manufacturing a semiconductor device according to claim 13, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 26. The method of manufacturing a semiconductor device according to claim 14, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 27. The method of manufacturing a semiconductor device according to claim 15, wherein an impurity is implanted in a direction perpendicular to a surface of the semiconductor substrate into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 28. The method for manufacturing a semiconductor device according to claim 16, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 29. The method of manufacturing a semiconductor device according to claim 17, wherein an impurity is implanted into an impurity implantation region that contributes to switching characteristics of the insulated gate field effect transistor in a direction perpendicular to the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the method is formed by an ion implantation method. 30. The method of manufacturing a semiconductor device according to claim 6, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed such that an impurity implantation region is formed obliquely with respect to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 31. The method of manufacturing a semiconductor device according to claim 7, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 32. The method of manufacturing a semiconductor device according to claim 8, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 33. The method of manufacturing a semiconductor device according to claim 9, wherein an impurity-implanted region contributing to switching characteristics of the insulated gate field effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 34. The method of manufacturing a semiconductor device according to claim 10, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 35. The method of manufacturing a semiconductor device according to claim 11, wherein an impurity-implanted region contributing to switching characteristics of the insulated gate field effect transistor is formed obliquely with respect to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 36. The method of manufacturing a semiconductor device according to claim 12, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 37. The method of manufacturing a semiconductor device according to claim 13, wherein an impurity-implanted region contributing to switching characteristics of the insulated gate field effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 38. The method of manufacturing a semiconductor device according to claim 14, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 39. The method of manufacturing a semiconductor device according to claim 15, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 40. The method of manufacturing a semiconductor device according to claim 16, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field-effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward. 41. The method of manufacturing a semiconductor device according to claim 17, wherein an impurity-implanted region that contributes to switching characteristics of the insulated gate field effect transistor is formed in a direction oblique to a surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed by an ion implantation method of implanting impurities downward.