JP2000012773A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide an electrode terminal outside a mold part in a conventional semiconductor device, an extra size of the terminal part is required, and the outer shape is reduced. Could not be done. In addition, since the pattern surface crosses the end surface of the mold portion, there is a problem that the mold presses the pattern in the molding process, thereby breaking the pattern. SOLUTION: A light emitting chip, a light receiving chip, and an IC are provided on a substrate.
In a semiconductor device on which electronic components are mounted and resin-molded, a multi-layer laminated substrate is used as the substrate, and a resin mold portion extending to an end surface of the multi-layer laminated substrate is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which electronic components such as a light emitting chip, a light receiving chip, and an IC are mounted on a substrate by reflow soldering or the like and molded with a resin, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 3A is an external view of a conventional semiconductor device having a mold structure, and FIG.
5 is a sectional view taken along line YY 'of FIG.

In FIG. 3A, a conventional semiconductor device 50 having a mold structure is an example of an optical coupling device having a light emitting lens portion and a light receiving lens portion, and is mounted on a pattern 52 of a substrate 51. There is a light emitting chip, a light receiving chip, and an IC (not shown), which are covered by a mold section 53 to form a light emitting lens section 54 and a light receiving lens section 55. Reference numeral 56 denotes a terminal portion, which is a pattern 5 of the substrate 51.
2 are electrically connected. The terminal portion 56 is a portion that is not covered with the mold resin. The outer dimension of the short side of the semiconductor device 50 is a length obtained by adding the length A of the mold portion and the length B of the pattern 52a not covered with the mold resin, (A +
B).

In FIG. 3B, a light emitting lens portion 54 of a semiconductor device 50 having a conventional mold structure includes a substrate 51, a pattern 52, a light emitting chip 57, and a mold portion 5.
3 is formed.

FIG. 3 shows an example of an optical coupling device having a light emitting lens portion and a light receiving lens portion. The short side of the semiconductor device 50 is, for example, A = 3.15 mm, B = 0.65 mm,
+ B = 3.8 mm.

FIG. 4A is a diagram showing a pattern 52 on the front side of a substrate 51 of a conventional semiconductor device 50.
(B) is a pattern 5 on the back side of the substrate 51 of the semiconductor device 50.
FIG.

In FIG. 4A, reference numeral 51 denotes a substrate; 52, a pattern on the front side; 53a, an end face of a molded portion; 57, a light emitting chip; 59, a light receiving chip; IC, 60 is IC, 6
1 is a gold wire.

In FIG. 4B, 51 is a substrate, 52 is a pattern on the back side, and 56 is a terminal portion.

[0009]

However, in the conventional semiconductor device 50, the electrode terminals must be formed outside the mold portion 53 so that the terminal portions 56 are not filled with the mold resin. In addition to the size of the mold portion, the size of the terminal is further required, and the external shape cannot be reduced.

Further, since the pattern 52 on the component mounting surface is directly protruded from the end face 53a of the mold portion, the copper foil layer for forming the pattern and the mold portion are compared with the adhesiveness between the substrate 51 and the resin forming the mold portion. Low adhesion to resin
The heat resistance to reflow soldering and hand soldering has been reduced, which has been a factor of reducing the reliability of products. Further, since the pattern crosses the end face 53a of the mold portion, there is a problem that the mold presses the pattern in the molding step, thereby breaking the pattern.

SUMMARY OF THE INVENTION The present invention has been made in view of these problems, and has been made to reduce the external shape of a semiconductor device, improve the heat resistance against reflow soldering and manual soldering, and prevent disconnection of a pattern to improve reliability. It is an object to provide a highly reliable semiconductor device and a manufacturing method thereof.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device including a light emitting chip, a light receiving chip, and an IC mounted on a substrate.
In a semiconductor device on which electronic components are mounted and resin-molded, a multi-layer laminated substrate is used as the substrate, and a resin mold portion extending to an end surface of the multi-layer laminated substrate is provided.

In the semiconductor device according to a second aspect of the present invention, a predetermined distance is provided between a pattern end of a component mounting surface of the multilayer laminated substrate and an outer end surface of the multilayer laminated substrate. Is what you do.

According to a third aspect of the present invention, there is provided a semiconductor device according to the third aspect of the present invention, wherein the heat radiation pattern is formed by connecting a pattern on which a component having heat generation, such as a light emitting chip or an IC, of the multilayer laminated substrate is mounted. And a heat-dissipating ground pattern for assisting heat radiation.

According to a fourth aspect of the present invention, in the semiconductor device according to the fourth aspect of the invention, the heat dissipation pattern and the heat dissipation ground pattern provided on the multi-layer laminated substrate are formed by forming the heat dissipation pattern and the heat dissipation ground pattern in an irregular shape. It is characterized in that the peripheral distance of the proximity surface is increased. Furthermore, claim 5 of the present invention
The semiconductor device according to the present invention is characterized in that a light emitting lens portion and a light receiving lens portion are provided on the resin mold portion formed on the multilayer laminated substrate.

According to a sixth aspect of the present invention, in the semiconductor device according to the sixth aspect of the invention, a pattern of a surface of the multilayer laminated substrate in contact with the resin mold portion is formed by electroplating, and at least a part of the pattern formed by electroplating. Are formed electrically independent of each other on the pattern forming surface from the end face of the resin mold portion.

Further, in the semiconductor device according to claim 7 of the present invention, the electroplating pattern is formed such that the electrically independent electroplating pattern is independent of other electroplating patterns on a forming surface thereof. A through-hole is provided in the formed substrate, and the through-hole is filled with a mold resin forming the resin mold portion.

Further, according to the method of manufacturing a semiconductor device according to the present invention, a light emitting chip, a light receiving chip, an IC
A method of manufacturing a semiconductor device, comprising mounting an isoelectronic component and resin molding, using a multilayer laminated substrate for the substrate, and having a resin molded portion extending to an end surface of the multilayer laminated substrate, Forming a pattern by electroplating on the surface in contact with the resin mold portion, and forming a through hole in the multilayer laminated substrate on which the electroplating pattern is formed, and disconnecting at least a part of the electroplating pattern. It is characterized by comprising a step of making the resin mold portion electrically independent and a step of covering the electrically independent electroplating pattern so as not to be exposed on an end face.

According to a ninth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
A method of manufacturing a semiconductor device, comprising mounting an isoelectronic component and resin molding, using a multilayer laminated substrate for the substrate, and having a resin molded portion extending to an end surface of the multilayer laminated substrate, A step of forming an electrically independent pattern on the surface in contact with the resin mold portion by electroplating by connecting through a through hole, so that the electrically independent electroplating pattern is not exposed on an end face. A step of covering and forming the resin mold portion.

[0020]

1 and 2 are views showing a first embodiment of the present invention, and FIG. 1A is an external view of a semiconductor device having a mold structure according to the present embodiment.
FIG. 1B is a sectional view taken along the line XX ′ of FIG. FIG. 2 is a diagram showing a pattern of a multilayer multilayer substrate of a semiconductor device having a mold structure according to the present embodiment.
FIG. 2A is a diagram showing a pattern on a mounting surface, and FIG.
FIG. 2C is a diagram showing a pattern of the intermediate layer, and FIG. 2C is a diagram showing a pattern of the back surface.

In FIG. 1A, a semiconductor device 10 having a mold structure according to the present embodiment is an example of an optical coupling device having a light-emitting lens portion and a light-receiving lens portion, and a substrate 11 includes an upper substrate 11a and a lower substrate 11a. Light-emitting chip, light-receiving chip, and IC, which are composed of a multilayer laminated substrate having a laminated structure of the upper substrate 11b and are mounted on the pattern 12 of the upper substrate 11a.
(Not shown), and forms a mold portion 13 having a light emitting lens portion 14 and a light receiving lens portion 15. 16
Is a terminal portion, which is electrically connected to the pattern 12 of the substrate 11.

In FIG. 1A and FIG. 1B, the substrate 11 is a multilayer laminated substrate (in this embodiment, an example of a two-layer substrate), and a terminal portion 16 is provided below the mold portion 13. After forming, the outer shape is the length A of the mold part 13 (about 3.15 mm)
Only fit. Further, the structure is such that the component mounting surface pattern does not pass between the mold portion 13 and the substrate 11a, and the component mounting surface pattern does not protrude from the end face of the product.

In FIG. 1B, the light emitting lens portion 14 of the semiconductor device 10 having the mold structure of the present embodiment is
It is formed by a substrate 11 (11a, 11b), a pattern 12, a light emitting chip 17, and a mold section 13 on the upper side.

Further, as shown in FIG.
The mold part 13 is formed up to the end face of the multilayer laminated substrate 11, so that the semiconductor device 10 having a small external shape can be obtained.

In the semiconductor device 10 of this embodiment shown in FIG.
This is an embodiment of an optical coupling device having a light-emitting lens portion and a light-receiving lens portion, and adopts a structure in which a component mounting surface pattern and an intermediate layer pattern are electrically connected by through holes as described with reference to FIG. Therefore, the short side of the semiconductor device 10 is, for example, A = 3.15 mm, which is A + B of the conventional example.
= 3.80 mm.
Further, the mold end face 13a does not cross the component mounting surface pattern, and no pattern disconnection occurs.

One example of the external size of the semiconductor device 10 of the present embodiment is that the short side (length) is about 2.5 mm to about 8.0 mm, the long side (width) is about 7.0 mm to about 15.0 mm, and the height is about 2.5
mm to about 7.0 mm.

In the above example, for example, the short side A = 3.15
mm, which has been described as being much smaller than A + B = 3.80 mm in the conventional example, but B = 0.65.
The effect of reducing mm is great. When a semiconductor device according to an embodiment of the present invention is applied to a small electronic device, for example, a mobile phone, the semiconductor device 10 is often mounted in a horizontal shape, that is, in a shape in which A is a height. The size of A is a factor that determines the thickness of the small electronic device. Therefore, a small electronic device having a thickness of B = 0.65 mm can be realized, and its practical effect is great.

FIG. 2 is a view showing a pattern of a laminated multilayer substrate of a semiconductor device having a mold structure according to the present embodiment, FIG. 2 (a) is a view showing a pattern on a mounting surface, and FIG. FIG. 2 is a diagram showing a layer pattern, and FIG.
(C) is a figure which shows the pattern of a back surface.

In FIG. 2A, 11a is a substrate, 12a
Is a front side pattern, 13a is a mold end face, 17 is a light emitting chip, 19 is a light receiving chip, 20 is an IC for controlling the light emitting chip 17 and the light receiving chip (photodiode or the like) 19, 21 is a gold wire, and 29 is a component. Mounting surface pattern 12
Through holes for electrically connecting the intermediate layer pattern 30 to the intermediate layer pattern 30.

The distance C is the distance between the pattern end 22 on the component mounting surface of the multilayer laminated substrate 11a and the end face 13a of the molded part, and C> 0. Preferably, C to about 0.2
mm to about 0.6 mm. Since the adhesive strength between the pattern 12 on the front side made of a copper foil layer or the like and the mold portion 13 is low, the size of C is an element that determines the adhesive strength between the substrate 11a and the mold portion 13.

In FIG. 2B, 11b is a substrate, 16
Is a terminal portion, 30 is a pattern on the front side, 13a is an end face of the mold portion, 30a is a light emitting chip heat radiation pattern, 30b is a heat radiation ground pattern, 29 is an electrical connection between the component mounting surface pattern 12 and the intermediate layer pattern 30. Through-hole, for. The intermediate layer pattern 30 includes a light emitting chip heat radiation pattern 30a and a heat radiation ground pattern 3.
0b and a wiring pattern 30c.

In FIG. 2B, the light emitting chip heat radiation pattern 30a and the heat radiation ground pattern 30b are adjacent to each other, and the combination of the uneven shape (31) allows
The light emitting chip heat radiation pattern 30a and the heat radiation ground pattern 30b are disposed close to each other, and the peripheral distance L between the adjacent surfaces of the two patterns is determined by the shape (31) of the uneven surface or the like.
, Heat is transmitted from the light emitting chip to the pattern 12, the light emitting chip heat radiating pattern 30a, and the heat radiating ground pattern 30b, so that the heat radiating property of the heat generated from the light emitting chip can be increased.

FIG. 2C is a diagram of the back surface of the substrate 11b, where 11b is the substrate, 16 is the terminal portion, and 32 is the pattern on the back surface.

Next, as the second and third embodiments, in the manufacture of the semiconductor device of the first embodiment, the pattern of the surface in contact with the mold portion 13 of the laminated multilayer substrate 11 is formed by electrolytic plating. What is formed will be described.

The pattern formed on the substrate of the semiconductor device or the like according to the first embodiment is preferably formed by electrolytic plating in consideration of sufficient conductivity as an electrode pattern and ease of formation. However, as shown in FIG. 3, since the light emitting chip 17 and the IC 20 cannot be directly connected by the gold wire 21, they must be connected via the relay pad 23, so that the pattern of the relay pad 23 is also changed by electroplating. Must be connected to the external pattern 24.

When such a connection is made, after a molded portion is formed by a resin mold in a later step, the substrate is cut by a dicing device or the like at the mold end surface 13a.
At the connection portion between the pattern of the relay pad 23 and the external pattern, the electroplating pattern is exposed, that is, the plating portion exists near the mold end surface 13a. For this reason, the adhesion between the multilayer laminated substrate and the mold portion is reduced to cause peeling, and the reliability of the semiconductor device itself is reduced due to chip corrosion due to intrusion of moisture or the like from the peeled portion. It becomes a factor.

The reason that the light emitting chip 17 and the IC 20 cannot be directly connected by the gold wire 21 is that if the light emitting chip and the IC are directly connected by the gold wire, a large pad (electrode) is required, thereby increasing the chip size. This can lead to increased costs and costs. Furthermore, light emitting chips and ICs
If these are directly connected by a gold wire, the characteristics of the chip may be adversely affected.

Therefore, in order to prevent such a problem, the second and third embodiments employ a pattern such as a relay pad which is electrically independent on the surface in contact with the resin mold portion of the multilayer laminated substrate. It is formed inside from the end face of the resin mold part, so that pattern formation by electroplating can be realized.

FIG. 4 is a view showing a pattern of a laminated multilayer substrate of a semiconductor device having a mold structure according to a second embodiment of the present invention, and FIG. 4 (a) shows a mounting surface (a resin molded portion of the multilayer laminated substrate). FIG. 4B is a diagram showing a pattern of an intermediate layer, and FIG.
FIG. 4C is a diagram showing a pattern on the back surface. Note that FIG. 4 shows a pattern at a stage before the resin mold portion is formed.

In FIG. 4A, reference numeral 12 denotes a pattern on the front side, 13a denotes an end face of a mold portion, 17 denotes a light emitting chip, and 19 denotes a light emitting chip.
Denotes a light receiving chip, 20 denotes an IC for controlling the light emitting chip 17 and the light receiving chip (photodiode or the like) 19, 2
1 is a gold wire; 29 is a through hole for electrically connecting the component mounting surface pattern 12 and the intermediate layer pattern 30;
3 is a relay pad, 24a is an external pattern, and 25 is a through hole.

In FIG. 4B, reference numeral 30 denotes a pattern on the front side, reference numeral 13a denotes an end face of the molded portion, reference numeral 30a denotes a light emitting chip heat radiation pattern, reference numeral 30b denotes a heat radiation ground pattern, and reference numeral 29 denotes a component mounting surface pattern 12 and an intermediate layer pattern 30. Are electrically connected to each other, 24b is an external pattern for performing electroplating, 25 is a through hole, and 26 is a counterbore hole. The intermediate layer pattern 30 includes a light emitting chip heat radiation pattern 30a, a heat radiation ground pattern 30b,
And the wiring pattern 30c.

FIG. 4C is a view of the back surface of the substrate 11b of the first embodiment, where 11b is the substrate, 16 is the terminal portion, 32 is the pattern on the back surface, 25 is a through hole, and 26 is a counterbore. The holes 24c are external patterns for performing electroplating.

In this embodiment, the pattern 1 shown in FIG.
2 and the relay pad 23 are formed by electroplating.
Base patterns corresponding to these are formed in advance. At this time, the base pattern for the relay pad 23 is a pattern that is connected to a part of the pattern 12 (the light emitting chip mounting portion in the illustrated case).

Then, since the base pattern of the relay pad 23 is connected to the base pattern of the pattern 12, it is connected to the intermediate layer pattern 30 and the back pattern 32 through the through holes 29. Since the intermediate layer pattern 30 is connected to the external pattern 24b and the back pattern 32 is connected to the external pattern 24c, the external pattern 24b or 24c is used to apply a voltage from outside, so that the pattern of the relay pad 23 is applied. The formation can be performed by electrolytic plating together with the pattern 12.

Thereafter, by forming a through hole 25 between the relay pad 23 and the pattern 12 by a drill or the like, the relay pad 23 can be disconnected from the pattern 12 and made electrically independent.

The counterbore hole is for forming the terminal portion 16 of the first embodiment, and is formed by counterbore processing after pattern formation by the electrolytic plating as described above. is there.

If the intermediate layer pattern 30 of FIG. 4B is formed with a conductive and thermal conductive pattern that can sufficiently perform its function, the upper substrate (11a in FIGS. 1 and 2) can be formed. Even if the electrolytic plating is performed after the substrate and the lower substrate (11b in FIGS. 1 and 2) are laminated, the pattern formation of the mounting surface as described above can be performed.

Also, an underlayer pattern for electrolytic plating is formed on both front and back surfaces of the upper substrate (11a in FIGS. 1 and 2) so as to correspond to the patterns shown in FIGS. 4 (a) and 4 (b). Then, after performing electrolytic plating in the same manner as described above, the lower substrate (11b in FIGS. 1 and 2) may be laminated. In this case, the through-hole 25 may be formed before or after lamination of the upper substrate and the lower substrate as long as it is before the resin mold. However, if the through-hole 25 is formed before lamination of the substrate and the through-hole 25 is not formed in the lower side of the substrate, leakage of the molding resin can be prevented at the time of forming the resin mold in a later step. The counterbore hole 26 is preferably formed after lamination of the substrates, because it can be formed in one step and there is no displacement. The external pattern 24a is
If it is not necessary, it need not be formed.

As described above, the resin mold portion is formed on the mounting surface of the multilayer multilayer substrate on which the pattern is formed by the electrolytic plating using the resin mold, and the end surface thereof becomes the mold end surface 13a shown in FIG. And cut at the end face by a dicing device or the like. Then, the electrolytic plating pattern is not exposed from the end surface of the mold portion on the surface where the multilayer multilayer substrate and the mold portion are in contact, that is, electrically independent on the surface where the multilayer multilayer substrate and the mold portion are in contact like a relay pad. The formed electrolytic plating pattern can also be formed inside from the end face of the mold portion, and the semiconductor device having the structure of the first embodiment can be realized by the electrolytic plating pattern.

Further, in the present embodiment, since the through-hole 25 is formed as described above, the molding resin is also filled in the through-hole 25, and the bonding between the substrate and the mold portion is performed. The area can be increased, and the adhesion can be improved and the adhesive strength can be increased.

Next, a third embodiment will be described with reference to FIG.
This will be described with reference to FIG. FIG. 5 is a view showing a pattern of a multilayer multilayer substrate of a semiconductor device having a mold structure according to a third embodiment of the present invention, and FIG. 5 (a) shows a mounting surface (a surface in contact with a resin mold portion of the multilayer multilayer substrate). 5) is a diagram showing a pattern of the intermediate layer, and FIG. 5 (c) is a diagram showing a pattern of the back surface. Note that all of FIGS. 5A and 5B show patterns at a stage before the resin mold portion is formed.

In FIG. 5A, 12 is a pattern on the front side, 13a is an end face of a mold portion, 17 is a light emitting chip, 19 is a light emitting chip.
Denotes a light receiving chip, 20 denotes an IC for controlling the light emitting chip 17 and the light receiving chip (photodiode or the like) 19, 2
1 is a gold wire; 29 is a through hole for electrically connecting the component mounting surface pattern 12 and the intermediate layer pattern 30;
3 is a relay pad, 24a is an external pattern, and 27 is a through hole for electrically connecting the relay pad 23 to the outside.

In FIG. 5B, reference numeral 30 denotes a pattern on the front side, 13a denotes an end face of the molded portion, 30a denotes a light-emitting chip heat-dissipation pattern, 30b denotes a heat-dissipation ground pattern, and 29 denotes a component mounting surface pattern 12 and an intermediate layer pattern 30. Are electrically connected to each other, 24b is an external pattern for electroplating, 26 is a counterbore, 27 and 28
Are through holes and lands for electrically connecting the relay pad 23 to the outside. The intermediate layer pattern 30 is composed of three types: a light emitting chip heat radiation pattern 30a, a heat radiation ground pattern 30b, and a wiring pattern 30c.

FIG. 5C is a diagram of the back surface of the substrate 11b of the first embodiment, where 11b is the substrate, 16 is the terminal portion, 32 is the back surface pattern, 25 is a through hole, and 26 is a counterbore. The holes 24c and 24d are external patterns for performing electroplating. Numerals 27 and 28 are through holes and lands for electrically connecting the relay pad 23 to the outside.

In this embodiment, the pattern 1 shown in FIG.
2 and the relay pad 23 are formed by electroplating.
Base patterns corresponding to these are formed in advance. At this time, in order to electrically connect the base pattern for the relay pad 23 to the outside, the through hole 27 and the land 28
Is formed.

Since the through holes 27 and the lands 28 are connected to the external pattern 24d, by applying a voltage from the outside using the external pattern 24d, the pattern formation of the relay pad 23 and the pattern 12 can be performed. It can be performed by plating. In addition,
As in the second embodiment, the intermediate layer pattern 30 is connected to the external pattern 24b and the back surface pattern 32 is connected to the external pattern 24c. Together with electrolytic plating.

That is, a pattern which is electrically independent on the surface in contact with the mold portion such as the relay pad 23 is connected to a pattern of another layer via a through hole,
The connection can be made via the patterns of the other layers so that the electroplating can be performed, so that the pattern can be formed by the electroplating.

The counterbore holes are for forming the terminal portions 16 of the first embodiment, and are formed by counterboring after forming the pattern by the electrolytic plating as described above. is there.

Also, if the intermediate layer pattern 30 of FIG. 5B is formed with a conductive and thermal conductive pattern that can sufficiently perform its function, the upper substrate (11a in FIGS. 1 and 2) can be formed. Even if the electrolytic plating is performed after the substrate and the lower substrate (11b in FIGS. 1 and 2) are laminated, the pattern formation of the mounting surface as described above can be performed.

Also, an underlayer pattern for electrolytic plating is formed on both the front and back surfaces of the upper substrate (11a in FIGS. 1 and 2) so as to correspond to the patterns shown in FIGS. 5 (a) and 4 (b). Then, after performing electrolytic plating in the same manner as described above, the lower substrate (11b in FIGS. 1 and 2) may be laminated. In this case, after forming the electrolytic plating pattern on the upper substrate alone, when laminating with the lower substrate, if the through hole 27 is not formed in the substrate on the lower side, it is possible to form It can also prevent resin leakage. If the counterbore 26 is formed after lamination,
It is preferable because it can be formed in one step and there is no displacement. The external pattern 24a may not be formed if unnecessary.

As described above, the resin mold portion is formed on the mounting surface of the multilayer multilayer substrate on which the pattern is formed by the electrolytic plating by using the resin mold, and the end surface thereof becomes the mold end surface 13a shown in FIG. And cut at the end face by a dicing device or the like. Then, the electrolytic plating pattern is not exposed from the end surface of the mold portion on the surface where the multilayer multilayer substrate and the mold portion are in contact, that is, electrically independent on the surface where the multilayer multilayer substrate and the mold portion are in contact like a relay pad. The formed electrolytic plating pattern can also be formed inside from the end face of the mold portion, and the semiconductor device having the structure of the first embodiment can be realized by the electrolytic plating pattern.

Further, in the present embodiment, the molding resin is filled into the inside of the substrate by the above-described through holes 27, so that the bonding area between the substrate and the molding portion is increased. The adhesive strength can also be increased.

In the above embodiment, as a substrate material, at least a glass epoxy resin (epoxy resin containing glass fiber) is used in contact with the resin mold portion, and an epoxy resin is used as a molding resin. -It is possible to improve the adhesiveness between the mold parts to increase the adhesive strength thereof, thereby further improving the reliability of the semiconductor device itself.

[0064]

As described above, the semiconductor device according to the first aspect of the present invention is a semiconductor device in which electronic components such as a light emitting chip, a light receiving chip, and an IC are mounted on a substrate and resin-molded. The present invention is characterized in that a multi-layer laminated substrate is used as a substrate, and a resin mold portion extending to an end face of the multi-layer laminated substrate is provided. Therefore, the terminal portion, which had to be disposed outside the mold portion in the conventional example, can be disposed below the mold portion, and the outer shape of the semiconductor device can be reduced.

According to the semiconductor device of the present invention, a predetermined distance is provided between a pattern end of a component mounting surface of the multilayer laminated substrate and an outer end surface of the multilayer laminated substrate. It is a feature. Therefore, since the mold end surface does not cross the component mounting surface pattern, there is no pattern surface having low adhesion to the mold resin at the mold end surface, and the adhesion between the mold portion and the substrate is increased and separation is prevented. Therefore, heat resistance to flow soldering and hand soldering can be improved. Further, in the molding step, the pattern surface is not pressed by the mold, and disconnection of the pattern can be prevented.

According to a third aspect of the present invention, there is provided a heat dissipation pattern which is provided in connection with a pattern on which a component having heat generation such as a light emitting chip or an IC of the multilayer laminated substrate is mounted. It is characterized in that a heat-dissipating ground pattern for assisting the heat dissipation is disposed close to the heat-dissipating ground pattern. Therefore, heat generated from the light emitting chip or the IC can be effectively conducted to the heat radiation ground pattern, and the heat radiation can be improved.
A highly reliable semiconductor device can be obtained.

According to the semiconductor device of the fourth aspect of the present invention, the multilayer laminated board is configured such that the disposed heat radiation pattern and the heat radiation ground pattern are formed by the shape of an uneven surface or the like. The present invention is characterized in that the peripheral distance of the adjacent surface of the pattern is increased. Therefore, it is possible to further improve the heat dissipation of the heat generated from the light emitting chip or the IC, and to obtain a more compact and highly reliable semiconductor device.

Further, according to the semiconductor device of the fifth aspect of the present invention, the resin mold portion formed on the multilayer laminated substrate is provided with a light emitting lens portion and a light receiving lens portion. Is what you do. Therefore, it is possible to obtain a small-sized semiconductor device including a highly reliable optical coupling device.

Further, according to the semiconductor device of the present invention, the pattern of the surface of the multilayer laminated substrate in contact with the resin mold portion is formed by electric field plating, and at least one of the patterns formed by the electric field plating is formed. A part is formed electrically independent from the end face of the resin mold portion on the pattern formation surface, so that the conductivity and the ease of formation can be improved without lowering the reliability. An electroplating pattern having excellent properties can be applied to the surface of the multilayer laminated substrate which is in contact with the resin mold portion.

Further, according to the semiconductor device of the present invention, the electroplating pattern is formed such that the electrically independent electroplating pattern is independent of other electroplating patterns on the formation surface. Through holes are provided in the substrate on which the pattern is formed, and the through holes are characterized by being filled with a molding resin forming the resin mold portion.
The adhesion (adhesion) between the substrate and the resin mold portion can be improved, and the reliability of the semiconductor device can be further improved.

In the method of manufacturing a semiconductor device according to the present invention, a light emitting chip, a light receiving chip, an IC
A method of manufacturing a semiconductor device, comprising mounting a plurality of isoelectronic components and performing resin molding, using a multilayer laminated substrate as the substrate and having a resin molded portion extending to an end face of the multilayer laminated substrate. Forming a pattern on the surface of the substrate in contact with the resin mold portion by electroplating, forming a through hole in the multilayer laminated substrate on which the electroplating pattern is formed, and disconnecting at least a part of the electroplating pattern. And electrically forming the resin mold portion so as to cover the electrically independent electroplating pattern so as not to be exposed on an end face. Therefore, an electroplating pattern having excellent conductivity and ease of formation can be formed on the surface of the multilayer laminated substrate which is in contact with the resin mold portion without lowering the reliability of the semiconductor device.

According to a ninth aspect of the present invention, in a method of manufacturing a semiconductor device, a light emitting chip, a light receiving chip, an IC
A method of manufacturing a semiconductor device, comprising mounting a plurality of isoelectronic components and performing resin molding, using a multilayer laminated substrate as the substrate and having a resin molded portion extending to an end face of the multilayer laminated substrate. A step of forming an electrically independent pattern on the surface of the substrate in contact with the resin mold portion by connecting through a through hole and forming by electroplating, so that the electrically independent electroplating pattern is not exposed on an end face; And forming the resin mold portion. Therefore,
An electroplating pattern excellent in conductivity and ease of formation can be formed on a surface of the multilayer laminated substrate that is in contact with the resin mold portion without lowering the reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram of a semiconductor device having a mold structure according to a first embodiment of the present invention, wherein FIG.
(B) is XX 'sectional drawing of (a).

FIG. 2 is a diagram showing a pattern of a multilayer multilayer substrate of a semiconductor device having a mold structure according to the first embodiment of the present invention, and FIG. 2 (a) is a diagram showing a pattern of a mounting surface;
(B) is a figure which shows the pattern of an intermediate | middle layer, (c) is a figure which shows the pattern of a back surface.

FIG. 3 is a view showing a pattern for electrolytic plating on a mounting surface for describing second and third embodiments of the present invention.

4A and 4B are diagrams showing a pattern of a multilayer multilayer substrate of a semiconductor device having a mold structure according to a second embodiment of the present invention, and FIG. 4A is a diagram showing a pattern of a mounting surface;
(B) is a figure which shows the pattern of an intermediate | middle layer, (c) is a figure which shows the pattern of a back surface.

5A and 5B are diagrams showing a pattern of a multilayered multilayer substrate of a semiconductor device having a mold structure according to a third embodiment of the present invention, and FIG. 5A is a diagram showing a pattern of a mounting surface;
(B) is a figure which shows the pattern of an intermediate | middle layer, (c) is a figure which shows the pattern of a back surface.

6A and 6B are diagrams of a semiconductor device having a mold structure of a conventional example, in which FIG. 6A is an external view, and FIG. 6B is a cross-sectional view taken along the line YY ′ of FIG.

7A and 7B are diagrams illustrating a pattern of a substrate of a semiconductor device having a mold structure of a conventional example, wherein FIG. 7A is a diagram illustrating a pattern on a mounting surface, and FIG. 7B is a diagram illustrating a pattern on a back surface.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device of this invention 11 Substrate 11a Upper substrate 11b Lower substrate 12 Front side pattern 13 Mold part 13a Mold part end face 14 Light emitting lens part 15 Light receiving lens part 16 Terminal part 17 Light emitting chip 19 Light receiving chip 20 IC 21 Gold wire 22 Pattern end of component mounting surface 23 Relay pad 24, 24a, 24b, 24c, 24d External pattern 25 Through hole 27, 29 Through hole 28 Land 30 Intermediate layer pattern 30a Light emitting chip heat radiation pattern 30b Heat radiation earth pattern 30c Wiring Pattern 31 uneven shape 32 back pattern

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 33/00 H01L 31/02 B (72) Inventor Ryoichi Masaki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Junji Oka 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Sharp Corporation

Claims (9)

[Claims] 1. A light emitting chip, a light receiving chip, and an IC on a substrate
What is claimed is: 1. A semiconductor device in which isoelectronic components are mounted and resin-molded, wherein a multi-layer laminated substrate is used as the substrate, and a resin mold portion extending to an end surface of the multi-layer laminated substrate is provided. 2. The semiconductor device according to claim 1, wherein a predetermined distance is provided between a pattern end of a component mounting surface of the multilayer laminated substrate and an outer end surface of the multilayer laminated substrate. . 3. The heat dissipation pattern according to claim 1, wherein the heat dissipation pattern is provided in connection with a pattern on which a component having heat generation, such as a light emitting chip or an IC, of the multilayer laminated substrate is mounted. A semiconductor device, comprising: disposing a heat-dissipating ground pattern to assist in close proximity. 4. The semiconductor device according to claim 3, wherein the heat dissipation pattern and the heat dissipation ground pattern provided on the multilayer laminated substrate are formed on the adjacent surfaces of the two patterns by a shape such as an uneven surface. A semiconductor device having an increased peripheral edge distance. 5. The semiconductor device according to claim 1, wherein a light emitting lens portion and a light receiving lens portion are provided on the resin mold portion formed on the multilayer laminated substrate. 6. The semiconductor device according to claim 1, wherein a pattern of a surface of said multilayer laminated substrate which is in contact with said resin mold portion is formed by electric field plating, and at least a part of the pattern formed by said electric field plating is formed by pattern formation. A semiconductor device, wherein the semiconductor device is formed electrically independent from the end surface of the resin mold portion from the end surface. 7. The semiconductor device according to claim 6, wherein said electroplating pattern is formed such that said electrically independent electroplating pattern is independent of another electroplating pattern on its forming surface. A semiconductor device, wherein a through-hole is provided in a substrate, and the through-hole is filled with a mold resin forming the resin mold portion. 8. A light-emitting chip, a light-receiving chip, and an IC on a substrate
A method of manufacturing a semiconductor device comprising mounting isoelectronic components and resin molding, using a multilayer laminated substrate as the substrate, and having a resin molded portion extending to an end face of the multilayer laminated substrate, Forming a pattern by electroplating on the surface in contact with the resin mold portion, forming a through hole in the multilayer laminated substrate on which the electroplating pattern is formed, and disconnecting at least a part of the electroplating pattern. A method of manufacturing a semiconductor device, comprising: a step of electrically insulated; and a step of forming the resin mold portion by covering the electrically insulated electroplating pattern so as not to be exposed on an end face. 9. A light emitting chip, a light receiving chip, and an IC on a substrate
A method of manufacturing a semiconductor device comprising mounting isoelectronic components and resin molding, using a multilayer laminated substrate as the substrate, and having a resin molded portion extending to an end face of the multilayer laminated substrate, Forming an electrically independent pattern on the surface in contact with the resin mold portion by through-holes and forming the same by electroplating, so that the electrically independent electroplating pattern is not exposed on the end face. A method of manufacturing a semiconductor device, comprising a step of covering and forming the resin mold portion.