JP2000012764A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower manufacturing cost and constitute a plurality of integrated circuit chips by a method, wherein an external pad connected to an external terminal provided in a main integrated circuit chip and a function extending pad connected to a sub-integrated circuit chip for extending a main integrated circuit function are provided. SOLUTION: A processor chip (main integrated circuit chip) 1 has an external pad 2 connected to an external terminal and additionally a function expanding pad 3 connected to a sub-integrated circuit chip for expanding the function of the processor chip 1. The processor chip 1 has 8 extended slots 4-1 to 4-8 constituted by the function extending pad 3, and at most 8 sub-integrated circuit chips can be connected thereto. A SRAM chip is connected onto the processor chip 1 via the function extending pad 3, so that such a processor chip 1 can increase the capacity of a cache memory, namely function expansion is made possible, so that it becomes unnecessary to secure extended slots in a package accommodating it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device constituted by one or more integrated circuit chips.

[0002]

2. Description of the Related Art At present, electronic equipment systems represented by computers and the like include various LSs such as processors and memories.
I on a circuit board called a motherboard.

[0003] In such electronic devices, in recent years, multifunctionality, high-speed operation, miniaturization, cost reduction, and the like have been rapidly advanced. This progress largely depends on miniaturization and high performance of LSIs.

[0004] Further, multi-functionality and high-speed operation of electronic equipment,
In order to accelerate the progress of miniaturization and price reduction, there is a movement to integrate a system configured on a motherboard into one chip. This is a technology called system LSI.

The problem of the system LSI is how to integrate a microprocessor operating at a very high speed, a memory having a very large scale, an analog circuit having a very high sensitivity, etc. on a single chip at a large scale and at a low cost. . In order to solve this problem, research and development are being promoted in LSI manufacturers. At present, a device that integrates a processor, a memory, an analog circuit, and the like on a small scale has reached a level sufficient for practical use. However, the integration of large-scale systems has not yet reached the practical stage. Moreover, it is a fact that research and development costs a lot of money.

[0006] Therefore, an LSI maker has decided to use a system LSI.
Of multi-chip package (MCP) product that accommodates multiple LSI chips in one package and multi-chip module (MCM) product that sets multiple LSI chips on a circuit board for system configuration We are promoting.

[0007] These MCPs and MCMs have already been put to practical use, for example, in processors and the like, and have sufficiently contributed to multifunction, high-speed operation, miniaturization, and cost reduction of electronic equipment. A typical example of the MCP is shown in FIG.

As shown in FIG. 18A, a processor chip 101 and an SRAM chip 102 as a cache memory are housed in a single ceramic package 103 in a bare state.

The problem of the MCP and the MCM is that, among the good chips, particularly excellent chips (Known Good Diode)
e: KGD) must be selected and assembled. In the case of MCP and MCM, the yield rapidly deteriorates unless a good chip is selected and assembled. As a result, manufacturing costs are relatively high, and product prices have to be set higher. Higher product prices delay market penetration and make less contribution to technological advances.

Therefore, as shown in FIG. 18B, a product containing only the processor chip 101 without mounting the SRAM chip 102 as a cache memory is produced simultaneously. Since such products are not MCPs,
There is no need to select and assemble KGD from non-defective chips, and it is sufficient to assemble non-defective chips as existing products. This significantly reduces manufacturing costs.

Therefore, a product having the same performance as the product shown in FIG. 18A can be provided to the market at a lower price (a popular product). In contrast to such a product, the product shown in FIG. 18A is a function-extended product in which the function is extended.

However, in the products shown in FIGS. 18A and 18B, an additional slot 104 for adding a cache memory must be provided in the package 103, which sufficiently meets the demand for miniaturization. It is hard to say that there is. In addition, since the size of the package 103 increases, the price of the package 103 naturally increases. In particular, in a high-end package such as a ceramic package, the manufacturing cost is considerably increased.

Although there is a means for separately preparing a package for a widespread product and a package for a function expansion product, a corresponding burden is imposed on a package maker.
A remarkable reduction in manufacturing cost cannot be expected. Even for LSI manufacturers, merely increasing the number of types of packages deteriorates productivity, and there is not much advantage that the manufacturing cost can be reduced.

[0014]

As described above, conventional MCP products and MCM products tend to have relatively high manufacturing costs. The present invention has been made in view of the above circumstances, and has as its object to reduce the manufacturing cost.
An object of the present invention is to provide a semiconductor integrated circuit device constituted by the above integrated circuit chips.

[0015]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a main integrated circuit chip and an external device connected to an external terminal provided on the main integrated circuit chip. A pad and a function extension pad provided on the main integrated circuit chip and connected to a sub-integrated circuit chip for expanding the function of the main integrated circuit chip are provided.

Further, the main integrated circuit chip has a function of becoming a product, and the main integrated circuit chip is a standard product constituted by itself and the standard product according to the connection of the sub integrated circuit chip. It is characterized by being replaced with a function expansion product that expands the functions of.

Further, the sub-integrated circuit chip has a function of becoming a product, and the sub-integrated circuit chip is connected to the standard integrated circuit chip and the main integrated circuit chip so as to form the main integrated circuit. It is characterized by being replaced with a function expansion component for expanding functions.

The surface of the main integrated circuit chip on which the function expansion pads are formed is flattened. Further, another aspect of the semiconductor integrated circuit device according to the present invention includes a main integrated circuit chip, an external pad provided on the main integrated circuit chip, connected to an external terminal, and provided on the main integrated circuit chip. A function expansion pad for expanding the function of the main integrated circuit chip; and a sub integrated circuit chip electrically connected to the function expansion pad for expanding the function of the main integrated circuit chip. It is characterized by having.

Further, the main integrated circuit chip is bare and the sub integrated circuit chip is housed in a package. Further, the package accommodating the sub-integrated circuit chip is a chip size package.

Further, the chip size package includes a wiring board for electrically connecting external pads provided on the sub-integrated circuit chip to function extension pads provided on the main integrated circuit chip. It is characterized by having.

The wiring board includes a function expansion wiring board used for connecting the sub-integrated circuit chip to the main integrated circuit chip, and a commercially available wiring board used for marketing the sub-integrated circuit chip. And is provided.

In the semiconductor integrated circuit device having the above configuration, the main integrated circuit chip has function expansion pads in addition to the external pads connected to the external terminals. By connecting a sub-integrated circuit chip for expanding the function of the main integrated circuit chip to the function expansion pad, the function of the main integrated circuit chip can be expanded. For this reason, there is no need to provide a slot for expanding the function in addition to the main integrated circuit chip in the package, and the package can be downsized. Since the size of the package can be reduced as described above, the manufacturing cost of a semiconductor integrated circuit device including one or more integrated circuit chips can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a perspective view of a processor chip according to a first embodiment of the present invention.

As shown in FIG. 1, a processor chip (main integrated circuit chip) 1 includes an external pad 2 connected to an external terminal (not shown) and a sub-integrated circuit chip for extending the function of the processor chip 1. Has a function expansion pad 3 connected to the. The processor chip 1 has eight additional slots 4-1 to 4 formed by function expansion pads 3.
-8, so that up to eight sub-integrated circuit chips can be connected. Hereinafter, the function expansion of the processor chip 1 will be described as an example of a case where a cache memory is connected to the additional slots 4-1 to 4-8 to increase the capacity of the cache memory.

FIGS. 2A and 2B are perspective views showing states in which the functions of the processor chip 1 are expanded.
As shown in FIGS. 2A and 2B, an SRAM chip (sub-integrated circuit chip) 5 is provided as a cache memory via a function expansion pad 3 provided in each of the additional slots 4-1 to 4-8. , Are connected to the processor chip 1. For connection between the processor chip 1 and the SRAM chip 5, a so-called flip-chip system is used in which connection is made using solder balls.

Here, assuming that the capacity of the SRAM chip 5 is 8M bits, in FIG. 2A, since two SRAM chips 5 are connected, the cache memory can be increased by 2M bytes. In FIG. 2B, eight SRAM chips 5 are used by using all the additional slots 4-1 to 4-8.
Is connected, the cache memory can be increased by 8 Mbytes.

As described above, according to the processor chip 1 according to the first embodiment, the SR
By connecting the AM chip 5 on the processor chip 1, the capacity of the cache memory can be increased, that is, the function can be expanded.
There is no need to secure additional slots. Therefore,
The size of the package can be reduced, and the manufacturing cost can be reduced.

Further, from the processor chip 1 according to the first embodiment, a standard product (standard processor) constituted only by the processor chip 1 without increasing the cache memory, and the cache memory is sequentially increased from 1 Mbyte to a maximum of 8 Mbyte. It is possible to obtain a total of 9 types of products, that is, eight types of function expansion products (function expansion processors) which are added and extend the functions of the processor chip 1. Moreover, these nine types of products can be deployed in one type of package,
Productivity also increases.

Therefore, a semiconductor integrated circuit device composed of one or more integrated circuit chips can be produced at a lower manufacturing cost. Next, an example of a suitable production flow using the processor chip 1 according to the first embodiment will be described.

FIG. 3 is a flowchart showing an example of a production flow using the processor chip 1 according to the first embodiment of the present invention. Reference numeral 10 shown in FIG. 3 is a standard product (standard processor) composed of only the processor chip 1
Production flow, reference numeral 11 denotes S
A production flow of a function extension product (function extension processor) to which the RAM chip 5 is connected, and reference numeral 12 is a production flow of a standard product (standard SRAM) including only the SRAM chip 5.

As shown in FIG. 3, the SRAM chip 5 used to extend the function of the processor chip 1 is not dedicated to the function extension, but is manufactured as an SRAM product by itself. As described above, the SRAM chip 5 is not developed exclusively for the function extension, but is developed on the assumption that the SRAM chip 5 is actually used as an SRAM product. This allows
For LSI manufacturers, development costs for new products can be reduced.

In addition, existing SRs that are actually commercialized
The function of the processor chip 1 can be extended by utilizing the AM chip. In this case, there is no need to newly develop an SRAM chip, so that there is no development cost for function expansion.

As described above, the SRAM chip 5 for extending the function of the processor chip 1 (main integrated circuit chip)
(Sub-integrated circuit chip) to have a function as a product.
Further, an SRAM product including only the SRAM chip 5 is produced. This allows L to produce a wide variety of products
For SI manufacturers, the total development cost can be reduced.

Therefore, if a processor product equipped with the processor chip 1 according to the first embodiment is produced according to the production flow shown in FIG. 3, not only this processor product but also other products, the first embodiment Then, SRAM
Manufacturing costs for products can also be reduced.

[Second Embodiment] In a processor chip 1 according to the present invention, an SRAM chip 5 is mounted thereon. Therefore, it is better that the surface on which the function expansion pad 3 is formed is flattened with high accuracy.

FIGS. 4A and 4B respectively show the second
FIG. 3 is a cross-sectional view of the semiconductor integrated circuit device according to the embodiment.
As shown in FIG. 4A, the surface of the insulating film 20 on which the function expansion pad 3 is formed is flattened. This flattening requires C
The MP method may be used. Arrows in the figure indicate surfaces planarized by the CMP method.

Further, as shown in FIG. 4B, the function expansion pad 3 is formed together with the insulating film 20 on which the function expansion pad 3 is formed.
The planarization may be performed by the MP method. This is the so-called damascene method. Arrows in the figure indicate surfaces planarized by the CMP method.

By flattening the surface of the processor chip 1 on which the function expansion pads 3 are formed, the SRAM chip 5 and the function expansion pads 3 can be more reliably connected. Therefore, when the functions of the processor chip 1 are expanded, the yield can be improved, and the manufacturing cost can be reduced.

Further, since the SRAM chip 5 and the function expansion pad 3 can be more securely connected, the effect of improving the reliability of the function expansion processor product, particularly the reliability related to the device life, can be expected at the same time.

[Third Embodiment] After completion of the wafer process, as shown in FIG. 3, a chip is subjected to a forced deterioration test called burn-in. Thereafter, the chips are tested, and only those that have been operated reliably are determined to be good chips, and the process proceeds to the next assembly process.

When producing an extended function product, a particularly good chip (Known Good Die: K)
GD). This KGD standard is extremely high. This is because bare chip shipment is assumed. That is, the chip is supplied to the user naked, and the assembly of the MCM is left to the user so that the user can freely perform the assembly according to the user's own preference.

The connection between the processor chip 1 according to the present invention and the SRAM chip 5 for expanding its function is of a flip-chip type. Therefore, a user who has a solder reflow device used for MCM assembly can connect the SRAM chip 5 to the processor chip 1 by himself / herself. Therefore, also in the present invention, the connection between the processor chip 1 and the SRAM chip 5 can be left to the user.

By the way, the reason why the KGD standard is excessively high is that a distribution system called “bare chip shipment” has just been born. Also, the MCM process is a relatively new technology and is not completely completed. In particular, the yield of MCM changes more than expected depending on the quality of KGD. The cause is not yet clear. Since the cause is not clear, the KGD standard must be set too high.

Among the LSIs, it is expected that a very small amount of KGD can be obtained from a single wafer in a memory LSI manufactured by using the most advanced technology. For this reason, when the SRAM chip 5 is manufactured using the most advanced technology, it is expected that considerable manufacturing costs will be required to obtain eight KGDs as shown in FIG. 2B. Is done. In this case, an inexpensive product cannot be supplied to the user.

One example of solving such a situation is the third embodiment. FIG. 5 is a flowchart showing a production flow according to the third embodiment of the present invention. Reference numeral 10 shown in FIG. 5 is a production flow of a standard product (standard processor) composed only of the processor chip 1, and reference numeral 11 is a function extension product (function extension processor) in which the SRAM chip 5 is connected to the processor chip 1. Production flow,
Reference numeral 12 is a production flow of a standard product (standard SRAM) including only the SRAM chip 5.

As shown in FIG. 5, in the third embodiment,
A non-defective chip is assembled to the processor chip 1 instead of the KGD, and an SRAM product in which this is packaged is connected.

The packaging technology is a well-established technology, and its standard is not set too high unlike KGD. That is, the criteria for packaged products are much more relevant than the criteria for KGD in the exploration phase.

As described above, according to the third embodiment, the packaged product is used as a component for function expansion.
The probability that a good chip is wasted can be reduced as compared with the case where the KGD is used as a component for function expansion. Therefore, it is possible to further reduce the manufacturing cost of the function expansion product.

[Fourth Embodiment] Next, an example of a package suitable for a product connected to a main integrated circuit chip for function expansion will be described as a fourth embodiment.

FIG. 6 is a diagram showing an SRAM product for function expansion according to a fourth embodiment of the present invention. FIG. 6A is a sectional view and FIG. 6B is an exploded view. FIG. 6 (A),
As shown in (B), the preferred package is
It is a chip size package (CSP). The SRAM chip 5 has connection solder balls 34. The connection solder balls 34 are connected to the connection pads 33 formed on the wiring board 31 by using a flip chip method. The connection between the wiring board 31 and the SRAM chip 5 is molded with a molding resin 35.

Solder ball 32 formed on wiring board 31
Are connected to the function expansion pads 3 of the processor chip 1 in a flip-chip manner. This connection is performed by placing the solder ball 32 on the function expansion pad 3 and then melting the solder ball 32 by a solder reflow device.

Such a CSP has a size substantially equal to the size of a chip. Therefore, its size is very small as compared with other packages, for example, QFPs. Therefore, more connections can be made on the processor chip 1.

Further, since the CSP has the wiring board 31,
The arrangement of the external terminals, that is, the solder balls 32, is
The arrangement of the solder balls 34 of the M chip 5 may be exactly the same. In this way, the present invention can be applied to both the case where the SRAM chip 5 is connected in a bare chip state and the case where the SRAM chip 5 is connected in a state where the SRAM chip 5 is accommodated in a CSP, which is convenient.

FIGS. 7A and 7B respectively show a processor chip 1 using an SRAM product according to the fourth embodiment.
FIG. 4 is a perspective view showing a state where the function of FIG. FIG. 7 (A)
Here, two SRAM products (CSP) 5 are connected to the processor chip 1 using two additional slots. Assuming that the SRAM product (CSP) 5 has a capacity of 8 Mbits, the product shown in FIG. 7A is a cache memory 2 Mbyte extension product.

In FIG. 7B, eight SRAs are provided in the processor chip 1 by using all eight additional slots.
M product (CSP) 5 is connected. Therefore, FIG.
The product shown in (B) is an extended product of 8 Mbytes of cache memory.

As described above, also in the fourth embodiment,
As in the first embodiment, in addition to a standard product including only the processor 1, a function expansion product corresponding to the number of connected SRAM products (CSP) 5 can be obtained.

[Fifth Embodiment] The function expansion according to the present invention can be applied not only to the addition of a cache memory but also to other function expansions. A representative example will be described as a fifth embodiment.

FIG. 8 is a perspective view of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. As shown in FIG. 8, the processor chip 1 includes a function expansion pad 3 connected to a sub-integrated circuit chip for expanding the function of the processor chip 1 in addition to an external pad 2 connected to an external terminal (not shown). have. The processor chip 1 is provided with six additional slots 4-1 constituted by function expansion pads 3.
1 to 4-16, so that up to six sub-integrated circuit chips can be connected.

In the fifth embodiment, the additional slot 4
A graphics controller is connected to -11, and an interface is connected to the additional slot 4-12. The interface is connected when the operating standard (operating frequency or operating power supply voltage) between the graphics controller and the processor chip 1 is different or the data transfer standard (number of input / output bits) between the graphics controller and the processor chip 1 is different. Is what is done. For this purpose, the interface incorporates a frequency converter circuit, a voltage converter circuit, a multi / demultiplexer, and the like.

An image memory is connected to the additional slots 4-13 and 4-14, an MEPG is connected to the additional slot 4-15 for image data communication, and a cache memory is connected to the additional slot 4-16. Has become.

In the fifth embodiment, the graphics controller, interface, image memory,
MPEG and a cache memory are prepared as sub-integrated circuit chips, respectively. By connecting these sub-integrated circuit chips to the processor chip 1 which is the main integrated circuit chip, a function expansion product of a type corresponding to the combination is prepared.

The standard product is a product composed of only the processor chip 1 shown in FIG. Hereinafter, an example in which the function of the main integrated circuit chip (processor chip 1) is expanded will be described on the assumption that each sub-integrated circuit chip is a CSP as in the fourth embodiment.

FIGS. 9A and 9B are perspective views showing a product having an extended graphics function. As shown in FIG. 9A, a graphics controller product (CSP) 51 is connected to the processor chip 1 by using an additional slot 4-11. As a result, the graphics function is extended to the processor chip 1 and becomes the graphics function extended product (I).

This graphics function expansion product (I)
No interface is connected. This is because the operation standard and data transfer standard of the graphics controller product (CSP) 51 are the same as the operation standard and data transfer standard of the processor chip 1.

On the other hand, in the graphics function expansion product (II) shown in FIG. 9B, an interface product (CSP) 52 is connected to the processor chip 1 by using an additional slot 4-12. This is because the operating standard and data transfer standard (hereinafter referred to as “standard”) of the graphics controller product (CSP) 51 ′ are
This is because it does not conform to the standard.

The interface product (CSP) 52 is
It has the function of electrically connecting those that do not conform to such standards. Such interface products (CS
The main reason for providing the additional slot 4-12 for connecting the P) 52 is as follows.

In the present invention, as described in the third embodiment, it is assumed that not only the connection between the main integrated circuit chip and the sub-integrated circuit chip is made by the manufacturer, but also that it is left to the user. The user can select the LS according to his preference.
I want a product. In other words, the user can use one manufacturer's LS
Not only I products but also LSI products from various manufacturers.

It is presumed that it will be difficult for a single maker to prepare all the LSI products as technology becomes more complex. In particular, the development of memories, processors, and graphics controllers requires a high degree of technical capability. For this reason, it is expected that it will be extremely difficult to prepare all of these LSI products by one manufacturer. Therefore, the tendency for users to seek LSI products from various manufacturers is increasing. As users demand LSI products from various manufacturers, it is sufficient that the standard of the main integrated circuit chip (processor chip 1) and the standard of the sub-integrated circuit chip (graphics controller product (CSP) 51 ') do not match. You have to assume.

In the fifth embodiment, an additional slot 4-12 for connecting an interface product (CSP) 52 is provided.
Is provided, the main integrated circuit chip and the sub-integrated circuit chip can be connected to each other even when the standards are different from each other. Therefore, it is possible to maintain the advantage that the user can assemble the apparatus according to the user's preference.

Further, it is not necessary for the manufacturer to newly develop a sub-integrated circuit chip conforming to the standard of the main integrated circuit chip, so that there is an advantage that the development cost can be reduced.

Further, if there is already a sub-integrated circuit chip which does not conform to the standard of the main integrated circuit chip and satisfies the specification required by the user, it can be connected to the main integrated circuit chip to produce a product. This also has the effect of reducing the turnaround time from order receipt to delivery.

FIG. 10A shows that the graphics function expansion product (II) has additional slots 4-13, 4-1.
4 shows a product in which two VRAM products (CSPs) 53 are added. The VRAM product (CSP) 53 functions as an image memory.

The capacity of the VRAM product (CSP) 53 is 8M
If it is a bit, it is a function expansion product having a 2 Mbyte image memory. FIG. 10B is a view similar to FIG.
The products shown in (1) and (2) use the additional slots 4-15 and 4-16, respectively, and add the MEPG product (CSP) 54 and the SRAM product (CSP) 5 respectively.

The MPEG product (CSP) 54 is for image data communication, and particularly has a function of compressing image data for communication. The SRAM product (CSP) 5 is a cache memory of the processor chip 1.

Assuming that the capacity of the SRAM product (CSP) 5 is 8M bits, it has a cache memory of 1M bytes. In addition, because it has an MPEG product (CSP) 54,
It is a function expansion product that combines image data communication functions.

As described above, according to the present invention, not only the cache memory of the processor can be expanded, but also the function of taking in the system of the electronic device in which the processor is used can be expanded.

[Sixth Embodiment] When commercializing the SRAM chip 5, it is assumed that the wiring arrangement of the circuit board on which this product is mounted is different from the arrangement of the function expansion pads 3 of the processor chip 1. Is done.

In such a case, the arrangement of the pads of the SRAM chip 5 is changed, that is, by using another mask set,
Commercially available SRAM chips and SRAM chips for function expansion must be manufactured. This complicates the wafer process. In particular, the number of types of mask sets used in the photolithography process increases, and it is necessary to manage all of these mask sets, so that the productivity of the SRAM chip is significantly impaired.

Further, since a high level of technology is required to develop and manufacture a new mask set used in the photolithography process, a corresponding manufacturing cost is required. An example of solving these circumstances is the sixth embodiment.

The sixth embodiment is similar to the fourth embodiment, except that the SRAM chip 5 is connected to the processor chip 1 as a CSP product. FIG. 11 shows a sixth embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a semiconductor integrated circuit device according to an embodiment.

As shown in FIG. 11, the CSP product has a wiring board 31. In the sixth embodiment, the wiring board 31 is provided with two types, a commercial wiring board 31A and a function expansion wiring board 31B. The commercially available wiring board 31A is used when an SRAM product using the SRAM chip 5 is marketed. The function extension wiring 31B is used when connecting the SRAM chip 5 to the processor chip 1.

The arrangement pitch P1 of the solder balls 32 on the commercial wiring board 31A matches the arrangement pitch of the wiring of the circuit board (not shown), and the arrangement pitch P1 of the connection pads 33.
2 is the arrangement pitch P of the solder balls 34 of the SRAM chip 5
It has been adapted to 3.

The solder balls 32 of the function expansion wiring board 31B
Is arranged at a pitch corresponding to the arrangement pitch of the function expansion pads 3 of the processor chip 1, and the arrangement pitch P5 of the connection pads 33 is adjusted to the arrangement pitch P3 of the solder balls 34 of the SRAM chip 5. Have been.

As described above, the wiring board 31 of the CSP product
In addition, by providing a commercially available wiring board 31A and a function expansion 31B respectively, from one type of mask set,
It is possible to obtain an SRAM product that can be connected to both the circuit board having different arrangement pitches and the processor chip 1.

In this case, the number of types of wiring boards 31 increases, but the deterioration in productivity can be reduced more than the number of types of mask sets used in the photolithography process increases. Further, the manufacturing cost of the wiring board 31 is lower than that of a mask set for photolithography. Naturally SRAM chip 1
Lower than.

Therefore, according to the sixth embodiment, it is possible to further reduce the manufacturing cost. The size of the additional slot 4 provided in the main integrated circuit chip;
The sizes of the sub-integrated circuit chips connected here may be different from each other. Also in this case, the sixth embodiment can be modified and applied as follows.

FIG. 12 is a sectional view showing a modification of the semiconductor integrated circuit device according to the sixth embodiment of the present invention. FIG.
As shown in FIG. 2, the size of the commercially available wiring board 31A is SR
The size of the AM chip 5 is almost the same. On the other hand, the size of the function expansion wiring board 31B is
And larger than the commercial wiring board 31A.

By providing the commercially available wiring board 31A and the function expansion wiring board 31B in this manner, even the SRAM chip 5 having a size different from the size of the additional slot 4 can be connected to the processor chip 1.

[Seventh Embodiment] Next, an example of a package accommodating a processor product according to the present invention will be described as a seventh embodiment of the present invention.

This description assumes that each sub-integrated circuit chip is a CSP as in the fourth embodiment. FIG. 13A is a plan view showing a state where the processor product according to the present invention is housed in a PGA type package. Further, FIG. 13B shows B in FIG.
It is sectional drawing which follows the -B line.

As shown in FIGS. 13A and 13B, the PG
The processor chip 1 to which the SRAM product (CSP) 5 is connected is accommodated in the A-type ceramic package 61. The external pads 2 of the processor chip 1 are electrically connected to wiring patterns (not shown) of the package 61 by bonding wires 62. The wiring pattern (not shown) is electrically connected to the external pins 63 of the package 61. Reference numeral 64 is a cap for hermetic sealing.

As described above, the processor according to the present invention comprises:
It can be accommodated in an existing PGA type ceramic package. Therefore, it can be connected to the motherboard constituting the system of the electronic device in the same manner as in the related art.

Also, the processor according to the present invention has a PG
Not only the A type ceramic package but also other existing packages can be accommodated. FIG. 14A shows an example in which the processor according to the present invention is housed in a BGA type ceramic package 71, and FIG. 14B shows an example in which the processor is housed in a mold package (QFP type) 72.

Further, the processor according to the present invention has a TA
It is also possible to use the B method. FIG. 14 (C) shows TAB
This is an example of a method. As shown in FIG. 14C, the external pads 2 of the processor chip 1 are electrically connected to the thin-film conductor patterns 74 formed on the TAB tape 73.
Reference numeral 75 denotes a potting resin for isolating a connection portion between the external pad 2 and the thin film conductor pattern 74 from the outside.

FIG. 14D shows an example in which the processor according to the present invention is housed in a chip size package 76. The chip size package 76 shown in FIG.
Are connected to a motherboard constituting a system of an electronic device by a flip-chip method.

As described above, the processor according to the present invention comprises:
It can be put into various existing packages and commercialized. [Eighth Embodiment] A processor product according to the present invention comprises:
Like the existing LSI chip, it is also possible to form a multi-chip package (MCP) or a multi-chip module (MCM). Hereinafter, an example in which the processor product according to the present invention is an MCP or an MCM will be described as an eighth embodiment of the present invention. Also in this description, each of the sub-integrated circuit chips is referred to as a CSP as in the fourth embodiment.
Is assumed.

FIG. 15 is a plan view when a processor product according to the present invention is a multi-chip package product. As shown in FIG. 15, an SRAM product (CSP) 5 is connected to a ceramic package 61, and four processor chips 1 with expanded functions are accommodated therein.
This results in an MCP product.

As described above, if the processor product according to the present invention is an MCP product, it becomes possible to integrate many functions more compactly than a conventional MCP product. FIG. 16 is a plan view when a processor product according to the present invention is a multi-chip module product.

As shown in FIG. 16, an SRAM product (CS
P) 5, the processor chip 1 whose function is expanded and the processor chip 1 described in the fifth embodiment are each connected to a circuit board 81 for system configuration to constitute a multi-chip module product. ing.

As described above, if the processor product according to the present invention is an MCM product, many functions can be integrated more compactly as in the MCP product. Further, the MCM product shown in FIG. 16 may be housed in a ceramic package 61 as shown in FIG. This is a product called a multi-chip module package product.

Although the present invention has been described with reference to the first to eighth embodiments, the present invention is not limited to these embodiments, and various modifications are possible. For example, in the above embodiment, the processor chip is exemplified as the main integrated circuit chip. However, the main integrated circuit chip may be changed to an ultra-large-scale memory chip having a gigabit class storage capacity.

In this case, a very large-scale memory chip
By connecting the sub-integrated circuit chip to extend the function, not only the function as a memory product but also the peripheral system is taken in, and an LSI product that integrates more advanced functions and ultra-large memory at the same time, It can be provided at a lower cost.

[0103]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device including one or more integrated circuit chips, which can reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a perspective view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIGS. 2A and 2B are perspective views showing states in which functions of the semiconductor integrated circuit device according to the first embodiment are expanded.

FIG. 3 is a flowchart showing a production flow using the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 4A is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 4B is a modification of the semiconductor integrated circuit device according to the second embodiment of the present invention; Sectional drawing which shows an example.

FIG. 5 is a flowchart showing a production flow of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 6A is a sectional view of a cache memory included in a semiconductor integrated circuit device according to a fourth embodiment of the present invention, and FIG. 4B is a semiconductor according to the fourth embodiment of the present invention; FIG. 2 is an exploded view of a cache memory included in the integrated circuit device.

FIGS. 7A and 7B are perspective views showing states in which the function of a main integrated circuit chip is expanded using a semiconductor integrated circuit device according to a fourth embodiment.

FIG. 8 is a perspective view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIGS. 9A and 9B are perspective views showing states in which functions of a semiconductor integrated circuit device according to a fifth embodiment are expanded.

FIGS. 10A and 10B are perspective views showing states in which functions of a semiconductor integrated circuit device according to a fifth embodiment are expanded.

FIG. 11 is a diagram showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 12 is a diagram showing a modification of the semiconductor integrated circuit device according to the sixth embodiment of the present invention.

FIG. 13A is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIG.
Sectional drawing which follows the BB line | wire in 3 (A).

FIGS. 14A to 14D are cross-sectional views showing modified examples of the semiconductor integrated circuit device according to the seventh embodiment of the present invention.

FIG. 15 is a plan view when the semiconductor integrated circuit device according to the present invention is used as a multi-chip package product.

FIG. 16 is a plan view when the semiconductor integrated circuit device according to the present invention is used as a multi-chip module product.

FIG. 17 is a plan view when the semiconductor integrated circuit device according to the present invention is used as a multi-chip module package product.

FIGS. 18A and 18B are plan views of a conventional multichip package product.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor chip, 2 ... External pad, 3 ... Function expansion pad, 4-1 to 4-8, 4-11 to 4-16 ... Expansion slot, 5 ... SRAM chip / SRAM product (CSP), 10 ... Standard Processor product production flow, 11: Function expansion processor product production flow, 12: Standard SRAM product production flow, 20: insulating film on which function expansion pads are formed, 31: wiring board, 31A: commercial wiring board, 31B: function Extension wiring board, 32: solder ball, 33: connection pad, 34: connection solder ball, 35: mold resin, 51, 51 ': graphics controller product (CS
P), 52: Interface product (CSP), 53: VRAM product (CSP), 54: MPEG product (CSP), 61: Ceramic package (PGA), 71: Ceramic package (BGA), 72: Mold package (QFP) , 75: Potting resin (TAB), 76: Chip size package (CSP), 81: Circuit board for system configuration (MCM).

Claims (9)

[Claims] 1. A main integrated circuit chip, an external pad provided on the main integrated circuit chip and connected to an external terminal, and a function of the main integrated circuit chip provided on the main integrated circuit chip is extended. And a function expansion pad connected to the sub-integrated circuit chip. 2. The main integrated circuit chip has a function to be a product, and the main integrated circuit chip is a standard product constituted by itself and the standard product according to the connection of the sub integrated circuit chip. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is replaced with a function expansion product having an expanded function. 3. The sub-integrated circuit chip has a function of becoming a product, and the sub-integrated circuit chip is connected to the main integrated circuit chip as a standard product and the main integrated circuit chip. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is replaced with a function expansion component for expanding a function. 4. The semiconductor integrated circuit device according to claim 1, wherein a surface of said main integrated circuit chip on which said function expansion pads are formed is flattened. . 5. A main integrated circuit chip, an external pad provided on the main integrated circuit chip and connected to an external terminal, and a function of the main integrated circuit chip provided on the main integrated circuit chip is extended. And a sub-integrated circuit chip electrically connected to the function-expanding pad for expanding the function of the main integrated circuit chip. apparatus. 6. The semiconductor integrated circuit device according to claim 5, wherein the main integrated circuit chip is a bare, and the sub integrated circuit chip is housed in a package. 7. The semiconductor integrated circuit device according to claim 6, wherein the package accommodating the sub-integrated circuit chip is a chip size package. 8. The chip size package includes a wiring board for electrically connecting external pads provided on the sub-integrated circuit chip to function expansion pads provided on the main integrated circuit chip. 9. The semiconductor integrated circuit device according to claim 7, comprising: 9. A wiring board used for connecting the sub-integrated circuit chip to the main integrated circuit chip, and a commercially available wiring board used for selling the sub-integrated circuit chip. 9. The semiconductor integrated circuit device according to claim 8, comprising: