JP2000010917A - Clock synchronous serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock synchronous serial interface circuit which can operate a slave connected to a master by using either one of two types of clocks. SOLUTION: This clock synchronous serial interface circuit is placed at the slave side of a system which sends serial clocks to a slave from a master and also makes the master select a slave by a slave selection signal for transmission and reception of the serial signals. A serial clock polarity discrimination circuit 1 is added to the said serial interface circuit to automatically discriminate the polarity of the serial clocks sent from the master based on the slave selection signal together with the clock generation means (an inverter 3 and a selector 2) which generate the clocks of the types necessary for the slave from the serial clocks received from the master based on the discrimination result of the circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock synchronous serial interface circuit provided in a peripheral device of a CPU.

[0002]

2. Description of the Related Art For example, when a peripheral device such as a memory is connected to a CPU, a system in which the CPU operates as a master and the peripheral device operates as a slave is constructed. And in such a system, the CPU
Supplies a peripheral device with a serial clock for synchronization, and the CPU selects a slave to be a serial signal transmission / reception partner by a select signal.

FIG. 5 is a block diagram showing an outline of a general three-wire serial interface. Master 10
1 indicates that when the first slave 102 is the transmission / reception partner of the serial signal, the first slave select line 104
The second slave 1 transmits an “high” signal (select signal).
When 02 is the transmission / reception partner of the serial signal, a High signal (select signal) is transmitted to the second slave select line 105. The selected slave obtains a clock from the serial clock line 106 and transmits and receives a serial signal to and from the master 101 via the serial input line 107. Note that a configuration in which transmission and reception of serial signals are performed on separate lines is called a four-line serial interface.

As shown in FIG. 6, when synchronizing the data fetch timing with a clock, a mode based on the falling edge of the clock (mode 1) and a mode based on the rising edge (mode 2) )You could think so. The CPU serving as the master includes a single type in which only one mode is provided, and a dual type in which both modes are provided and either of which can be selected by a register or the like. On the other hand, the slave is given only one of the modes.

[0005]

As described above, the slave is provided with only one of the modes. Therefore, when providing peripheral devices or the like as slaves, there are two models, one for mode 1 and the other for mode 2. Must be prepared. Generally, in the manufacture of these two models, two types of glass masks are prepared in, for example, a metal wiring forming step in the manufacturing process of an IC serving as a central processing unit of the model, and these glass masks are used for the purpose. The method to use for each model,
For example, in a test process after the completion of an IC chip, a method for performing any one of the modes by performing a pad fuse trimming process is adopted. However,
Such a method has a drawback that the manufacturing process is complicated and the manufacturing cost of the device is increased.

An object of the present invention is to provide a clock synchronous serial interface circuit capable of operating a slave connected to a master with any of two types of serial clocks.

[0007]

A clock synchronous serial interface circuit according to the present invention transmits a serial clock from a master to a slave, and the master selects a slave which is a transmission / reception partner of a serial signal by a select signal. A clock synchronous serial interface circuit provided on the slave side, wherein a polarity discriminating circuit for automatically discriminating the polarity of the serial clock transmitted by the master based on the select signal; Clock generating means for generating a serial clock of a type required by the slave from the serial clock received from the master based on the serial clock.

According to the above configuration, whether the slave needs the serial clock of mode 1 irrespective of whether the serial clock transmitted from the master is mode 1 or mode 2, the serial clock of mode 1 is used. Since the clock is generated based on the serial clock transmitted from the master, only the model corresponding to the mode 1 serial clock needs to be manufactured for the slave provided with this interface circuit. And
Since only one kind of slave needs to be manufactured in this way, the manufacturing process can be prevented from becoming complicated, and the cost of the slave can be reduced.

The clock generating means includes a selector for selecting and outputting one of a signal input to a first input terminal and a signal input to a second input terminal based on the result of the determination. Input the serial clock from the master as it is to the first input terminal of
The serial clock from the master may be inverted and input to the second input terminal.

A means may be provided for obtaining a signal obtained by calculating the logical product of the signal obtained by delaying the select signal by a delay element and the serial clock generated from the clock generating means, as a final generated serial clock. With this configuration, even if unwanted noise is present at the beginning of the generated serial clock, the noise can be removed from the final generated serial clock.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a clock synchronous serial interface circuit according to this embodiment, and FIG. 2 is a timing chart showing various signal waveforms at various parts in FIG.

A serial clock polarity discriminating circuit 1 inputs a slave select signal and a serial clock signal sent from a master (not shown), and sets the polarity of the serial clock signal to an edge when the slave select signal becomes active. The determination is automatically performed based on the signal, and the result of the determination is output as a Low or High signal. Specifically, the serial clock polarity discriminating circuit 1 is configured as shown in FIG.
As shown in FIG. 2, when the serial clock signal is Low at the time when the slave select signal rises (active edge) (Mode 1), Low is output as the determination result, while FIG. As shown, when the serial clock signal is High when the slave select signal rises (mode 2),
High is output as the determination result.

The selector 2 has a first input terminal and a second input terminal. The first input terminal receives the serial clock signal as it is, and the second input terminal supplies the serial clock signal to the inverter. The inverted serial clock signal inverted in 3 is input. When the determination result of the serial clock polarity determination circuit 1 is Low, the selector 2 selects and outputs the input signal of the first input terminal, that is, the serial clock signal.
When it is high, the input signal of the second input terminal, that is, the inverted serial clock signal is selected and output.

FIG. 3 shows a specific example of the configuration of FIG.
FIG. 9 is a circuit diagram illustrating a configuration example further including a delay element and an AND circuit. Here, the flip-flop 13 in FIG. 3 corresponds to the serial clock polarity discriminating circuit 1 in FIG. 1, a complex gate composed of two AND circuits 14, 15 and an OR circuit 16 corresponds to the selector 2 in FIG. Reference numeral 17 corresponds to the inverter 3 in FIG.

The data terminal (D terminal) of the flip-flop 13 is connected to the serial clock terminal 11, and the control terminal is connected to the slave select terminal 12. One input terminal of the AND circuit 14 in the complex gate receives an inverted serial clock signal obtained by inverting a serial clock signal by an inverter 17, and the other input terminal receives a Q output of the flip-flop 13. One input terminal of the AND circuit 15 in the complex gate receives the serial clock signal as it is, and the other input terminal receives the QB output of the flip-flop 13. The OR gate 16 of the complex gate ORs the outputs of the AND circuits 14 and 15 and outputs this as a generated serial clock.

One input terminal of the AND circuit 19 is connected to the slave select terminal 12 via the delay element 18, and the other input terminal is connected to the output terminal of the OR circuit 16 of the complex gate. . In other words, the AND circuit 19 is provided with the OR gate 1 of the complex gate and the slave select signal delayed by the delay element 18.
The logical AND with the serial clock generated from step No. 6 is taken and this is output as the final generated serial clock.

As shown in FIG. 4A, when the serial clock signal is low at the time when the slave select signal rises (mode 1), as shown in FIG. 4A, the flip-flop 13 outputs Low as a Q output (determination result). Is output. When the Q output is Low, the QB output is High.
h. AND circuit 14 to which Q output (Low) is input
Continuously outputs Low, and the AND circuit 15 to which the QB output (High) is input outputs a serial clock signal. And the OR circuit 1 of the complex gate
6 outputs the serial clock signal from the AND circuit 15 as a generated serial clock.

Also, the flip-flop 13 is provided in FIG.
As shown in (b), when the serial clock signal is high at the time when the slave select signal rises (mode 2), the Q output (determination result) is Hi.
gh is output. When the Q output is High, Q
The B output becomes Low. The AND circuit 14 receiving the Q output (High) outputs an inverted serial clock signal, and the AND circuit 15 receiving the QB output (Low) outputs the inverted serial clock signal.
ow will continue to be output. Then, the complex gate OR circuit 16 outputs the inverted serial clock signal output from the AND circuit 14 as a generated serial clock.

As described above, when the serial clock transmitted from the master is in mode 1, the clock synchronous serial interface circuit described above uses the serial clock as it is, and the serial clock transmitted from the master is in mode 2. In this case, the serial clock is inverted to be a mode 1 serial clock.
It is only necessary to manufacture only the serial clock compatible model. In other words, there is no need to manufacture two types of slaves, a serial clock compatible model in mode 1 and a serial clock compatible model in mode 2.

In the case where the master outputs, for example, a serial clock of mode 2, if the high of the serial clock of mode 2 occurs slightly after the rising edge of the slave select signal, the OR
An undesired pulse (High) is generated at the beginning of the output (generated clock) of the circuit 16, and this is output as a High level of the clock.
There is a possibility that the slave who mistakenly recognizes that the data fetch timing is wrong (refer to the generated clock in FIG. 4B). In the configuration example of FIG. 3, the logical AND of the delayed slave select signal and the output (generated serial clock) of the OR circuit 16 is taken, the unwanted pulse is removed, and this is output as the final generated clock. As a result, the above-described problems can be prevented.

[0022]

As described above, according to the present invention, even if the master employs any mode of serial clock, only one type of serial clock compatible model needs to be provided as a slave. Can be simplified, and the throughput can be improved, so that the manufacturing cost of the slave can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a clock synchronous serial interface circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing various signal waveforms of each unit in FIG.

FIG. 3 is a circuit diagram showing a specific example of the configuration of FIG. 1 and further including a delay element and an AND circuit;

FIG. 4 is a timing chart showing various signal waveforms of each unit in FIG.

FIG. 5 is an explanatory diagram showing a connection relationship between a master and a slave by a three-wire serial interface.

FIG. 6 is a timing chart showing various signal waveforms of each section in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Serial clock polarity discrimination circuit 2 Selector 3 Inverter 11 Serial clock terminal 12 Slave select terminal 13 Flip-flop 14 AND circuit 15 AND circuit 16 OR circuit 17 Inverter 18 Delay element 19 AND circuit

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Katsunori Yoshinaka 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. (Reference) 5B077 FF11 GG05 GG15 GG16 GG24 GG33 MM01 MM02 NN02 5K034 AA11 FF01 FF04 HH04 HH05 HH07 NN04 PP01

Claims (3)

[Claims] 1. A clock synchronous serial interface circuit provided on a slave side of a system for transmitting a serial clock from a master to a slave, wherein the master selects a slave to be a transmission / reception partner of a serial signal by a select signal. A polarity discriminating circuit for automatically discriminating the polarity of the serial clock transmitted by the master based on the select signal; and a need for the slave from the serial clock received from the master based on the discrimination result of the polarity discriminating circuit. And a clock generating means for generating a serial clock of the following type. 2. The apparatus according to claim 1, wherein the clock generating means includes a selector for selecting and outputting one of a signal input to a first input terminal and a signal input to a second input terminal based on the determination result. 2. The selector according to claim 1, wherein a serial clock from the master is input to a first input terminal of the selector as it is, and a serial clock from the master is inverted and input to a second input terminal. 2. A clock synchronous serial interface circuit according to claim 1. 3. A means for obtaining a logical product of a signal obtained by delaying the select signal by a delay element and a serial clock generated from the clock generating means, and using the signal as a final generated serial clock. 3. A clock synchronous serial interface circuit according to claim 1, wherein