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ITTO20040244A1 - Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore - Google Patents

Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore

Info

Publication number
ITTO20040244A1
ITTO20040244A1 IT000244A ITTO20040244A ITTO20040244A1 IT TO20040244 A1 ITTO20040244 A1 IT TO20040244A1 IT 000244 A IT000244 A IT 000244A IT TO20040244 A ITTO20040244 A IT TO20040244A IT TO20040244 A1 ITTO20040244 A1 IT TO20040244A1
Authority
IT
Italy
Prior art keywords
procedure
manufacture
integrated devices
low thickness
semiconductive
Prior art date
Application number
IT000244A
Other languages
English (en)
Inventor
Riccardo Depetro
Pietro Montanini
Anna Ponza
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000244A priority Critical patent/ITTO20040244A1/it
Publication of ITTO20040244A1 publication Critical patent/ITTO20040244A1/it
Priority to CNB2005800166720A priority patent/CN100474563C/zh
Priority to EP10185628A priority patent/EP2261969A1/en
Priority to PCT/EP2005/051694 priority patent/WO2005104223A1/en
Priority to EP05738025A priority patent/EP1745505B1/en
Priority to US11/584,259 priority patent/US7605015B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Sensors (AREA)
  • Dicing (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
IT000244A 2004-04-20 2004-04-20 Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore ITTO20040244A1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT000244A ITTO20040244A1 (it) 2004-04-20 2004-04-20 Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore
CNB2005800166720A CN100474563C (zh) 2004-04-20 2005-04-18 薄半导体芯片中集成器件的分割工艺
EP10185628A EP2261969A1 (en) 2004-04-20 2005-04-18 Process for the singulation of integrated devices in thin semiconductor chips
PCT/EP2005/051694 WO2005104223A1 (en) 2004-04-20 2005-04-18 Process for the singulation of integrated devices in thin semiconductor chips
EP05738025A EP1745505B1 (en) 2004-04-20 2005-04-18 Process for the singulation of integrated devices in thin semiconductor chips
US11/584,259 US7605015B2 (en) 2004-04-20 2006-10-19 Process for the singulation of integrated devices in thin semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000244A ITTO20040244A1 (it) 2004-04-20 2004-04-20 Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore

Publications (1)

Publication Number Publication Date
ITTO20040244A1 true ITTO20040244A1 (it) 2004-07-20

Family

ID=34966105

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000244A ITTO20040244A1 (it) 2004-04-20 2004-04-20 Procedimento per la fabbricazione di dispositivi integrati in piastrine semiconduttrici a basso spessore

Country Status (5)

Country Link
US (1) US7605015B2 (it)
EP (2) EP2261969A1 (it)
CN (1) CN100474563C (it)
IT (1) ITTO20040244A1 (it)
WO (1) WO2005104223A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2202791B1 (en) * 2005-11-16 2016-01-27 STMicroelectronics Srl Semiconductor device having deep through vias
DE102006059394B4 (de) * 2006-12-08 2019-11-21 Institut Für Mikroelektronik Stuttgart Integrierte Schaltung und Verfahren zu deren Herstellung
WO2007104444A1 (de) 2006-03-14 2007-09-20 Institut Für Mikroelektronik Stuttgart Verfahren zum herstellen einer integrierten schaltung
US7999454B2 (en) 2008-08-14 2011-08-16 Global Oled Technology Llc OLED device with embedded chip driving
US8115380B2 (en) * 2008-08-14 2012-02-14 Global Oled Technology Llc Display device with chiplets
US8916873B2 (en) 2011-09-14 2014-12-23 Infineon Technologies Ag Photodetector with controllable spectral response
US8975715B2 (en) 2011-09-14 2015-03-10 Infineon Technologies Ag Photodetector and method for manufacturing the same
US9003644B2 (en) 2012-10-15 2015-04-14 Stmicroelectronics Pte Ltd PNP apparatus and PNP tool head with direct bonding pressure pick-up tip
DE202014104087U1 (de) * 2014-09-01 2014-09-09 Infineon Technologies Ag Integrierte Schaltung mit Hohlraum-basierter elektrischer Isolation einer Fotodiode
JP6892353B2 (ja) * 2017-08-21 2021-06-23 ローム株式会社 Ｍｅｍｓ検出素子の製造方法およびｍｅｍｓ検出素子

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466630A (en) * 1994-03-21 1995-11-14 United Microelectronics Corp. Silicon-on-insulator technique with buried gap
EP1043770B1 (en) * 1999-04-09 2006-03-01 STMicroelectronics S.r.l. Formation of buried cavities in a monocrystalline semiconductor wafer and a wafer
EP1130631A1 (en) * 2000-02-29 2001-09-05 STMicroelectronics S.r.l. Process for forming a buried cavity in a semiconductor material wafer
US7294536B2 (en) * 2000-07-25 2007-11-13 Stmicroelectronics S.R.L. Process for manufacturing an SOI wafer by annealing and oxidation of buried channels
DE60127148T2 (de) 2001-12-28 2007-12-13 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für SOI Scheibe durch Wärmebehandlung und Oxidation von vergrabenen Kanälen

Also Published As

Publication number Publication date
US7605015B2 (en) 2009-10-20
EP1745505A1 (en) 2007-01-24
US20070141809A1 (en) 2007-06-21
CN1985369A (zh) 2007-06-20
WO2005104223A8 (en) 2006-11-23
EP1745505B1 (en) 2011-08-17
EP2261969A1 (en) 2010-12-15
CN100474563C (zh) 2009-04-01
WO2005104223A1 (en) 2005-11-03

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