ITRM910076A0 - Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento. - Google Patents
Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento.Info
- Publication number
- ITRM910076A0 ITRM910076A0 IT91RM76A ITRM910076A ITRM910076A0 IT RM910076 A0 ITRM910076 A0 IT RM910076A0 IT 91RM76 A IT91RM76 A IT 91RM76A IT RM910076 A ITRM910076 A IT RM910076A IT RM910076 A0 ITRM910076 A0 IT RM910076A0
- Authority
- IT
- Italy
- Prior art keywords
- architecture
- learning process
- neuron network
- network physically
- insertable
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Analogue/Digital Conversion (AREA)
- Image Analysis (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITRM910076A IT1244911B (it) | 1991-01-31 | 1991-01-31 | Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento. |
US07/828,077 US5299286A (en) | 1991-01-31 | 1992-01-30 | Data processing system for implementing architecture of neural network subject to learning process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITRM910076A IT1244911B (it) | 1991-01-31 | 1991-01-31 | Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento. |
Publications (3)
Publication Number | Publication Date |
---|---|
ITRM910076A0 true ITRM910076A0 (it) | 1991-01-31 |
ITRM910076A1 ITRM910076A1 (it) | 1992-07-31 |
IT1244911B IT1244911B (it) | 1994-09-13 |
Family
ID=11399819
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITRM910076A IT1244911B (it) | 1991-01-31 | 1991-01-31 | Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento. |
Country Status (2)
Country | Link |
---|---|
US (1) | US5299286A (it) |
IT (1) | IT1244911B (it) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05210649A (ja) * | 1992-01-24 | 1993-08-20 | Mitsubishi Electric Corp | 神経回路網表現装置 |
US5619619A (en) * | 1993-03-11 | 1997-04-08 | Kabushiki Kaisha Toshiba | Information recognition system and control system using same |
EP0636991A3 (en) * | 1993-07-29 | 1997-01-08 | Matsushita Electric Ind Co Ltd | Information processing device for implementing a neural network. |
KR970007006B1 (ko) * | 1993-08-31 | 1997-05-01 | 한국전자통신연구원 | 인공 신경 회로와 패턴 분리 및 인식용 발진 신경 망의 구조 |
US5486999A (en) * | 1994-04-20 | 1996-01-23 | Mebane; Andrew H. | Apparatus and method for categorizing health care utilization |
US5781702A (en) * | 1995-06-07 | 1998-07-14 | Univ South Western | Hybrid chip-set architecture for artificial neural network system |
DE69518326T2 (de) | 1995-10-13 | 2001-01-18 | Stmicroelectronics S.R.L., Agrate Brianza | Niederspannungsneuronalnetzwerk mit sehr niedrigem Leistungsverbrauch |
US5740023A (en) * | 1996-05-24 | 1998-04-14 | Lucent Technologies Inc. | Control system for a modular power supply and method of operation thereof |
US6389404B1 (en) * | 1998-12-30 | 2002-05-14 | Irvine Sensors Corporation | Neural processing module with input architectures that make maximal use of a weighted synapse array |
US8463723B2 (en) * | 2009-03-01 | 2013-06-11 | International Business Machines Corporation | Electronic synapse |
US7978510B2 (en) | 2009-03-01 | 2011-07-12 | International Businesss Machines Corporation | Stochastic synapse memory element with spike-timing dependent plasticity (STDP) |
US8510244B2 (en) | 2009-03-20 | 2013-08-13 | ISC8 Inc. | Apparatus comprising artificial neuronal assembly |
US8275727B2 (en) * | 2009-11-13 | 2012-09-25 | International Business Machines Corporation | Hardware analog-digital neural networks |
US8676734B2 (en) * | 2010-07-07 | 2014-03-18 | Qualcomm, Incorporated | Methods and systems for replaceable synaptic weight storage in neuro-processors |
US8515885B2 (en) | 2010-10-29 | 2013-08-20 | International Business Machines Corporation | Neuromorphic and synaptronic spiking neural network with synaptic weights learned using simulation |
US8892487B2 (en) | 2010-12-30 | 2014-11-18 | International Business Machines Corporation | Electronic synapses for reinforcement learning |
US8918351B2 (en) | 2012-07-30 | 2014-12-23 | International Business Machines Corporation | Providing transposable access to a synapse array using column aggregation |
US9218564B2 (en) | 2012-07-30 | 2015-12-22 | International Business Machines Corporation | Providing transposable access to a synapse array using a recursive array layout |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8619452D0 (en) * | 1986-08-08 | 1986-12-17 | Dobson V G | Signal generating & processing |
FR2644264B1 (fr) * | 1989-03-10 | 1991-05-10 | Thomson Csf | Reseau neuronal analogique programmable |
US5148514A (en) * | 1989-05-15 | 1992-09-15 | Mitsubishi Denki Kabushiki Kaisha | Neural network integrated circuit device having self-organizing function |
US5146542A (en) * | 1989-06-15 | 1992-09-08 | General Electric Company | Neural net using capacitive structures connecting output lines and differentially driven input line pairs |
US5039871A (en) * | 1990-05-21 | 1991-08-13 | General Electric Company | Capacitive structures for weighted summation as used in neural nets |
US5039870A (en) * | 1990-05-21 | 1991-08-13 | General Electric Company | Weighted summation circuits having different-weight ranks of capacitive structures |
US5140531A (en) * | 1990-08-01 | 1992-08-18 | General Electric Company | Analog neural nets supplied digital synapse signals on a bit-slice basis |
US5065132A (en) * | 1990-11-16 | 1991-11-12 | Texas Instruments Incorporated | Programmable resistor and an array of the same |
-
1991
- 1991-01-31 IT ITRM910076A patent/IT1244911B/it active IP Right Grant
-
1992
- 1992-01-30 US US07/828,077 patent/US5299286A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ITRM910076A1 (it) | 1992-07-31 |
US5299286A (en) | 1994-03-29 |
IT1244911B (it) | 1994-09-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19960119 |