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ITMI912235A0 - Metodo per formare un micromodello sotto il imite di risoluzione di un processo fotolitografico - Google Patents

Metodo per formare un micromodello sotto il imite di risoluzione di un processo fotolitografico

Info

Publication number
ITMI912235A0
ITMI912235A0 IT91MI2235A ITMI912235A ITMI912235A0 IT MI912235 A0 ITMI912235 A0 IT MI912235A0 IT 91MI2235 A IT91MI2235 A IT 91MI2235A IT MI912235 A ITMI912235 A IT MI912235A IT MI912235 A0 ITMI912235 A0 IT MI912235A0
Authority
IT
Italy
Prior art keywords
micromodel
forming
under
resolution limit
photolithographic process
Prior art date
Application number
IT91MI2235A
Other languages
English (en)
Inventor
Woo-Sung Han
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912235A0 publication Critical patent/ITMI912235A0/it
Publication of ITMI912235A1 publication Critical patent/ITMI912235A1/it
Application granted granted Critical
Publication of IT1251004B publication Critical patent/IT1251004B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/40Treatment after imagewise removal, e.g. baking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
ITMI912235A 1991-01-30 1991-08-09 Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico IT1251004B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001578A KR920015482A (ko) 1991-01-30 1991-01-30 광리소그라피의 한계해상도 이하의 미세패턴 형성방법

Publications (3)

Publication Number Publication Date
ITMI912235A0 true ITMI912235A0 (it) 1991-08-09
ITMI912235A1 ITMI912235A1 (it) 1993-02-09
IT1251004B IT1251004B (it) 1995-04-28

Family

ID=19310487

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912235A IT1251004B (it) 1991-01-30 1991-08-09 Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico

Country Status (6)

Country Link
JP (1) JPH04249311A (it)
KR (1) KR920015482A (it)
DE (1) DE4126635A1 (it)
FR (1) FR2672138A1 (it)
GB (1) GB2252449A (it)
IT (1) IT1251004B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (de) * 1992-10-29 1994-05-05 Siemens Ag Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats
DE4440230C2 (de) * 1993-11-10 1999-03-18 Hyundai Electronics Ind Verfahren zur Bildung feiner Strukturen eines Halbleiterbauelements
KR100229611B1 (ko) 1996-06-12 1999-11-15 구자홍 액정표시장치의 제조방법
JP2000156377A (ja) * 1998-11-19 2000-06-06 Murata Mfg Co Ltd レジストパターン及びその形成方法並びに配線パターンの形成方法
JP5655443B2 (ja) * 2010-09-06 2015-01-21 住友電気工業株式会社 無機化合物膜のエッチング方法および半導体光素子の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
JPS63114214A (ja) * 1986-09-11 1988-05-19 フェアチャイルド セミコンダクタ コーポレーション 二層マスクを使用するプラズマエッチング
US4878993A (en) * 1988-12-22 1989-11-07 North American Philips Corporation Method of etching thin indium tin oxide films

Also Published As

Publication number Publication date
GB2252449A (en) 1992-08-05
ITMI912235A1 (it) 1993-02-09
JPH04249311A (ja) 1992-09-04
FR2672138A1 (fr) 1992-07-31
GB9117267D0 (en) 1991-09-25
KR920015482A (ko) 1992-08-27
IT1251004B (it) 1995-04-28
DE4126635A1 (de) 1992-08-13

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Legal Events

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0001 Granted