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ITMI20002018A0 - Circuito di lettura per memorie non volatili a semiconduttore. - Google Patents

Circuito di lettura per memorie non volatili a semiconduttore.

Info

Publication number
ITMI20002018A0
ITMI20002018A0 IT2000MI002018A ITMI20002018A ITMI20002018A0 IT MI20002018 A0 ITMI20002018 A0 IT MI20002018A0 IT 2000MI002018 A IT2000MI002018 A IT 2000MI002018A IT MI20002018 A ITMI20002018 A IT MI20002018A IT MI20002018 A0 ITMI20002018 A0 IT MI20002018A0
Authority
IT
Italy
Prior art keywords
reading circuit
volatile memories
semiconductor non
semiconductor
memories
Prior art date
Application number
IT2000MI002018A
Other languages
English (en)
Inventor
Osama Khouri
Guido Torelli
Alessandro Manstretta
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000MI002018A priority Critical patent/IT1318892B1/it
Publication of ITMI20002018A0 publication Critical patent/ITMI20002018A0/it
Priority to US09/953,070 priority patent/US6563737B2/en
Publication of ITMI20002018A1 publication Critical patent/ITMI20002018A1/it
Application granted granted Critical
Publication of IT1318892B1 publication Critical patent/IT1318892B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
IT2000MI002018A 2000-09-15 2000-09-15 Circuito di lettura per memorie non volatili a semiconduttore. IT1318892B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000MI002018A IT1318892B1 (it) 2000-09-15 2000-09-15 Circuito di lettura per memorie non volatili a semiconduttore.
US09/953,070 US6563737B2 (en) 2000-09-15 2001-09-13 Reading circuit for semiconductor non-volatile memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000MI002018A IT1318892B1 (it) 2000-09-15 2000-09-15 Circuito di lettura per memorie non volatili a semiconduttore.

Publications (3)

Publication Number Publication Date
ITMI20002018A0 true ITMI20002018A0 (it) 2000-09-15
ITMI20002018A1 ITMI20002018A1 (it) 2002-03-15
IT1318892B1 IT1318892B1 (it) 2003-09-19

Family

ID=11445809

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000MI002018A IT1318892B1 (it) 2000-09-15 2000-09-15 Circuito di lettura per memorie non volatili a semiconduttore.

Country Status (2)

Country Link
US (1) US6563737B2 (it)
IT (1) IT1318892B1 (it)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1251523B1 (en) * 2001-04-19 2007-08-15 STMicroelectronics S.r.l. Method and circuit for timing dynamic reading of a memory cell with control of the integration time
US6665216B1 (en) * 2002-07-23 2003-12-16 Macronix International Co., Ltd. Apparatus and system for reading non-volatile memory with dual reference cells
US7324393B2 (en) * 2002-09-24 2008-01-29 Sandisk Corporation Method for compensated sensing in non-volatile memory
JP2004220711A (ja) * 2003-01-16 2004-08-05 Nec Micro Systems Ltd 半導体集積回路装置
KR100517561B1 (ko) * 2003-08-19 2005-09-28 삼성전자주식회사 불 휘발성 반도체 메모리 장치
JP4167567B2 (ja) * 2003-09-01 2008-10-15 松下電器産業株式会社 半導体集積回路装置及びその検査方法
JP2005259330A (ja) * 2004-02-09 2005-09-22 Sharp Corp バイアス電圧印加回路及び半導体記憶装置
KR100558571B1 (ko) * 2004-03-03 2006-03-13 삼성전자주식회사 반도체 메모리 장치의 전류 센스앰프 회로
TWI247311B (en) * 2004-03-25 2006-01-11 Elite Semiconductor Esmt Circuit and method for preventing nonvolatile memory from over erasure
JP2006179109A (ja) * 2004-12-22 2006-07-06 Matsushita Electric Ind Co Ltd メモリ回路
ITMI20042538A1 (it) * 2004-12-29 2005-03-29 Atmel Corp Metodo e sistema per la riduzione del soft-writing in una memoria flash a livelli multipli
JP4772363B2 (ja) * 2005-04-12 2011-09-14 株式会社東芝 不揮発性半導体記憶装置
DE102006017480B4 (de) * 2006-04-13 2008-11-27 Austriamicrosystems Ag Schaltungsanordnung mit einer nicht-flüchtigen Speicherzelle und Verfahren
US7859906B1 (en) * 2007-03-30 2010-12-28 Cypress Semiconductor Corporation Circuit and method to increase read margin in non-volatile memories using a differential sensing circuit
US7724595B2 (en) * 2008-01-08 2010-05-25 Macronix International Co., Ltd. Current-mode sense amplifier and sense amplifying method
CN101425339B (zh) * 2008-12-05 2010-12-29 上海贝岭股份有限公司 一种大容量eeprom存储器读放电路
US8385147B2 (en) * 2010-03-30 2013-02-26 Silicon Storage Technology, Inc. Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
KR102619682B1 (ko) * 2016-12-13 2023-12-28 삼성전자주식회사 메모리 장치 및 그 동작 방법
CN112071341B (zh) * 2020-08-31 2022-12-06 上海华虹宏力半导体制造有限公司 感测放大器电路结构

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0678874B1 (en) * 1994-04-19 2000-07-26 STMicroelectronics S.r.l. Memory array cell reading circuit

Also Published As

Publication number Publication date
US6563737B2 (en) 2003-05-13
US20020057604A1 (en) 2002-05-16
IT1318892B1 (it) 2003-09-19
ITMI20002018A1 (it) 2002-03-15

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