IT998866B - Procedimento per produrre struttu re a piu strati metallo isolatore semiconduttore - Google Patents
Procedimento per produrre struttu re a piu strati metallo isolatore semiconduttoreInfo
- Publication number
- IT998866B IT998866B IT30438/73A IT3043873A IT998866B IT 998866 B IT998866 B IT 998866B IT 30438/73 A IT30438/73 A IT 30438/73A IT 3043873 A IT3043873 A IT 3043873A IT 998866 B IT998866 B IT 998866B
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- metal structure
- layer metal
- producing multi
- structure semiconductor
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title 1
- 239000002184 metal Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP47107222A JPS5910073B2 (ja) | 1972-10-27 | 1972-10-27 | シリコン・ゲ−トmos型半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
IT998866B true IT998866B (it) | 1976-02-20 |
Family
ID=14453572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT30438/73A IT998866B (it) | 1972-10-27 | 1973-10-23 | Procedimento per produrre struttu re a piu strati metallo isolatore semiconduttore |
Country Status (10)
Country | Link |
---|---|
US (1) | US3906620A (it) |
JP (1) | JPS5910073B2 (it) |
CA (1) | CA1032659A (it) |
DE (1) | DE2352331A1 (it) |
FR (1) | FR2204892B1 (it) |
GB (1) | GB1428713A (it) |
HK (1) | HK30179A (it) |
IT (1) | IT998866B (it) |
MY (1) | MY7900036A (it) |
NL (1) | NL179434C (it) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2554450A1 (de) * | 1975-12-03 | 1977-06-16 | Siemens Ag | Verfahren zur herstellung einer integrierten schaltung |
JPS5293278A (en) * | 1976-01-30 | 1977-08-05 | Matsushita Electronics Corp | Manufacture for mos type semiconductor intergrated circuit |
IT1089299B (it) * | 1977-01-26 | 1985-06-18 | Mostek Corp | Procedimento per fabbricare un dispositivo semiconduttore |
US4553314B1 (en) * | 1977-01-26 | 2000-04-18 | Sgs Thomson Microelectronics | Method for making a semiconductor device |
DE2858815C2 (de) * | 1977-01-26 | 1996-01-18 | Sgs Thomson Microelectronics | Verfahren zur Ausbildung eines Feldeffekttransistors in einer Halbleitervorrichtung |
US4259779A (en) * | 1977-08-24 | 1981-04-07 | Rca Corporation | Method of making radiation resistant MOS transistor |
US4240196A (en) * | 1978-12-29 | 1980-12-23 | Bell Telephone Laboratories, Incorporated | Fabrication of two-level polysilicon devices |
DE2902665A1 (de) * | 1979-01-24 | 1980-08-07 | Siemens Ag | Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie |
US4287661A (en) * | 1980-03-26 | 1981-09-08 | International Business Machines Corporation | Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation |
US4667395A (en) * | 1985-03-29 | 1987-05-26 | International Business Machines Corporation | Method for passivating an undercut in semiconductor device preparation |
JPH01235254A (ja) * | 1988-03-15 | 1989-09-20 | Nec Corp | 半導体装置及びその製造方法 |
US5550069A (en) * | 1990-06-23 | 1996-08-27 | El Mos Electronik In Mos Technologie Gmbh | Method for producing a PMOS transistor |
US6780718B2 (en) * | 1993-11-30 | 2004-08-24 | Stmicroelectronics, Inc. | Transistor structure and method for making same |
KR970003837B1 (en) * | 1993-12-16 | 1997-03-22 | Lg Semicon Co Ltd | Fabrication of mosfet |
JP2001291861A (ja) * | 2000-04-05 | 2001-10-19 | Nec Corp | Mosトランジスタ、トランジスタ製造方法 |
US8435873B2 (en) | 2006-06-08 | 2013-05-07 | Texas Instruments Incorporated | Unguarded Schottky barrier diodes with dielectric underetch at silicide interface |
KR101163224B1 (ko) * | 2011-02-15 | 2012-07-06 | 에스케이하이닉스 주식회사 | 듀얼 폴리게이트 형성방법 및 이를 이용한 반도체소자의 제조방법 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB967002A (en) * | 1961-05-05 | 1964-08-19 | Standard Telephones Cables Ltd | Improvements in or relating to semiconductor devices |
NL131898C (it) * | 1965-03-26 | |||
NL6617141A (it) * | 1966-02-11 | 1967-08-14 | Siemens Ag | |
US3764865A (en) * | 1970-03-17 | 1973-10-09 | Rca Corp | Semiconductor devices having closely spaced contacts |
US3798752A (en) * | 1971-03-11 | 1974-03-26 | Nippon Electric Co | Method of producing a silicon gate insulated-gate field effect transistor |
CA910506A (en) * | 1971-06-25 | 1972-09-19 | Bell Canada-Northern Electric Research Limited | Modification of channel regions in insulated gate field effect transistors |
US3775191A (en) * | 1971-06-28 | 1973-11-27 | Bell Canada Northern Electric | Modification of channel regions in insulated gate field effect transistors |
JPS5340762B2 (it) * | 1974-07-22 | 1978-10-28 |
-
1972
- 1972-10-27 JP JP47107222A patent/JPS5910073B2/ja not_active Expired
-
1973
- 1973-10-04 FR FR7335486A patent/FR2204892B1/fr not_active Expired
- 1973-10-18 GB GB4869573A patent/GB1428713A/en not_active Expired
- 1973-10-18 DE DE19732352331 patent/DE2352331A1/de not_active Withdrawn
- 1973-10-23 NL NLAANVRAGE7314576,A patent/NL179434C/xx not_active IP Right Cessation
- 1973-10-23 IT IT30438/73A patent/IT998866B/it active
- 1973-10-26 CA CA184,345A patent/CA1032659A/en not_active Expired
- 1973-10-29 US US410445A patent/US3906620A/en not_active Expired - Lifetime
-
1979
- 1979-05-10 HK HK301/79A patent/HK30179A/xx unknown
- 1979-12-30 MY MY36/79A patent/MY7900036A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
FR2204892A1 (it) | 1974-05-24 |
NL7314576A (it) | 1974-05-01 |
JPS5910073B2 (ja) | 1984-03-06 |
MY7900036A (en) | 1979-12-31 |
HK30179A (en) | 1979-05-18 |
GB1428713A (en) | 1976-03-17 |
CA1032659A (en) | 1978-06-06 |
NL179434B (nl) | 1986-04-01 |
JPS4966074A (it) | 1974-06-26 |
US3906620A (en) | 1975-09-23 |
DE2352331A1 (de) | 1974-05-16 |
NL179434C (nl) | 1986-09-01 |
FR2204892B1 (it) | 1976-10-01 |
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