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IT1313401B1 - Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test. - Google Patents

Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test.

Info

Publication number
IT1313401B1
IT1313401B1 IT1999VA000035A ITVA990035A IT1313401B1 IT 1313401 B1 IT1313401 B1 IT 1313401B1 IT 1999VA000035 A IT1999VA000035 A IT 1999VA000035A IT VA990035 A ITVA990035 A IT VA990035A IT 1313401 B1 IT1313401 B1 IT 1313401B1
Authority
IT
Italy
Prior art keywords
management
test structure
scan test
integrated fuse
fuse trimming
Prior art date
Application number
IT1999VA000035A
Other languages
English (en)
Inventor
Giuseppe Cantone
Roberto Cappelletti
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999VA000035A priority Critical patent/IT1313401B1/it
Publication of ITVA990035A0 publication Critical patent/ITVA990035A0/it
Priority to US09/718,078 priority patent/US6675360B1/en
Publication of ITVA990035A1 publication Critical patent/ITVA990035A1/it
Application granted granted Critical
Publication of IT1313401B1 publication Critical patent/IT1313401B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fuses (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
IT1999VA000035A 1999-11-23 1999-11-23 Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test. IT1313401B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1999VA000035A IT1313401B1 (it) 1999-11-23 1999-11-23 Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test.
US09/718,078 US6675360B1 (en) 1999-11-23 2000-11-21 System of management of the trimming of integrated fuses within a scan test architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999VA000035A IT1313401B1 (it) 1999-11-23 1999-11-23 Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test.

Publications (3)

Publication Number Publication Date
ITVA990035A0 ITVA990035A0 (it) 1999-11-23
ITVA990035A1 ITVA990035A1 (it) 2001-05-23
IT1313401B1 true IT1313401B1 (it) 2002-07-23

Family

ID=11423547

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999VA000035A IT1313401B1 (it) 1999-11-23 1999-11-23 Sistema per la gestione del trimming di fusibili integrati inserito in una struttura di scan test.

Country Status (2)

Country Link
US (1) US6675360B1 (it)
IT (1) IT1313401B1 (it)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7100061B2 (en) * 2000-01-18 2006-08-29 Transmeta Corporation Adaptive power control
US7941675B2 (en) 2002-12-31 2011-05-10 Burr James B Adaptive power control
US7112978B1 (en) 2002-04-16 2006-09-26 Transmeta Corporation Frequency specific closed loop feedback control of integrated circuits
US6792379B2 (en) * 2002-04-24 2004-09-14 Yoshiyuki Ando Data-based control of integrated circuits
US7228242B2 (en) * 2002-12-31 2007-06-05 Transmeta Corporation Adaptive power control based on pre package characterization of integrated circuits
US7953990B2 (en) 2002-12-31 2011-05-31 Stewart Thomas E Adaptive power control based on post package characterization of integrated circuits
US7692477B1 (en) 2003-12-23 2010-04-06 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US7129771B1 (en) 2003-12-23 2006-10-31 Transmeta Corporation Servo loop for well bias voltage source
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7012461B1 (en) 2003-12-23 2006-03-14 Transmeta Corporation Stabilization component for a substrate potential regulation circuit
US7562233B1 (en) 2004-06-22 2009-07-14 Transmeta Corporation Adaptive control of operating and body bias voltages
US7774625B1 (en) 2004-06-22 2010-08-10 Eric Chien-Li Sheng Adaptive voltage control by accessing information stored within and specific to a microprocessor
US7631232B2 (en) * 2007-09-28 2009-12-08 Inventec Corporation Parallel burning system and method
EP2687738B1 (en) 2012-07-20 2015-09-09 Aktiebolaget SKF Angular contact bearing assembly for use in a steering column and method for assembling a steering column
EP2687739A1 (en) 2012-07-20 2014-01-22 Aktiebolaget SKF Angular contact bearing assembly for use in a steering column
EP2687421B1 (en) 2012-07-20 2015-03-04 Aktiebolaget SKF Angular contact ball bearing assembly for use in a steering column
FR3018137A1 (it) * 2014-03-03 2015-09-04 St Microelectronics Grenoble 2
CN104698364A (zh) * 2015-02-28 2015-06-10 上海华虹宏力半导体制造有限公司 一种自动配平电路
US12002751B2 (en) * 2020-10-29 2024-06-04 Changxin Memory Technologies, Inc. Adjustment method and device for chip output characteristics

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0185611B1 (ko) * 1995-12-11 1999-04-15 김광호 불휘발성 반도체 메모리장치의 고전압 레벨 최적화 회로 및 그 방법
US6134148A (en) * 1997-09-30 2000-10-17 Hitachi, Ltd. Semiconductor integrated circuit and data processing system
JP3398564B2 (ja) * 1997-04-11 2003-04-21 富士通株式会社 半導体装置
US6072349A (en) * 1997-12-31 2000-06-06 Intel Corporation Comparator
US6006169A (en) * 1997-12-31 1999-12-21 Intel Corporation Method and apparatus for trimming an integrated circuit
JP4587500B2 (ja) * 1998-11-11 2010-11-24 ルネサスエレクトロニクス株式会社 半導体集積回路、メモリモジュール、記憶媒体、及び半導体集積回路の救済方法
DE69910566T2 (de) * 1999-09-14 2004-06-24 Stmicroelectronics S.R.L., Agrate Brianza Elektronische integrierte Schaltung mit Trimmmittel und Verfahren dafür

Also Published As

Publication number Publication date
ITVA990035A0 (it) 1999-11-23
US6675360B1 (en) 2004-01-06
ITVA990035A1 (it) 2001-05-23

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