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IT1276042B1 - Dispositivo a circuito integrato e metodo per produrre lo stesso - Google Patents

Dispositivo a circuito integrato e metodo per produrre lo stesso

Info

Publication number
IT1276042B1
IT1276042B1 IT93MI002681A ITMI932681A IT1276042B1 IT 1276042 B1 IT1276042 B1 IT 1276042B1 IT 93MI002681 A IT93MI002681 A IT 93MI002681A IT MI932681 A ITMI932681 A IT MI932681A IT 1276042 B1 IT1276042 B1 IT 1276042B1
Authority
IT
Italy
Prior art keywords
memory electrode
integrated circuit
circuit device
substrate
opening
Prior art date
Application number
IT93MI002681A
Other languages
English (en)
Inventor
Hashimoto Koichi
Ema Taiji
Matsunaga Daisuke
Hashimi Kazuo
Ohtsuka Toshiyuki
Shinpuku Fumihiko
Kawaguchi Kazushi
Miyazawa Hisashi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ITMI932681A0 publication Critical patent/ITMI932681A0/it
Publication of ITMI932681A1 publication Critical patent/ITMI932681A1/it
Application granted granted Critical
Publication of IT1276042B1 publication Critical patent/IT1276042B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In un metodo per produrre un dispositivo a circuito integrato, viene formata una struttura a strati sovrapposti su una pellicola isolante su un substrato, la struttura a strati sovrapposti comprende una o una pluralità di pellicole di spazi e una o una pluralità di prime pellicole conduttive contenenti silicio. Viene formata un'apertura nella struttura a strati sovrapposti, l'apertura è parte di un foro per un contatto di elettrodo di memoria. La pellicola isolante sul substrato viene incisa attraverso l'apertura così il substrato viene parzialmente esposto attraverso il foro di contatto per elettrodo di memoria. Viene formata una seconda pellicola conduttiva contenenti silicio su una superficie comprendente il foro di contatto per elettrodo di memoria. La seconda pellicola conduttiva e la struttura a strati sovrapposti sono modellate, e in seguito viene apportata una pellicola o la pluralità di pellicole di spazi, così viene realizzato un elettrodo di memoria comprendente una parte di tronco posizionata nel foro di contatto per elettrodo di memoria, ed almeno una aletta che si estende dalla parte di tronco (Figura 1).
IT93MI002681A 1992-12-22 1993-12-21 Dispositivo a circuito integrato e metodo per produrre lo stesso IT1276042B1 (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34175992 1992-12-22
JP5148119A JPH06244377A (ja) 1992-12-22 1993-06-18 集積回路装置及びその製造方法

Publications (3)

Publication Number Publication Date
ITMI932681A0 ITMI932681A0 (it) 1993-12-21
ITMI932681A1 ITMI932681A1 (it) 1995-06-21
IT1276042B1 true IT1276042B1 (it) 1997-10-24

Family

ID=26478442

Family Applications (1)

Application Number Title Priority Date Filing Date
IT93MI002681A IT1276042B1 (it) 1992-12-22 1993-12-21 Dispositivo a circuito integrato e metodo per produrre lo stesso

Country Status (3)

Country Link
JP (1) JPH06244377A (it)
KR (1) KR940016838A (it)
IT (1) IT1276042B1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100295656B1 (ko) * 1997-09-12 2001-08-07 김영환 반도체메모리제조방법
JP4650153B2 (ja) * 2005-08-05 2011-03-16 セイコーエプソン株式会社 電気光学装置、電子機器及び電気光学装置の製造方法

Also Published As

Publication number Publication date
JPH06244377A (ja) 1994-09-02
ITMI932681A0 (it) 1993-12-21
ITMI932681A1 (it) 1995-06-21
KR940016838A (ko) 1994-07-25

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961220